diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/bus_gk20a.c | 44 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 |
8 files changed, 41 insertions, 22 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c index b2800772..60481544 100644 --- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -65,7 +65,7 @@ void gk20a_bus_init_hw(struct gk20a *g) | |||
65 | 65 | ||
66 | void gk20a_bus_isr(struct gk20a *g) | 66 | void gk20a_bus_isr(struct gk20a *g) |
67 | { | 67 | { |
68 | u32 val, save0, save1, err_code; | 68 | u32 val, save0, save1, fecs_errcode = 0; |
69 | 69 | ||
70 | val = gk20a_readl(g, bus_intr_0_r()); | 70 | val = gk20a_readl(g, bus_intr_0_r()); |
71 | 71 | ||
@@ -78,29 +78,37 @@ void gk20a_bus_isr(struct gk20a *g) | |||
78 | 78 | ||
79 | save0 = gk20a_readl(g, timer_pri_timeout_save_0_r()); | 79 | save0 = gk20a_readl(g, timer_pri_timeout_save_0_r()); |
80 | if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) { | 80 | if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) { |
81 | 81 | /* | |
82 | err_code = gk20a_readl(g, | 82 | * write & addr fields in timeout_save0 |
83 | * might not be reliable | ||
84 | */ | ||
85 | fecs_errcode = gk20a_readl(g, | ||
83 | timer_pri_timeout_fecs_errcode_r()); | 86 | timer_pri_timeout_fecs_errcode_r()); |
84 | /* write and addr fields are not reliable */ | 87 | } |
85 | nvgpu_err(g, "NV_PBUS_INTR_0: 0x%08x " | 88 | |
86 | "FECS_ERRCODE 0x%08x", val, err_code); | 89 | save1 = gk20a_readl(g, timer_pri_timeout_save_1_r()); |
90 | nvgpu_err(g, "NV_PBUS_INTR_0: 0x%08x ADR 0x%08x " | ||
91 | "%s DATA 0x%08x ", | ||
92 | val, | ||
93 | timer_pri_timeout_save_0_addr_v(save0) << 2, | ||
94 | timer_pri_timeout_save_0_write_v(save0) ? | ||
95 | "WRITE" : "READ", save1); | ||
87 | 96 | ||
88 | if ((err_code & 0xffffff00) == 0xbadf1300) | 97 | gk20a_writel(g, timer_pri_timeout_save_0_r(), 0); |
98 | gk20a_writel(g, timer_pri_timeout_save_1_r(), 0); | ||
99 | |||
100 | if (fecs_errcode) { | ||
101 | nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode); | ||
102 | if (g->ops.priv_ring.decode_error_code) | ||
103 | g->ops.priv_ring.decode_error_code(g, | ||
104 | fecs_errcode); | ||
105 | |||
106 | if ((fecs_errcode & 0xffffff00) == 0xbadf1300) | ||
89 | nvgpu_err(g, "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: " | 107 | nvgpu_err(g, "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: " |
90 | "0x%08x", | 108 | "0x%08x", |
91 | gk20a_readl(g, gr_gpc0_fs_gpc_r())); | 109 | gk20a_readl(g, gr_gpc0_fs_gpc_r())); |
92 | } else { | ||
93 | save1 = gk20a_readl(g, timer_pri_timeout_save_1_r()); | ||
94 | nvgpu_err(g, "NV_PBUS_INTR_0: 0x%08x ADR 0x%08x " | ||
95 | "R/W %s DATA 0x%08x", | ||
96 | val, | ||
97 | timer_pri_timeout_save_0_addr_v(save0) << 2, | ||
98 | timer_pri_timeout_save_0_write_v(save0) ? | ||
99 | "WRITE" : "READ", save1); | ||
100 | } | 110 | } |
101 | 111 | ||
102 | gk20a_writel(g, timer_pri_timeout_save_0_r(), 0); | ||
103 | gk20a_writel(g, timer_pri_timeout_save_1_r(), 0); | ||
104 | } else { | 112 | } else { |
105 | nvgpu_err(g, "Unhandled NV_PBUS_INTR_0: 0x%08x", val); | 113 | nvgpu_err(g, "Unhandled NV_PBUS_INTR_0: 0x%08x", val); |
106 | } | 114 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 95736d30..7162dc73 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1113,6 +1113,7 @@ struct gpu_ops { | |||
1113 | } falcon; | 1113 | } falcon; |
1114 | struct { | 1114 | struct { |
1115 | void (*isr)(struct gk20a *g); | 1115 | void (*isr)(struct gk20a *g); |
1116 | void (*decode_error_code)(struct gk20a *g, u32 error_code); | ||
1116 | } priv_ring; | 1117 | } priv_ring; |
1117 | struct { | 1118 | struct { |
1118 | int (*check_priv_security)(struct gk20a *g); | 1119 | int (*check_priv_security)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index dbea8033..bfd1e99a 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -49,6 +49,7 @@ | |||
49 | #include "gp10b/fb_gp10b.h" | 49 | #include "gp10b/fb_gp10b.h" |
50 | #include "gp10b/pmu_gp10b.h" | 50 | #include "gp10b/pmu_gp10b.h" |
51 | #include "gp10b/gr_gp10b.h" | 51 | #include "gp10b/gr_gp10b.h" |
52 | #include "gp10b/priv_ring_gp10b.h" | ||
52 | 53 | ||
53 | #include "gp106/fifo_gp106.h" | 54 | #include "gp106/fifo_gp106.h" |
54 | #include "gp106/regops_gp106.h" | 55 | #include "gp106/regops_gp106.h" |
@@ -729,6 +730,7 @@ static const struct gpu_ops gp106_ops = { | |||
729 | }, | 730 | }, |
730 | .priv_ring = { | 731 | .priv_ring = { |
731 | .isr = gp10b_priv_ring_isr, | 732 | .isr = gp10b_priv_ring_isr, |
733 | .decode_error_code = gp10b_priv_ring_decode_error_code, | ||
732 | }, | 734 | }, |
733 | .fuse = { | 735 | .fuse = { |
734 | .check_priv_security = gp106_fuse_check_priv_security, | 736 | .check_priv_security = gp106_fuse_check_priv_security, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index dd413c5a..a6a66f93 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -646,6 +646,7 @@ static const struct gpu_ops gp10b_ops = { | |||
646 | }, | 646 | }, |
647 | .priv_ring = { | 647 | .priv_ring = { |
648 | .isr = gp10b_priv_ring_isr, | 648 | .isr = gp10b_priv_ring_isr, |
649 | .decode_error_code = gp10b_priv_ring_decode_error_code, | ||
649 | }, | 650 | }, |
650 | .fuse = { | 651 | .fuse = { |
651 | .check_priv_security = gp10b_fuse_check_priv_security, | 652 | .check_priv_security = gp10b_fuse_check_priv_security, |
diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c index 0fac76f2..12cd2a84 100644 --- a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c | |||
@@ -64,7 +64,7 @@ static const char *const error_type_badf5xyy[] = { | |||
64 | "pri route error" | 64 | "pri route error" |
65 | }; | 65 | }; |
66 | 66 | ||
67 | static void gp10b_priv_ring_decode_error_code(struct gk20a *g, | 67 | void gp10b_priv_ring_decode_error_code(struct gk20a *g, |
68 | u32 error_code) | 68 | u32 error_code) |
69 | { | 69 | { |
70 | u32 error_type, error_type_index; | 70 | u32 error_type, error_type_index; |
@@ -141,7 +141,8 @@ void gp10b_priv_ring_isr(struct gk20a *g) | |||
141 | pri_ringstation_sys_priv_error_info_subid_v(error_info), | 141 | pri_ringstation_sys_priv_error_info_subid_v(error_info), |
142 | pri_ringstation_sys_priv_error_info_priv_level_v(error_info), | 142 | pri_ringstation_sys_priv_error_info_priv_level_v(error_info), |
143 | error_code); | 143 | error_code); |
144 | gp10b_priv_ring_decode_error_code(g, error_code); | 144 | if (g->ops.priv_ring.decode_error_code) |
145 | g->ops.priv_ring.decode_error_code(g, error_code); | ||
145 | } | 146 | } |
146 | 147 | ||
147 | if (status1) { | 148 | if (status1) { |
@@ -166,7 +167,9 @@ void gp10b_priv_ring_isr(struct gk20a *g) | |||
166 | pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info), | 167 | pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info), |
167 | error_code); | 168 | error_code); |
168 | 169 | ||
169 | gp10b_priv_ring_decode_error_code(g, error_code); | 170 | if (g->ops.priv_ring.decode_error_code) |
171 | g->ops.priv_ring.decode_error_code(g, | ||
172 | error_code); | ||
170 | 173 | ||
171 | status1 = status1 & (~(BIT(gpc))); | 174 | status1 = status1 & (~(BIT(gpc))); |
172 | if (!status1) | 175 | if (!status1) |
diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h index 5b004a58..dd418e5b 100644 --- a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B PRIV ringmaster | 2 | * GP10B PRIV ringmaster |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -27,5 +27,7 @@ | |||
27 | struct gk20a; | 27 | struct gk20a; |
28 | 28 | ||
29 | void gp10b_priv_ring_isr(struct gk20a *g); | 29 | void gp10b_priv_ring_isr(struct gk20a *g); |
30 | void gp10b_priv_ring_decode_error_code(struct gk20a *g, | ||
31 | u32 error_code); | ||
30 | 32 | ||
31 | #endif /*__PRIV_RING_GP10B_H__*/ | 33 | #endif /*__PRIV_RING_GP10B_H__*/ |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index b0caf9a6..be9afd8b 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -734,6 +734,7 @@ static const struct gpu_ops gv100_ops = { | |||
734 | }, | 734 | }, |
735 | .priv_ring = { | 735 | .priv_ring = { |
736 | .isr = gp10b_priv_ring_isr, | 736 | .isr = gp10b_priv_ring_isr, |
737 | .decode_error_code = gp10b_priv_ring_decode_error_code, | ||
737 | }, | 738 | }, |
738 | .nvlink = { | 739 | .nvlink = { |
739 | .discover_ioctrl = gv100_nvlink_discover_ioctrl, | 740 | .discover_ioctrl = gv100_nvlink_discover_ioctrl, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index ee3fc3de..2d4f82d1 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -711,6 +711,7 @@ static const struct gpu_ops gv11b_ops = { | |||
711 | }, | 711 | }, |
712 | .priv_ring = { | 712 | .priv_ring = { |
713 | .isr = gp10b_priv_ring_isr, | 713 | .isr = gp10b_priv_ring_isr, |
714 | .decode_error_code = gp10b_priv_ring_decode_error_code, | ||
714 | }, | 715 | }, |
715 | .fuse = { | 716 | .fuse = { |
716 | .check_priv_security = gp10b_fuse_check_priv_security, | 717 | .check_priv_security = gp10b_fuse_check_priv_security, |