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-rw-r--r--drivers/gpu/nvgpu/gp10b/mc_gp10b.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index abbd2191..fc0e6553 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -29,20 +29,20 @@ void mc_gp10b_intr_enable(struct gk20a *g)
29 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 29 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
30 0xffffffff); 30 0xffffffff);
31 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = 31 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
32 mc_intr_pfifo_pending_f() 32 mc_intr_pfifo_pending_f() |
33 | mc_intr_replayable_fault_pending_f() 33 mc_intr_priv_ring_pending_f() |
34 | eng_intr_mask; 34 mc_intr_pbus_pending_f() |
35 mc_intr_ltc_pending_f() |
36 mc_intr_replayable_fault_pending_f() |
37 eng_intr_mask;
35 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), 38 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
36 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); 39 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
37 40
38 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), 41 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
39 0xffffffff); 42 0xffffffff);
40 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = 43 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
41 mc_intr_pfifo_pending_f() 44 mc_intr_pfifo_pending_f() |
42 | mc_intr_priv_ring_pending_f() 45 eng_intr_mask;
43 | mc_intr_ltc_pending_f()
44 | mc_intr_pbus_pending_f()
45 | eng_intr_mask;
46 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), 46 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
47 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); 47 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
48} 48}