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-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c12
-rw-r--r--include/uapi/linux/nvgpu.h1
2 files changed, 10 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 16ca16d8..92536b36 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1689,6 +1689,7 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct device *dev,
1689 u32 pbdma_intr_0 = gk20a_readl(g, pbdma_intr_0_r(pbdma_id)); 1689 u32 pbdma_intr_0 = gk20a_readl(g, pbdma_intr_0_r(pbdma_id));
1690 u32 pbdma_intr_1 = gk20a_readl(g, pbdma_intr_1_r(pbdma_id)); 1690 u32 pbdma_intr_1 = gk20a_readl(g, pbdma_intr_1_r(pbdma_id));
1691 u32 handled = 0; 1691 u32 handled = 0;
1692 u32 error_notifier = NVGPU_CHANNEL_PBDMA_ERROR;
1692 bool reset = false; 1693 bool reset = false;
1693 int i; 1694 int i;
1694 1695
@@ -1740,6 +1741,12 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct device *dev,
1740 reset = true; 1741 reset = true;
1741 } 1742 }
1742 1743
1744 if (pbdma_intr_0 & pbdma_intr_0_pbcrc_pending_f()) {
1745 error_notifier =
1746 NVGPU_CHANNEL_PBDMA_PUSHBUFFER_CRC_MISMATCH;
1747 reset = true;
1748 }
1749
1743 if (pbdma_intr_0 & pbdma_intr_0_device_pending_f()) { 1750 if (pbdma_intr_0 & pbdma_intr_0_device_pending_f()) {
1744 gk20a_fifo_reset_pbdma_header(g, pbdma_id); 1751 gk20a_fifo_reset_pbdma_header(g, pbdma_id);
1745 1752
@@ -1773,8 +1780,7 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct device *dev,
1773 struct channel_gk20a *ch = &f->channel[id]; 1780 struct channel_gk20a *ch = &f->channel[id];
1774 1781
1775 if (gk20a_channel_get(ch)) { 1782 if (gk20a_channel_get(ch)) {
1776 gk20a_set_error_notifier(ch, 1783 gk20a_set_error_notifier(ch, error_notifier);
1777 NVGPU_CHANNEL_PBDMA_ERROR);
1778 gk20a_fifo_recover_ch(g, id, true); 1784 gk20a_fifo_recover_ch(g, id, true);
1779 gk20a_channel_put(ch); 1785 gk20a_channel_put(ch);
1780 } 1786 }
@@ -1787,7 +1793,7 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct device *dev,
1787 list_for_each_entry(ch, &tsg->ch_list, ch_entry) { 1793 list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
1788 if (gk20a_channel_get(ch)) { 1794 if (gk20a_channel_get(ch)) {
1789 gk20a_set_error_notifier(ch, 1795 gk20a_set_error_notifier(ch,
1790 NVGPU_CHANNEL_PBDMA_ERROR); 1796 error_notifier);
1791 gk20a_channel_put(ch); 1797 gk20a_channel_put(ch);
1792 } 1798 }
1793 } 1799 }
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index b37d0060..8b4c4549 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -939,6 +939,7 @@ struct nvgpu_notification {
939#define NVGPU_CHANNEL_FIFO_ERROR_MMU_ERR_FLT 31 939#define NVGPU_CHANNEL_FIFO_ERROR_MMU_ERR_FLT 31
940#define NVGPU_CHANNEL_PBDMA_ERROR 32 940#define NVGPU_CHANNEL_PBDMA_ERROR 32
941#define NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR 43 941#define NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR 43
942#define NVGPU_CHANNEL_PBDMA_PUSHBUFFER_CRC_MISMATCH 80
942 __u16 info16; /* info returned depends on method 000c-000d */ 943 __u16 info16; /* info returned depends on method 000c-000d */
943 __u16 status; /* user sets bit 15, NV sets status 000e-000f */ 944 __u16 status; /* user sets bit 15, NV sets status 000e-000f */
944#define NVGPU_CHANNEL_SUBMIT_TIMEOUT 1 945#define NVGPU_CHANNEL_SUBMIT_TIMEOUT 1