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-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c2
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.h3
2 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index da683af6..aac6cba3 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -2504,7 +2504,7 @@ int gv11b_gr_sm_trigger_suspend(struct gk20a *g)
2504 return 0; 2504 return 0;
2505} 2505}
2506 2506
2507void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) 2507void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
2508{ 2508{
2509 /* Check if we have at least one valid warp 2509 /* Check if we have at least one valid warp
2510 * get paused state on maxwell 2510 * get paused state on maxwell
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index 3f06fe77..dbaee5a7 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -44,6 +44,7 @@ struct gk20a;
44struct zbc_entry; 44struct zbc_entry;
45struct zbc_query_params; 45struct zbc_query_params;
46struct channel_ctx_gk20a; 46struct channel_ctx_gk20a;
47struct nvgpu_warpstate;
47 48
48enum { 49enum {
49 VOLTA_CHANNEL_GPFIFO_A = 0xC36F, 50 VOLTA_CHANNEL_GPFIFO_A = 0xC36F,
@@ -158,7 +159,7 @@ int gr_gv11b_init_fs_state(struct gk20a *g);
158void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, 159void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
159 u32 *esr_sm_sel); 160 u32 *esr_sm_sel);
160int gv11b_gr_sm_trigger_suspend(struct gk20a *g); 161int gv11b_gr_sm_trigger_suspend(struct gk20a *g);
161void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state); 162void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state);
162int gv11b_gr_update_sm_error_state(struct gk20a *g, 163int gv11b_gr_update_sm_error_state(struct gk20a *g,
163 struct channel_gk20a *ch, u32 sm_id, 164 struct channel_gk20a *ch, u32 sm_id,
164 struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state); 165 struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state);