2 files changed, 31 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index d8da6f3f..835351c4 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -926,6 +926,27 @@ int vgpu_gr_nonstall_isr(struct gk20a *g,
         return 0;
 }
 
+static int vgpu_gr_set_sm_debug_mode(struct gk20a *g,
+        struct channel_gk20a *ch, u64 sms, bool enable)
+{
+        struct gk20a_platform *platform = gk20a_get_platform(g->dev);
+        struct tegra_vgpu_cmd_msg msg;
+        struct tegra_vgpu_sm_debug_mode *p = &msg.params.sm_debug_mode;
+        int err;
+
+        gk20a_dbg_fn("");
+
+        msg.cmd = TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE;
+        msg.handle = platform->virt_handle;
+        p->handle = ch->virt_ctx;
+        p->sms = sms;
+        p->enable = (u32)enable;
+        err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+        WARN_ON(err || msg.ret);
+
+        return err ? err : msg.ret;
+}
+
 void vgpu_init_gr_ops(struct gpu_ops *gops)
 {
         gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx;
@@ -944,4 +965,5 @@ void vgpu_init_gr_ops(struct gpu_ops *gops)
         gops->gr.zbc_set_table = vgpu_gr_add_zbc;
         gops->gr.zbc_query_table = vgpu_gr_query_zbc;
         gops->gr.init_ctx_state = vgpu_gr_init_ctx_state;
+        gops->gr.set_sm_debug_mode = vgpu_gr_set_sm_debug_mode;
 }
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index b7bcc905..dbfa06d5 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -71,7 +71,8 @@ enum {
         TEGRA_VGPU_CMD_ZBC_QUERY_TABLE,
         TEGRA_VGPU_CMD_AS_MAP_EX,
         TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS,
-        TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE
+        TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE,
+        TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE
 };
 
 struct tegra_vgpu_connect_params {
@@ -264,6 +265,12 @@ struct tegra_vgpu_mmu_debug_mode {
         u32 enable;
 };
 
+struct tegra_vgpu_sm_debug_mode {
+        u64 handle;
+        u64 sms;
+        u32 enable;
+};
+
 struct tegra_vgpu_cmd_msg {
         u32 cmd;
         int ret;
@@ -289,6 +296,7 @@ struct tegra_vgpu_cmd_msg {
                 struct tegra_vgpu_zbc_query_table_params zbc_query_table;
                 struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers;
                 struct tegra_vgpu_mmu_debug_mode mmu_debug_mode;
+                struct tegra_vgpu_sm_debug_mode sm_debug_mode;
                 char padding[192];
         } params;
 };