diff options
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 8 | ||||
-rw-r--r-- | include/linux/tegra_vgpu.h | 27 |
2 files changed, 5 insertions, 30 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index cac1db29..234d8a69 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | |||
@@ -309,6 +309,7 @@ static int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, | |||
309 | 309 | ||
310 | static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) | 310 | static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) |
311 | { | 311 | { |
312 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
312 | int err; | 313 | int err; |
313 | 314 | ||
314 | gk20a_dbg_fn(""); | 315 | gk20a_dbg_fn(""); |
@@ -317,11 +318,10 @@ static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) | |||
317 | if (err) | 318 | if (err) |
318 | return err; | 319 | return err; |
319 | 320 | ||
320 | vgpu_get_attribute(vgpu_get_handle(g), | 321 | g->gr.t18x.ctx_vars.preempt_image_size = |
321 | TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE, | 322 | priv->constants.preempt_ctx_size; |
322 | &g->gr.t18x.ctx_vars.preempt_image_size); | ||
323 | if (!g->gr.t18x.ctx_vars.preempt_image_size) | 323 | if (!g->gr.t18x.ctx_vars.preempt_image_size) |
324 | return -ENXIO; | 324 | return -EINVAL; |
325 | 325 | ||
326 | return 0; | 326 | return 0; |
327 | } | 327 | } |
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 5d4fa36a..daef7d98 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -114,32 +114,6 @@ struct tegra_vgpu_channel_hwctx_params { | |||
114 | u64 handle; | 114 | u64 handle; |
115 | }; | 115 | }; |
116 | 116 | ||
117 | enum { | ||
118 | TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, /*deprecated */ | ||
119 | TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, /* deprecated */ | ||
120 | TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, /* deprecated */ | ||
121 | TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, /* deprecated */ | ||
122 | TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, /* deprecated */ | ||
123 | TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, /* deprecated */ | ||
124 | TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6, /* deprecated */ | ||
125 | TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */ | ||
126 | TEGRA_VGPU_ATTRIB_L2_SIZE = 8, /* deprecated */ | ||
127 | TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, /* deprecated */ | ||
128 | TEGRA_VGPU_ATTRIB_NUM_FBPS = 10, /* deprecated */ | ||
129 | TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11, /* deprecated */ | ||
130 | TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12, /* deprecated */ | ||
131 | TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13, /* deprecated */ | ||
132 | TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14, /* deprecated */ | ||
133 | TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, /* deprecated */ | ||
134 | TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, /* deprecated */ | ||
135 | TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, /* deprecated */ | ||
136 | TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, /* deprecated */ | ||
137 | TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, /* deprecated */ | ||
138 | TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, /* deprecated */ | ||
139 | TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */ | ||
140 | TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE = 64, /* gap to hide T18x IP */ | ||
141 | }; | ||
142 | |||
143 | struct tegra_vgpu_attrib_params { | 117 | struct tegra_vgpu_attrib_params { |
144 | u32 attrib; | 118 | u32 attrib; |
145 | u32 value; | 119 | u32 value; |
@@ -458,6 +432,7 @@ struct tegra_vgpu_constants_params { | |||
458 | u32 hwpm_ctx_size; | 432 | u32 hwpm_ctx_size; |
459 | u8 force_preempt_mode; | 433 | u8 force_preempt_mode; |
460 | u32 default_timeslice_us; | 434 | u32 default_timeslice_us; |
435 | u32 preempt_ctx_size; | ||
461 | }; | 436 | }; |
462 | 437 | ||
463 | struct tegra_vgpu_channel_cyclestats_snapshot_params { | 438 | struct tegra_vgpu_channel_cyclestats_snapshot_params { |