diff options
-rw-r--r-- | drivers/gpu/nvgpu/Kconfig.nvgpu | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hal_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 106 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | 170 |
7 files changed, 8 insertions, 284 deletions
diff --git a/drivers/gpu/nvgpu/Kconfig.nvgpu b/drivers/gpu/nvgpu/Kconfig.nvgpu index 4d7e0f12..73904a94 100644 --- a/drivers/gpu/nvgpu/Kconfig.nvgpu +++ b/drivers/gpu/nvgpu/Kconfig.nvgpu | |||
@@ -36,7 +36,7 @@ config GK20A_PERFMON | |||
36 | decrease frequency if idle). | 36 | decrease frequency if idle). |
37 | 37 | ||
38 | config GK20A_DEVFREQ | 38 | config GK20A_DEVFREQ |
39 | depends on TEGRA_CLK_FRAMEWORK || COMMON_CLK | 39 | depends on COMMON_CLK |
40 | bool "Use Devfreq" | 40 | bool "Use Devfreq" |
41 | help | 41 | help |
42 | Select this to use devfreq based scaling. | 42 | Select this to use devfreq based scaling. |
@@ -104,7 +104,7 @@ config TEGRA_ACR | |||
104 | 104 | ||
105 | config TEGRA_USE_NA_GPCPLL | 105 | config TEGRA_USE_NA_GPCPLL |
106 | bool "Enable noise aware mode of GM20B GPCPLL on Tegra" | 106 | bool "Enable noise aware mode of GM20B GPCPLL on Tegra" |
107 | depends on TEGRA_CLK_FRAMEWORK || COMMON_CLK | 107 | depends on COMMON_CLK |
108 | default n | 108 | default n |
109 | help | 109 | help |
110 | Enable noise aware (NA) mode of GM20b GPCPLL. In this mode PLL output | 110 | Enable noise aware (NA) mode of GM20b GPCPLL. In this mode PLL output |
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h index f07efa40..76f5de43 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h | |||
@@ -104,11 +104,6 @@ struct clk_gk20a { | |||
104 | #endif | 104 | #endif |
105 | 105 | ||
106 | struct gpu_ops; | 106 | struct gpu_ops; |
107 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
108 | void gk20a_init_clk_ops(struct gpu_ops *gops); | ||
109 | #else | ||
110 | static inline void gk20a_init_clk_ops(struct gpu_ops *gops) {} | ||
111 | #endif | ||
112 | 107 | ||
113 | /* APIs used for both GK20A and GM20B */ | 108 | /* APIs used for both GK20A and GM20B */ |
114 | unsigned long gk20a_clk_get_rate(struct gk20a *g); | 109 | unsigned long gk20a_clk_get_rate(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 3d1e0847..217b1186 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1275,8 +1275,6 @@ enum gk20a_nonstall_ops { | |||
1275 | gk20a_nonstall_ops_post_events = BIT(1), | 1275 | gk20a_nonstall_ops_post_events = BIT(1), |
1276 | }; | 1276 | }; |
1277 | 1277 | ||
1278 | void gk20a_init_clk_ops(struct gpu_ops *gops); | ||
1279 | |||
1280 | /* register accessors */ | 1278 | /* register accessors */ |
1281 | int gk20a_lockout_registers(struct gk20a *g); | 1279 | int gk20a_lockout_registers(struct gk20a *g); |
1282 | int gk20a_restore_registers(struct gk20a *g); | 1280 | int gk20a_restore_registers(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c index ff9e0fc1..d7642182 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c | |||
@@ -23,7 +23,6 @@ | |||
23 | #include <linux/pm_runtime.h> | 23 | #include <linux/pm_runtime.h> |
24 | #include <linux/fb.h> | 24 | #include <linux/fb.h> |
25 | #include <linux/gk20a.h> | 25 | #include <linux/gk20a.h> |
26 | #include <linux/clk/tegra.h> | ||
27 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) | 26 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) |
28 | #include <soc/tegra/tegra-dvfs.h> | 27 | #include <soc/tegra/tegra-dvfs.h> |
29 | #endif | 28 | #endif |
@@ -717,9 +716,6 @@ static ssize_t fmax_at_vmin_safe_read(struct device *dev, | |||
717 | unsigned long gpu_fmax_at_vmin_hz = 0; | 716 | unsigned long gpu_fmax_at_vmin_hz = 0; |
718 | struct clk *clk = g->clk.tegra_clk; | 717 | struct clk *clk = g->clk.tegra_clk; |
719 | 718 | ||
720 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
721 | clk = clk_get_parent(clk); | ||
722 | #endif | ||
723 | gpu_fmax_at_vmin_hz = tegra_dvfs_get_fmax_at_vmin_safe_t(clk); | 719 | gpu_fmax_at_vmin_hz = tegra_dvfs_get_fmax_at_vmin_safe_t(clk); |
724 | 720 | ||
725 | return snprintf(buf, PAGE_SIZE, "%d\n", (int)(gpu_fmax_at_vmin_hz)); | 721 | return snprintf(buf, PAGE_SIZE, "%d\n", (int)(gpu_fmax_at_vmin_hz)); |
diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c index 729a277f..8a3beb39 100644 --- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c | |||
@@ -167,7 +167,6 @@ int gk20a_init_hal(struct gk20a *g) | |||
167 | gk20a_init_mm(gops); | 167 | gk20a_init_mm(gops); |
168 | gk20a_falcon_init_hal(gops); | 168 | gk20a_falcon_init_hal(gops); |
169 | gk20a_init_pmu_ops(gops); | 169 | gk20a_init_pmu_ops(gops); |
170 | gk20a_init_clk_ops(gops); | ||
171 | gk20a_init_regops(gops); | 170 | gk20a_init_regops(gops); |
172 | gk20a_init_debug_ops(gops); | 171 | gk20a_init_debug_ops(gops); |
173 | gk20a_init_dbg_session_ops(gops); | 172 | gk20a_init_dbg_session_ops(gops); |
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index d1dbf181..f1f75b74 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -22,7 +22,6 @@ | |||
22 | #include <linux/debugfs.h> | 22 | #include <linux/debugfs.h> |
23 | #include <linux/uaccess.h> | 23 | #include <linux/uaccess.h> |
24 | #endif | 24 | #endif |
25 | #include <linux/clk/tegra.h> | ||
26 | #include <soc/tegra/fuse.h> | 25 | #include <soc/tegra/fuse.h> |
27 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) | 26 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) |
28 | #include <soc/tegra/tegra-dvfs.h> | 27 | #include <soc/tegra/tegra-dvfs.h> |
@@ -1142,7 +1141,7 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1142 | { | 1141 | { |
1143 | struct clk_gk20a *clk = &g->clk; | 1142 | struct clk_gk20a *clk = &g->clk; |
1144 | unsigned long safe_rate; | 1143 | unsigned long safe_rate; |
1145 | struct clk *ref, *c; | 1144 | struct clk *ref = NULL, *c; |
1146 | int err; | 1145 | int err; |
1147 | 1146 | ||
1148 | gk20a_dbg_fn(""); | 1147 | gk20a_dbg_fn(""); |
@@ -1178,12 +1177,7 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1178 | */ | 1177 | */ |
1179 | c = clk_get_parent(clk->tegra_clk); | 1178 | c = clk_get_parent(clk->tegra_clk); |
1180 | 1179 | ||
1181 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1182 | ref = clk_get_parent(clk_get_parent(c)); | ||
1183 | #elif defined (CONFIG_COMMON_CLK) | ||
1184 | ref = clk_get_sys("gpu_ref", "gpu_ref"); | 1180 | ref = clk_get_sys("gpu_ref", "gpu_ref"); |
1185 | #endif | ||
1186 | |||
1187 | if (IS_ERR(ref)) { | 1181 | if (IS_ERR(ref)) { |
1188 | nvgpu_err(g, "failed to get GPCPLL reference clock"); | 1182 | nvgpu_err(g, "failed to get GPCPLL reference clock"); |
1189 | err = -EINVAL; | 1183 | err = -EINVAL; |
@@ -1474,91 +1468,6 @@ static int set_pll_freq(struct gk20a *g, int allow_slide) | |||
1474 | return err; | 1468 | return err; |
1475 | } | 1469 | } |
1476 | 1470 | ||
1477 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1478 | static int gm20b_clk_export_set_rate(void *data, unsigned long *rate) | ||
1479 | { | ||
1480 | u32 old_freq; | ||
1481 | int ret = -ENODATA; | ||
1482 | struct gk20a *g = data; | ||
1483 | struct clk_gk20a *clk = &g->clk; | ||
1484 | |||
1485 | if (rate) { | ||
1486 | nvgpu_mutex_acquire(&clk->clk_mutex); | ||
1487 | old_freq = clk->gpc_pll.freq; | ||
1488 | ret = set_pll_target(g, rate_gpu_to_gpc2clk(*rate), old_freq); | ||
1489 | if (!ret && clk->gpc_pll.enabled && clk->clk_hw_on) | ||
1490 | ret = set_pll_freq(g, 1); | ||
1491 | if (!ret) | ||
1492 | *rate = rate_gpc2clk_to_gpu(clk->gpc_pll.freq); | ||
1493 | nvgpu_mutex_release(&clk->clk_mutex); | ||
1494 | } | ||
1495 | return ret; | ||
1496 | } | ||
1497 | |||
1498 | static int gm20b_clk_export_enable(void *data) | ||
1499 | { | ||
1500 | int ret = 0; | ||
1501 | struct gk20a *g = data; | ||
1502 | struct clk_gk20a *clk = &g->clk; | ||
1503 | |||
1504 | nvgpu_mutex_acquire(&clk->clk_mutex); | ||
1505 | if (!clk->gpc_pll.enabled && clk->clk_hw_on) | ||
1506 | ret = set_pll_freq(g, 1); | ||
1507 | nvgpu_mutex_release(&clk->clk_mutex); | ||
1508 | return ret; | ||
1509 | } | ||
1510 | |||
1511 | static void gm20b_clk_export_disable(void *data) | ||
1512 | { | ||
1513 | struct gk20a *g = data; | ||
1514 | struct clk_gk20a *clk = &g->clk; | ||
1515 | |||
1516 | nvgpu_mutex_acquire(&clk->clk_mutex); | ||
1517 | if (clk->gpc_pll.enabled && clk->clk_hw_on) | ||
1518 | clk_disable_gpcpll(g, 1); | ||
1519 | nvgpu_mutex_release(&clk->clk_mutex); | ||
1520 | } | ||
1521 | |||
1522 | static void gm20b_clk_export_init(void *data, unsigned long *rate, bool *state) | ||
1523 | { | ||
1524 | struct gk20a *g = data; | ||
1525 | struct clk_gk20a *clk = &g->clk; | ||
1526 | |||
1527 | nvgpu_mutex_acquire(&clk->clk_mutex); | ||
1528 | if (state) | ||
1529 | *state = clk->gpc_pll.enabled; | ||
1530 | if (rate) | ||
1531 | *rate = rate_gpc2clk_to_gpu(clk->gpc_pll.freq); | ||
1532 | nvgpu_mutex_release(&clk->clk_mutex); | ||
1533 | } | ||
1534 | |||
1535 | static struct tegra_clk_export_ops gm20b_clk_export_ops = { | ||
1536 | .init = gm20b_clk_export_init, | ||
1537 | .enable = gm20b_clk_export_enable, | ||
1538 | .disable = gm20b_clk_export_disable, | ||
1539 | .set_rate = gm20b_clk_export_set_rate, | ||
1540 | }; | ||
1541 | |||
1542 | static int gm20b_clk_register_export_ops(struct gk20a *g) | ||
1543 | { | ||
1544 | int ret; | ||
1545 | struct clk *c; | ||
1546 | |||
1547 | if (gm20b_clk_export_ops.data) | ||
1548 | return 0; | ||
1549 | |||
1550 | gm20b_clk_export_ops.data = (void *)g; | ||
1551 | c = g->clk.tegra_clk; | ||
1552 | if (!c || !clk_get_parent(c)) | ||
1553 | return -ENOSYS; | ||
1554 | |||
1555 | ret = tegra_clk_register_export_ops(clk_get_parent(c), | ||
1556 | &gm20b_clk_export_ops); | ||
1557 | |||
1558 | return ret; | ||
1559 | } | ||
1560 | #endif /* CONFIG_TEGRA_CLK_FRAMEWORK */ | ||
1561 | |||
1562 | static int gm20b_init_clk_support(struct gk20a *g) | 1471 | static int gm20b_init_clk_support(struct gk20a *g) |
1563 | { | 1472 | { |
1564 | struct clk_gk20a *clk = &g->clk; | 1473 | struct clk_gk20a *clk = &g->clk; |
@@ -1570,13 +1479,6 @@ static int gm20b_init_clk_support(struct gk20a *g) | |||
1570 | if (err) | 1479 | if (err) |
1571 | return err; | 1480 | return err; |
1572 | 1481 | ||
1573 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1574 | clk->g = g; | ||
1575 | err = gm20b_init_clk_setup_sw(g); | ||
1576 | if (err) | ||
1577 | return err; | ||
1578 | #endif | ||
1579 | |||
1580 | nvgpu_mutex_acquire(&clk->clk_mutex); | 1482 | nvgpu_mutex_acquire(&clk->clk_mutex); |
1581 | clk->clk_hw_on = true; | 1483 | clk->clk_hw_on = true; |
1582 | 1484 | ||
@@ -1585,12 +1487,6 @@ static int gm20b_init_clk_support(struct gk20a *g) | |||
1585 | if (err) | 1487 | if (err) |
1586 | return err; | 1488 | return err; |
1587 | 1489 | ||
1588 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1589 | err = gm20b_clk_register_export_ops(g); | ||
1590 | if (err) | ||
1591 | return err; | ||
1592 | #endif | ||
1593 | |||
1594 | /* FIXME: this effectively prevents host level clock gating */ | 1490 | /* FIXME: this effectively prevents host level clock gating */ |
1595 | err = clk_prepare_enable(g->clk.tegra_clk); | 1491 | err = clk_prepare_enable(g->clk.tegra_clk); |
1596 | if (err) | 1492 | if (err) |
diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c index 2bb7d5cb..a8a1451a 100644 --- a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | |||
@@ -26,12 +26,9 @@ | |||
26 | #include <linux/dma-attrs.h> | 26 | #include <linux/dma-attrs.h> |
27 | #include <linux/nvmap.h> | 27 | #include <linux/nvmap.h> |
28 | #include <linux/reset.h> | 28 | #include <linux/reset.h> |
29 | #if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_TEGRA_DVFS) | 29 | #if defined(CONFIG_TEGRA_DVFS) |
30 | #include <linux/tegra_soctherm.h> | 30 | #include <linux/tegra_soctherm.h> |
31 | #endif | 31 | #endif |
32 | #if defined(CONFIG_TEGRA_CLK_FRAMEWORK) | ||
33 | #include <linux/platform/tegra/dvfs.h> | ||
34 | #endif | ||
35 | #include <linux/platform/tegra/common.h> | 32 | #include <linux/platform/tegra/common.h> |
36 | #include <linux/platform/tegra/mc.h> | 33 | #include <linux/platform/tegra/mc.h> |
37 | #include <linux/clk/tegra.h> | 34 | #include <linux/clk/tegra.h> |
@@ -391,137 +388,7 @@ done: | |||
391 | 388 | ||
392 | #endif | 389 | #endif |
393 | 390 | ||
394 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | 391 | #if defined(CONFIG_TEGRA_DVFS) |
395 | /* | ||
396 | * gk20a_tegra_railgate() | ||
397 | * | ||
398 | * Gate (disable) gk20a power rail | ||
399 | */ | ||
400 | |||
401 | static int gk20a_tegra_railgate(struct device *dev) | ||
402 | { | ||
403 | struct gk20a *g = get_gk20a(dev); | ||
404 | struct gk20a_platform *platform = dev_get_drvdata(dev); | ||
405 | int ret = 0; | ||
406 | |||
407 | if (g->is_fmodel || | ||
408 | !tegra_dvfs_is_rail_up(platform->gpu_rail)) | ||
409 | return 0; | ||
410 | |||
411 | tegra_mc_flush(MC_CLIENT_GPU); | ||
412 | |||
413 | udelay(10); | ||
414 | |||
415 | /* enable clamp */ | ||
416 | pmc_write(0x1, PMC_GPU_RG_CNTRL_0); | ||
417 | pmc_read(PMC_GPU_RG_CNTRL_0); | ||
418 | |||
419 | udelay(10); | ||
420 | |||
421 | platform->reset_assert(dev); | ||
422 | |||
423 | udelay(10); | ||
424 | |||
425 | /* | ||
426 | * GPCPLL is already disabled before entering this function; reference | ||
427 | * clocks are enabled until now - disable them just before rail gating | ||
428 | */ | ||
429 | clk_disable(platform->clk[0]); | ||
430 | clk_disable(platform->clk[1]); | ||
431 | |||
432 | udelay(10); | ||
433 | |||
434 | if (tegra_dvfs_is_rail_up(platform->gpu_rail)) { | ||
435 | ret = tegra_dvfs_rail_power_down(platform->gpu_rail); | ||
436 | if (ret) | ||
437 | goto err_power_off; | ||
438 | } else | ||
439 | pr_info("No GPU regulator?\n"); | ||
440 | |||
441 | return 0; | ||
442 | |||
443 | err_power_off: | ||
444 | nvgpu_err(get_gk20a(dev), "Could not railgate GPU"); | ||
445 | return ret; | ||
446 | } | ||
447 | |||
448 | |||
449 | /* | ||
450 | * gk20a_tegra_unrailgate() | ||
451 | * | ||
452 | * Ungate (enable) gk20a power rail | ||
453 | */ | ||
454 | |||
455 | static int gk20a_tegra_unrailgate(struct device *dev) | ||
456 | { | ||
457 | struct gk20a *g = get_gk20a(dev); | ||
458 | struct gk20a_platform *platform = dev_get_drvdata(dev); | ||
459 | int ret = 0; | ||
460 | bool first = false; | ||
461 | |||
462 | if (g->is_fmodel) | ||
463 | return 0; | ||
464 | |||
465 | if (!platform->gpu_rail) { | ||
466 | platform->gpu_rail = tegra_dvfs_get_rail_by_name("vdd_gpu"); | ||
467 | if (IS_ERR_OR_NULL(platform->gpu_rail)) { | ||
468 | WARN(1, "No GPU regulator?\n"); | ||
469 | return -EINVAL; | ||
470 | } | ||
471 | first = true; | ||
472 | } | ||
473 | |||
474 | ret = tegra_dvfs_rail_power_up(platform->gpu_rail); | ||
475 | if (ret) | ||
476 | return ret; | ||
477 | |||
478 | if (!first) { | ||
479 | ret = clk_enable(platform->clk[0]); | ||
480 | if (ret) { | ||
481 | nvgpu_err(platform->g, "could not turn on gpu pll"); | ||
482 | goto err_clk_on; | ||
483 | } | ||
484 | ret = clk_enable(platform->clk[1]); | ||
485 | if (ret) { | ||
486 | nvgpu_err(platform->g, "could not turn on pwr clock"); | ||
487 | goto err_clk_on; | ||
488 | } | ||
489 | } | ||
490 | |||
491 | udelay(10); | ||
492 | |||
493 | platform->reset_assert(dev); | ||
494 | |||
495 | udelay(10); | ||
496 | |||
497 | pmc_write(0, PMC_GPU_RG_CNTRL_0); | ||
498 | pmc_read(PMC_GPU_RG_CNTRL_0); | ||
499 | |||
500 | udelay(10); | ||
501 | |||
502 | platform->reset_deassert(dev); | ||
503 | |||
504 | /* Flush MC after boot/railgate/SC7 */ | ||
505 | tegra_mc_flush(MC_CLIENT_GPU); | ||
506 | |||
507 | udelay(10); | ||
508 | |||
509 | tegra_mc_flush_done(MC_CLIENT_GPU); | ||
510 | |||
511 | udelay(10); | ||
512 | |||
513 | return 0; | ||
514 | |||
515 | err_clk_on: | ||
516 | tegra_dvfs_rail_power_down(platform->gpu_rail); | ||
517 | |||
518 | return ret; | ||
519 | } | ||
520 | |||
521 | #endif | ||
522 | |||
523 | |||
524 | #if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_TEGRA_DVFS) | ||
525 | /* | 392 | /* |
526 | * gk20a_tegra_is_railgated() | 393 | * gk20a_tegra_is_railgated() |
527 | * | 394 | * |
@@ -619,17 +486,6 @@ static int gm20b_tegra_unrailgate(struct device *dev) | |||
619 | if (g->is_fmodel) | 486 | if (g->is_fmodel) |
620 | return 0; | 487 | return 0; |
621 | 488 | ||
622 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
623 | if (!platform->gpu_rail) { | ||
624 | platform->gpu_rail = tegra_dvfs_get_rail_by_name(GPU_RAIL_NAME); | ||
625 | if (IS_ERR_OR_NULL(platform->gpu_rail)) { | ||
626 | WARN(1, "No GPU regulator?\n"); | ||
627 | return -EINVAL; | ||
628 | } | ||
629 | first = true; | ||
630 | } | ||
631 | #endif | ||
632 | |||
633 | ret = tegra_dvfs_rail_power_up(platform->gpu_rail); | 489 | ret = tegra_dvfs_rail_power_up(platform->gpu_rail); |
634 | if (ret) | 490 | if (ret) |
635 | return ret; | 491 | return ret; |
@@ -713,16 +569,10 @@ static struct { | |||
713 | char *name; | 569 | char *name; |
714 | unsigned long default_rate; | 570 | unsigned long default_rate; |
715 | } tegra_gk20a_clocks[] = { | 571 | } tegra_gk20a_clocks[] = { |
716 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
717 | {"PLLG_ref", UINT_MAX}, | ||
718 | {"pwr", 204000000}, | ||
719 | {"emc", UINT_MAX}, | ||
720 | #elif defined(CONFIG_COMMON_CLK) | ||
721 | {"gpu_ref", UINT_MAX}, | 572 | {"gpu_ref", UINT_MAX}, |
722 | {"pll_p_out5", 204000000}, | 573 | {"pll_p_out5", 204000000}, |
723 | {"emc", UINT_MAX}, | 574 | {"emc", UINT_MAX}, |
724 | {"fuse", UINT_MAX}, | 575 | {"fuse", UINT_MAX}, |
725 | #endif | ||
726 | }; | 576 | }; |
727 | 577 | ||
728 | 578 | ||
@@ -1021,7 +871,7 @@ static int gk20a_tegra_suspend(struct device *dev) | |||
1021 | return 0; | 871 | return 0; |
1022 | } | 872 | } |
1023 | 873 | ||
1024 | #if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_COMMON_CLK) | 874 | #if defined(CONFIG_COMMON_CLK) |
1025 | static long gk20a_round_clk_rate(struct device *dev, unsigned long rate) | 875 | static long gk20a_round_clk_rate(struct device *dev, unsigned long rate) |
1026 | { | 876 | { |
1027 | struct gk20a_platform *platform = gk20a_get_platform(dev); | 877 | struct gk20a_platform *platform = gk20a_get_platform(dev); |
@@ -1073,11 +923,6 @@ struct gk20a_platform gk20a_tegra_platform = { | |||
1073 | 923 | ||
1074 | /* power management callbacks */ | 924 | /* power management callbacks */ |
1075 | .suspend = gk20a_tegra_suspend, | 925 | .suspend = gk20a_tegra_suspend, |
1076 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1077 | .railgate = gk20a_tegra_railgate, | ||
1078 | .unrailgate = gk20a_tegra_unrailgate, | ||
1079 | .is_railgated = gk20a_tegra_is_railgated, | ||
1080 | #endif | ||
1081 | 926 | ||
1082 | .busy = gk20a_tegra_busy, | 927 | .busy = gk20a_tegra_busy, |
1083 | .idle = gk20a_tegra_idle, | 928 | .idle = gk20a_tegra_idle, |
@@ -1085,11 +930,6 @@ struct gk20a_platform gk20a_tegra_platform = { | |||
1085 | .reset_assert = gk20a_tegra_reset_assert, | 930 | .reset_assert = gk20a_tegra_reset_assert, |
1086 | .reset_deassert = gk20a_tegra_reset_deassert, | 931 | .reset_deassert = gk20a_tegra_reset_deassert, |
1087 | 932 | ||
1088 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1089 | .clk_round_rate = gk20a_round_clk_rate, | ||
1090 | .get_clk_freqs = gk20a_clk_get_freqs, | ||
1091 | #endif | ||
1092 | |||
1093 | /* frequency scaling configuration */ | 933 | /* frequency scaling configuration */ |
1094 | .prescale = gk20a_tegra_prescale, | 934 | .prescale = gk20a_tegra_prescale, |
1095 | .postscale = gk20a_tegra_postscale, | 935 | .postscale = gk20a_tegra_postscale, |
@@ -1130,7 +970,7 @@ struct gk20a_platform gm20b_tegra_platform = { | |||
1130 | /* power management callbacks */ | 970 | /* power management callbacks */ |
1131 | .suspend = gk20a_tegra_suspend, | 971 | .suspend = gk20a_tegra_suspend, |
1132 | 972 | ||
1133 | #if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_TEGRA_DVFS) | 973 | #if defined(CONFIG_TEGRA_DVFS) |
1134 | .railgate = gm20b_tegra_railgate, | 974 | .railgate = gm20b_tegra_railgate, |
1135 | .unrailgate = gm20b_tegra_unrailgate, | 975 | .unrailgate = gm20b_tegra_unrailgate, |
1136 | .is_railgated = gk20a_tegra_is_railgated, | 976 | .is_railgated = gk20a_tegra_is_railgated, |
@@ -1147,7 +987,7 @@ struct gk20a_platform gm20b_tegra_platform = { | |||
1147 | .reset_deassert = gk20a_tegra_reset_deassert, | 987 | .reset_deassert = gk20a_tegra_reset_deassert, |
1148 | #endif | 988 | #endif |
1149 | 989 | ||
1150 | #if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_COMMON_CLK) | 990 | #if defined(CONFIG_COMMON_CLK) |
1151 | .clk_round_rate = gk20a_round_clk_rate, | 991 | .clk_round_rate = gk20a_round_clk_rate, |
1152 | .get_clk_freqs = gk20a_clk_get_freqs, | 992 | .get_clk_freqs = gk20a_clk_get_freqs, |
1153 | #endif | 993 | #endif |