diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 33 |
1 files changed, 18 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index a9aea632..ed730174 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -525,6 +525,7 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g) | |||
525 | GFP_KERNEL); | 525 | GFP_KERNEL); |
526 | if (!f->userd.cpuva) { | 526 | if (!f->userd.cpuva) { |
527 | dev_err(d, "memory allocation failed\n"); | 527 | dev_err(d, "memory allocation failed\n"); |
528 | err = -ENOMEM; | ||
528 | goto clean_up; | 529 | goto clean_up; |
529 | } | 530 | } |
530 | 531 | ||
@@ -545,6 +546,7 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g) | |||
545 | gk20a_mem_flag_none); | 546 | gk20a_mem_flag_none); |
546 | if (!f->userd.gpu_va) { | 547 | if (!f->userd.gpu_va) { |
547 | dev_err(d, "gmmu mapping failed\n"); | 548 | dev_err(d, "gmmu mapping failed\n"); |
549 | err = -ENOMEM; | ||
548 | goto clean_up; | 550 | goto clean_up; |
549 | } | 551 | } |
550 | 552 | ||
@@ -1572,27 +1574,28 @@ void gk20a_fifo_isr(struct gk20a *g) | |||
1572 | u32 fifo_intr = gk20a_readl(g, fifo_intr_0_r()); | 1574 | u32 fifo_intr = gk20a_readl(g, fifo_intr_0_r()); |
1573 | u32 clear_intr = 0; | 1575 | u32 clear_intr = 0; |
1574 | 1576 | ||
1575 | /* note we're not actually in an "isr", but rather | 1577 | if (g->fifo.sw_ready) { |
1576 | * in a threaded interrupt context... */ | 1578 | /* note we're not actually in an "isr", but rather |
1577 | mutex_lock(&g->fifo.intr.isr.mutex); | 1579 | * in a threaded interrupt context... */ |
1580 | mutex_lock(&g->fifo.intr.isr.mutex); | ||
1578 | 1581 | ||
1579 | gk20a_dbg(gpu_dbg_intr, "fifo isr %08x\n", fifo_intr); | 1582 | gk20a_dbg(gpu_dbg_intr, "fifo isr %08x\n", fifo_intr); |
1580 | 1583 | ||
1581 | /* handle runlist update */ | 1584 | /* handle runlist update */ |
1582 | if (fifo_intr & fifo_intr_0_runlist_event_pending_f()) { | 1585 | if (fifo_intr & fifo_intr_0_runlist_event_pending_f()) { |
1583 | gk20a_fifo_handle_runlist_event(g); | 1586 | gk20a_fifo_handle_runlist_event(g); |
1584 | clear_intr |= fifo_intr_0_runlist_event_pending_f(); | 1587 | clear_intr |= fifo_intr_0_runlist_event_pending_f(); |
1585 | } | 1588 | } |
1586 | if (fifo_intr & fifo_intr_0_pbdma_intr_pending_f()) | 1589 | if (fifo_intr & fifo_intr_0_pbdma_intr_pending_f()) |
1587 | clear_intr |= fifo_pbdma_isr(g, fifo_intr); | 1590 | clear_intr |= fifo_pbdma_isr(g, fifo_intr); |
1588 | 1591 | ||
1589 | if (unlikely(fifo_intr & error_intr_mask)) | 1592 | if (unlikely(fifo_intr & error_intr_mask)) |
1590 | clear_intr = fifo_error_isr(g, fifo_intr); | 1593 | clear_intr = fifo_error_isr(g, fifo_intr); |
1591 | 1594 | ||
1595 | mutex_unlock(&g->fifo.intr.isr.mutex); | ||
1596 | } | ||
1592 | gk20a_writel(g, fifo_intr_0_r(), clear_intr); | 1597 | gk20a_writel(g, fifo_intr_0_r(), clear_intr); |
1593 | 1598 | ||
1594 | mutex_unlock(&g->fifo.intr.isr.mutex); | ||
1595 | |||
1596 | return; | 1599 | return; |
1597 | } | 1600 | } |
1598 | 1601 | ||