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-rw-r--r--drivers/gpu/nvgpu/gk20a/cde_gk20a.c4
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_gk20a.c13
-rw-r--r--drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c3
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c4
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.c8
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h114
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c5
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c174
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.h6
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_ops_gk20a.h62
-rw-r--r--drivers/gpu/nvgpu/gk20a/hal.c10
-rw-r--r--drivers/gpu/nvgpu/gk20a/ltc_common.c6
-rw-r--r--drivers/gpu/nvgpu/gk20a/ltc_gk20a.c31
-rw-r--r--drivers/gpu/nvgpu/gk20a/mm_gk20a.c4
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.c4
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c91
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.h8
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_ops_gm20b.h79
-rw-r--r--drivers/gpu/nvgpu/gm20b/ltc_gm20b.c38
-rw-r--r--drivers/gpu/nvgpu/gr_ops.h103
-rw-r--r--drivers/gpu/nvgpu/nvgpu_gpuid.h30
-rw-r--r--drivers/gpu/nvgpu/vgpu/gr_vgpu.c27
-rw-r--r--drivers/gpu/nvgpu/vgpu/ltc_vgpu.c8
-rw-r--r--drivers/gpu/nvgpu/vgpu/vgpu.c3
24 files changed, 306 insertions, 529 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
index d9fe9ef1..ee62f02a 100644
--- a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
@@ -50,7 +50,7 @@ static void gk20a_deinit_cde_img(struct gk20a_cde_ctx *cde_ctx)
50 } 50 }
51 51
52 for (i = 0; i < cde_ctx->num_obj_ids; i++) 52 for (i = 0; i < cde_ctx->num_obj_ids; i++)
53 gr_gk20a_free_obj_ctx(cde_ctx->ch, 53 gk20a_free_obj_ctx(cde_ctx->ch,
54 &(struct nvgpu_free_obj_ctx_args) 54 &(struct nvgpu_free_obj_ctx_args)
55 { cde_ctx->obj_ids[i] }); 55 { cde_ctx->obj_ids[i] });
56 56
@@ -401,7 +401,7 @@ static int gk20a_init_cde_required_class(struct gk20a_cde_ctx *cde_ctx,
401 alloc_obj_ctx.class_num = required_class; 401 alloc_obj_ctx.class_num = required_class;
402 alloc_obj_ctx.padding = 0; 402 alloc_obj_ctx.padding = 0;
403 403
404 err = gr_gk20a_alloc_obj_ctx(cde_ctx->ch, &alloc_obj_ctx); 404 err = gk20a_alloc_obj_ctx(cde_ctx->ch, &alloc_obj_ctx);
405 if (err) { 405 if (err) {
406 gk20a_warn(&cde_ctx->pdev->dev, "cde: failed to allocate ctx. err=%d", 406 gk20a_warn(&cde_ctx->pdev->dev, "cde: failed to allocate ctx. err=%d",
407 err); 407 err);
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 777d7ca9..9f2e0017 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -28,7 +28,6 @@
28 28
29#include "debug_gk20a.h" 29#include "debug_gk20a.h"
30 30
31#include "gr_ops.h"
32#include "gk20a.h" 31#include "gk20a.h"
33#include "dbg_gpu_gk20a.h" 32#include "dbg_gpu_gk20a.h"
34#include "fence_gk20a.h" 33#include "fence_gk20a.h"
@@ -639,7 +638,7 @@ void gk20a_free_channel(struct channel_gk20a *ch, bool finish)
639 gk20a_free_error_notifiers(ch); 638 gk20a_free_error_notifiers(ch);
640 639
641 /* release channel ctx */ 640 /* release channel ctx */
642 g->ops.gr->free_channel_ctx(ch); 641 g->ops.gr.free_channel_ctx(ch);
643 642
644 gk20a_gr_flush_channel_tlb(gr); 643 gk20a_gr_flush_channel_tlb(gr);
645 644
@@ -1559,8 +1558,8 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c,
1559 1558
1560#ifdef CONFIG_DEBUG_FS 1559#ifdef CONFIG_DEBUG_FS
1561 /* update debug settings */ 1560 /* update debug settings */
1562 if (g->ops.ltc->sync_debugfs) 1561 if (g->ops.ltc.sync_debugfs)
1563 g->ops.ltc->sync_debugfs(g); 1562 g->ops.ltc.sync_debugfs(g);
1564#endif 1563#endif
1565 1564
1566 gk20a_dbg_info("channel %d", c->hw_chid); 1565 gk20a_dbg_info("channel %d", c->hw_chid);
@@ -2081,7 +2080,7 @@ static int gk20a_channel_zcull_bind(struct channel_gk20a *ch,
2081 2080
2082 gk20a_dbg_fn(""); 2081 gk20a_dbg_fn("");
2083 2082
2084 return g->ops.gr->bind_ctxsw_zcull(g, gr, ch, 2083 return g->ops.gr.bind_ctxsw_zcull(g, gr, ch,
2085 args->gpu_va, args->mode); 2084 args->gpu_va, args->mode);
2086} 2085}
2087 2086
@@ -2301,7 +2300,7 @@ long gk20a_channel_ioctl(struct file *filp,
2301 __func__, cmd); 2300 __func__, cmd);
2302 return err; 2301 return err;
2303 } 2302 }
2304 err = ch->g->ops.gr->alloc_obj_ctx(ch, 2303 err = ch->g->ops.gr.alloc_obj_ctx(ch,
2305 (struct nvgpu_alloc_obj_ctx_args *)buf); 2304 (struct nvgpu_alloc_obj_ctx_args *)buf);
2306 gk20a_idle(dev); 2305 gk20a_idle(dev);
2307 break; 2306 break;
@@ -2313,7 +2312,7 @@ long gk20a_channel_ioctl(struct file *filp,
2313 __func__, cmd); 2312 __func__, cmd);
2314 return err; 2313 return err;
2315 } 2314 }
2316 err = ch->g->ops.gr->free_obj_ctx(ch, 2315 err = ch->g->ops.gr.free_obj_ctx(ch,
2317 (struct nvgpu_free_obj_ctx_args *)buf); 2316 (struct nvgpu_free_obj_ctx_args *)buf);
2318 gk20a_idle(dev); 2317 gk20a_idle(dev);
2319 break; 2318 break;
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c
index aae77647..93831844 100644
--- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c
@@ -21,7 +21,6 @@
21#include <linux/nvgpu.h> 21#include <linux/nvgpu.h>
22#include <uapi/linux/nvgpu.h> 22#include <uapi/linux/nvgpu.h>
23 23
24#include "gr_ops.h"
25#include "gk20a.h" 24#include "gk20a.h"
26#include "fence_gk20a.h" 25#include "fence_gk20a.h"
27 26
@@ -275,7 +274,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
275 if (zcull_info == NULL) 274 if (zcull_info == NULL)
276 return -ENOMEM; 275 return -ENOMEM;
277 276
278 err = g->ops.gr->get_zcull_info(g, &g->gr, zcull_info); 277 err = g->ops.gr.get_zcull_info(g, &g->gr, zcull_info);
279 if (err) { 278 if (err) {
280 kfree(zcull_info); 279 kfree(zcull_info);
281 break; 280 break;
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 347765aa..ed730174 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1265,8 +1265,8 @@ void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids,
1265 if (verbose) 1265 if (verbose)
1266 gk20a_debug_dump(g->dev); 1266 gk20a_debug_dump(g->dev);
1267 1267
1268 if (g->ops.ltc->flush) 1268 if (g->ops.ltc.flush)
1269 g->ops.ltc->flush(g); 1269 g->ops.ltc.flush(g);
1270 1270
1271 /* store faulted engines in advance */ 1271 /* store faulted engines in advance */
1272 g->fifo.mmu_fault_engines = 0; 1272 g->fifo.mmu_fault_engines = 0;
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 5dda7d74..cea53e00 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -612,7 +612,7 @@ static irqreturn_t gk20a_intr_thread_stall(int irq, void *dev_id)
612 if (mc_intr_0 & mc_intr_0_priv_ring_pending_f()) 612 if (mc_intr_0 & mc_intr_0_priv_ring_pending_f())
613 gk20a_priv_ring_isr(g); 613 gk20a_priv_ring_isr(g);
614 if (mc_intr_0 & mc_intr_0_ltc_pending_f()) 614 if (mc_intr_0 & mc_intr_0_ltc_pending_f())
615 g->ops.ltc->isr(g); 615 g->ops.ltc.isr(g);
616 if (mc_intr_0 & mc_intr_0_pbus_pending_f()) 616 if (mc_intr_0 & mc_intr_0_pbus_pending_f())
617 gk20a_pbus_isr(g); 617 gk20a_pbus_isr(g);
618 618
@@ -881,8 +881,8 @@ static int gk20a_pm_finalize_poweron(struct device *dev)
881 goto done; 881 goto done;
882 } 882 }
883 883
884 if (g->ops.ltc->init_fs_state) 884 if (g->ops.ltc.init_fs_state)
885 g->ops.ltc->init_fs_state(g); 885 g->ops.ltc.init_fs_state(g);
886 886
887 err = gk20a_init_mm_support(g); 887 err = gk20a_init_mm_support(g);
888 if (err) { 888 if (err) {
@@ -1818,7 +1818,7 @@ int gk20a_init_gpu_characteristics(struct gk20a *g)
1818{ 1818{
1819 struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; 1819 struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics;
1820 1820
1821 gpu->L2_cache_size = g->ops.ltc->determine_L2_size_bytes(g); 1821 gpu->L2_cache_size = g->ops.ltc.determine_L2_size_bytes(g);
1822 gpu->on_board_video_memory_size = 0; /* integrated GPU */ 1822 gpu->on_board_video_memory_size = 0; /* integrated GPU */
1823 1823
1824 gpu->num_gpc = g->gr.gpc_count; 1824 gpu->num_gpc = g->gr.gpc_count;
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 2c3fb400..5669e1c5 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -33,7 +33,7 @@ struct acr_gm20b;
33#include <linux/tegra-soc.h> 33#include <linux/tegra-soc.h>
34 34
35#include "../../../arch/arm/mach-tegra/iomap.h" 35#include "../../../arch/arm/mach-tegra/iomap.h"
36#include "nvgpu_gpuid.h" 36
37#include "as_gk20a.h" 37#include "as_gk20a.h"
38#include "clk_gk20a.h" 38#include "clk_gk20a.h"
39#include "fifo_gk20a.h" 39#include "fifo_gk20a.h"
@@ -60,33 +60,81 @@ enum gk20a_cbc_op {
60 gk20a_cbc_op_invalidate, 60 gk20a_cbc_op_invalidate,
61}; 61};
62 62
63struct gpu_ltc_ops {
64 int (*determine_L2_size_bytes)(struct gk20a *gk20a);
65 void (*set_max_ways_evict_last)(struct gk20a *g, u32 max_ways);
66 int (*init_comptags)(struct gk20a *g, struct gr_gk20a *gr);
67 int (*cbc_ctrl)(struct gk20a *g, enum gk20a_cbc_op op,
68 u32 min, u32 max);
69 void (*set_zbc_color_entry)(struct gk20a *g,
70 struct zbc_entry *color_val,
71 u32 index);
72 void (*set_zbc_depth_entry)(struct gk20a *g,
73 struct zbc_entry *depth_val,
74 u32 index);
75 void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr);
76 void (*sync_debugfs)(struct gk20a *g);
77 void (*init_fs_state)(struct gk20a *g);
78 void (*elpg_flush)(struct gk20a *g);
79 void (*isr)(struct gk20a *g);
80 u32 (*cbc_fix_config)(struct gk20a *g, int base);
81 void (*flush)(struct gk20a *g);
82};
83
84struct gpu_ltc_ops;
85struct gpu_gr_ops;
86
87struct gpu_ops { 63struct gpu_ops {
88 const struct gpu_ltc_ops *ltc; 64 struct {
89 const struct gpu_gr_ops *gr; 65 int (*determine_L2_size_bytes)(struct gk20a *gk20a);
66 void (*set_max_ways_evict_last)(struct gk20a *g, u32 max_ways);
67 int (*init_comptags)(struct gk20a *g, struct gr_gk20a *gr);
68 int (*cbc_ctrl)(struct gk20a *g, enum gk20a_cbc_op op,
69 u32 min, u32 max);
70 void (*set_zbc_color_entry)(struct gk20a *g,
71 struct zbc_entry *color_val,
72 u32 index);
73 void (*set_zbc_depth_entry)(struct gk20a *g,
74 struct zbc_entry *depth_val,
75 u32 index);
76 void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr);
77 void (*sync_debugfs)(struct gk20a *g);
78 void (*init_fs_state)(struct gk20a *g);
79 void (*elpg_flush)(struct gk20a *g);
80 void (*isr)(struct gk20a *g);
81 u32 (*cbc_fix_config)(struct gk20a *g, int base);
82 void (*flush)(struct gk20a *g);
83 } ltc;
84 struct {
85 int (*init_fs_state)(struct gk20a *g);
86 void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset);
87 void (*bundle_cb_defaults)(struct gk20a *g);
88 void (*cb_size_default)(struct gk20a *g);
89 int (*calc_global_ctx_buffer_size)(struct gk20a *g);
90 void (*commit_global_attrib_cb)(struct gk20a *g,
91 struct channel_ctx_gk20a *ch_ctx,
92 u64 addr, bool patch);
93 void (*commit_global_bundle_cb)(struct gk20a *g,
94 struct channel_ctx_gk20a *ch_ctx,
95 u64 addr, u64 size, bool patch);
96 int (*commit_global_cb_manager)(struct gk20a *g,
97 struct channel_gk20a *ch,
98 bool patch);
99 void (*commit_global_pagepool)(struct gk20a *g,
100 struct channel_ctx_gk20a *ch_ctx,
101 u64 addr, u32 size, bool patch);
102 void (*init_gpc_mmu)(struct gk20a *g);
103 int (*handle_sw_method)(struct gk20a *g, u32 addr,
104 u32 class_num, u32 offset, u32 data);
105 void (*set_alpha_circular_buffer_size)(struct gk20a *g,
106 u32 data);
107 void (*set_circular_buffer_size)(struct gk20a *g, u32 data);
108 void (*enable_hww_exceptions)(struct gk20a *g);
109 bool (*is_valid_class)(struct gk20a *g, u32 class_num);
110 void (*get_sm_dsm_perf_regs)(struct gk20a *g,
111 u32 *num_sm_dsm_perf_regs,
112 u32 **sm_dsm_perf_regs,
113 u32 *perf_register_stride);
114 void (*get_sm_dsm_perf_ctrl_regs)(struct gk20a *g,
115 u32 *num_sm_dsm_perf_regs,
116 u32 **sm_dsm_perf_regs,
117 u32 *perf_register_stride);
118 void (*set_hww_esr_report_mask)(struct gk20a *g);
119 int (*setup_alpha_beta_tables)(struct gk20a *g,
120 struct gr_gk20a *gr);
121 int (*falcon_load_ucode)(struct gk20a *g,
122 u64 addr_base,
123 struct gk20a_ctxsw_ucode_segments *segments,
124 u32 reg_offset);
125 int (*load_ctxsw_ucode)(struct gk20a *g);
126 u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index);
127 void (*free_channel_ctx)(struct channel_gk20a *c);
128 int (*alloc_obj_ctx)(struct channel_gk20a *c,
129 struct nvgpu_alloc_obj_ctx_args *args);
130 int (*free_obj_ctx)(struct channel_gk20a *c,
131 struct nvgpu_free_obj_ctx_args *args);
132 int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr,
133 struct channel_gk20a *c, u64 zcull_va,
134 u32 mode);
135 int (*get_zcull_info)(struct gk20a *g, struct gr_gk20a *gr,
136 struct gr_zcull_info *zcull_params);
137 } gr;
90 const char *name; 138 const char *name;
91 struct { 139 struct {
92 void (*init_fs_state)(struct gk20a *g); 140 void (*init_fs_state)(struct gk20a *g);
@@ -672,6 +720,18 @@ int __gk20a_do_unidle(struct platform_device *pdev);
672const struct firmware * 720const struct firmware *
673gk20a_request_firmware(struct gk20a *g, const char *fw_name); 721gk20a_request_firmware(struct gk20a *g, const char *fw_name);
674 722
723#define NVGPU_GPU_ARCHITECTURE_SHIFT 4
724
725/* constructs unique and compact GPUID from nvgpu_gpu_characteristics
726 * arch/impl fields */
727#define GK20A_GPUID(arch, impl) ((u32) ((arch) | (impl)))
728
729#define GK20A_GPUID_GK20A \
730 GK20A_GPUID(NVGPU_GPU_ARCH_GK100, NVGPU_GPU_IMPL_GK20A)
731
732#define GK20A_GPUID_GM20B \
733 GK20A_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM20B)
734
675int gk20a_init_gpu_characteristics(struct gk20a *g); 735int gk20a_init_gpu_characteristics(struct gk20a *g);
676 736
677int gk20a_user_init(struct platform_device *dev); 737int gk20a_user_init(struct platform_device *dev);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
index 2abb0e9d..52a34086 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
@@ -26,7 +26,6 @@
26 26
27#include <mach/clk.h> 27#include <mach/clk.h>
28 28
29#include "gr_ops.h"
30#include "gk20a.h" 29#include "gk20a.h"
31#include "gr_gk20a.h" 30#include "gr_gk20a.h"
32#include "fifo_gk20a.h" 31#include "fifo_gk20a.h"
@@ -624,9 +623,9 @@ static ssize_t tpc_fs_mask_read(struct device *device,
624 u32 tpc_fs_mask = 0; 623 u32 tpc_fs_mask = 0;
625 624
626 for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { 625 for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
627 if (g->ops.gr->get_gpc_tpc_mask) 626 if (g->ops.gr.get_gpc_tpc_mask)
628 tpc_fs_mask |= 627 tpc_fs_mask |=
629 g->ops.gr->get_gpc_tpc_mask(g, gpc_index) << 628 g->ops.gr.get_gpc_tpc_mask(g, gpc_index) <<
630 (gr->max_tpc_per_gpc_count * gpc_index); 629 (gr->max_tpc_per_gpc_count * gpc_index);
631 } 630 }
632 631
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index dddec803..524547e7 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -27,7 +27,6 @@
27#include <linux/firmware.h> 27#include <linux/firmware.h>
28#include <linux/nvhost.h> 28#include <linux/nvhost.h>
29 29
30#include "gr_ops.h"
31#include "gk20a.h" 30#include "gk20a.h"
32#include "kind_gk20a.h" 31#include "kind_gk20a.h"
33#include "gr_ctx_gk20a.h" 32#include "gr_ctx_gk20a.h"
@@ -66,6 +65,11 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g,
66 struct channel_gk20a *c); 65 struct channel_gk20a *c);
67static void gr_gk20a_unmap_global_ctx_buffers(struct channel_gk20a *c); 66static void gr_gk20a_unmap_global_ctx_buffers(struct channel_gk20a *c);
68 67
68/* channel gr ctx buffer */
69static int gr_gk20a_alloc_channel_gr_ctx(struct gk20a *g,
70 struct channel_gk20a *c);
71static void gr_gk20a_free_channel_gr_ctx(struct channel_gk20a *c);
72
69/* channel patch ctx buffer */ 73/* channel patch ctx buffer */
70static int gr_gk20a_alloc_channel_patch_ctx(struct gk20a *g, 74static int gr_gk20a_alloc_channel_patch_ctx(struct gk20a *g,
71 struct channel_gk20a *c); 75 struct channel_gk20a *c);
@@ -747,7 +751,7 @@ clean_up:
747 return ret; 751 return ret;
748} 752}
749 753
750int gr_gk20a_commit_global_cb_manager(struct gk20a *g, 754static int gr_gk20a_commit_global_cb_manager(struct gk20a *g,
751 struct channel_gk20a *c, bool patch) 755 struct channel_gk20a *c, bool patch)
752{ 756{
753 struct gr_gk20a *gr = &g->gr; 757 struct gr_gk20a *gr = &g->gr;
@@ -852,7 +856,7 @@ static int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g,
852 gk20a_dbg_info("pagepool buffer addr : 0x%016llx, size : %d", 856 gk20a_dbg_info("pagepool buffer addr : 0x%016llx, size : %d",
853 addr, size); 857 addr, size);
854 858
855 g->ops.gr->commit_global_pagepool(g, ch_ctx, addr, size, patch); 859 g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, patch);
856 860
857 /* global bundle cb */ 861 /* global bundle cb */
858 addr = (u64_lo32(ch_ctx->global_ctx_buffer_va[CIRCULAR_VA]) >> 862 addr = (u64_lo32(ch_ctx->global_ctx_buffer_va[CIRCULAR_VA]) >>
@@ -865,7 +869,7 @@ static int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g,
865 gk20a_dbg_info("bundle cb addr : 0x%016llx, size : %d", 869 gk20a_dbg_info("bundle cb addr : 0x%016llx, size : %d",
866 addr, size); 870 addr, size);
867 871
868 g->ops.gr->commit_global_bundle_cb(g, ch_ctx, addr, size, patch); 872 g->ops.gr.commit_global_bundle_cb(g, ch_ctx, addr, size, patch);
869 873
870 /* global attrib cb */ 874 /* global attrib cb */
871 addr = (u64_lo32(ch_ctx->global_ctx_buffer_va[ATTRIBUTE_VA]) >> 875 addr = (u64_lo32(ch_ctx->global_ctx_buffer_va[ATTRIBUTE_VA]) >>
@@ -874,7 +878,7 @@ static int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g,
874 (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v())); 878 (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()));
875 879
876 gk20a_dbg_info("attrib cb addr : 0x%016llx", addr); 880 gk20a_dbg_info("attrib cb addr : 0x%016llx", addr);
877 g->ops.gr->commit_global_attrib_cb(g, ch_ctx, addr, patch); 881 g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, patch);
878 882
879 if (patch) 883 if (patch)
880 gr_gk20a_ctx_patch_write_end(g, ch_ctx); 884 gr_gk20a_ctx_patch_write_end(g, ch_ctx);
@@ -882,7 +886,7 @@ static int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g,
882 return 0; 886 return 0;
883} 887}
884 888
885void gr_gk20a_commit_global_attrib_cb(struct gk20a *g, 889static void gr_gk20a_commit_global_attrib_cb(struct gk20a *g,
886 struct channel_ctx_gk20a *ch_ctx, 890 struct channel_ctx_gk20a *ch_ctx,
887 u64 addr, bool patch) 891 u64 addr, bool patch)
888{ 892{
@@ -895,7 +899,7 @@ void gr_gk20a_commit_global_attrib_cb(struct gk20a *g,
895 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(), patch); 899 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(), patch);
896} 900}
897 901
898void gr_gk20a_commit_global_bundle_cb(struct gk20a *g, 902static void gr_gk20a_commit_global_bundle_cb(struct gk20a *g,
899 struct channel_ctx_gk20a *ch_ctx, 903 struct channel_ctx_gk20a *ch_ctx,
900 u64 addr, u64 size, bool patch) 904 u64 addr, u64 size, bool patch)
901{ 905{
@@ -1149,7 +1153,7 @@ static inline u32 clear_count_bits(u32 num, u32 clear_count)
1149 return num; 1153 return num;
1150} 1154}
1151 1155
1152int gr_gk20a_setup_alpha_beta_tables(struct gk20a *g, 1156static int gr_gk20a_setup_alpha_beta_tables(struct gk20a *g,
1153 struct gr_gk20a *gr) 1157 struct gr_gk20a *gr)
1154{ 1158{
1155 u32 table_index_bits = 5; 1159 u32 table_index_bits = 5;
@@ -1253,7 +1257,7 @@ static u32 gr_gk20a_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
1253 return 0x1; 1257 return 0x1;
1254} 1258}
1255 1259
1256int gr_gk20a_init_fs_state(struct gk20a *g) 1260static int gr_gk20a_ctx_state_floorsweep(struct gk20a *g)
1257{ 1261{
1258 struct gr_gk20a *gr = &g->gr; 1262 struct gr_gk20a *gr = &g->gr;
1259 u32 tpc_index, gpc_index; 1263 u32 tpc_index, gpc_index;
@@ -1315,14 +1319,14 @@ int gr_gk20a_init_fs_state(struct gk20a *g)
1315 1319
1316 /* gr__setup_pd_mapping stubbed for gk20a */ 1320 /* gr__setup_pd_mapping stubbed for gk20a */
1317 gr_gk20a_setup_rop_mapping(g, gr); 1321 gr_gk20a_setup_rop_mapping(g, gr);
1318 if (g->ops.gr->setup_alpha_beta_tables) 1322 if (g->ops.gr.setup_alpha_beta_tables)
1319 g->ops.gr->setup_alpha_beta_tables(g, gr); 1323 g->ops.gr.setup_alpha_beta_tables(g, gr);
1320 1324
1321 if (gr->num_fbps == 1) 1325 if (gr->num_fbps == 1)
1322 max_ways_evict = 9; 1326 max_ways_evict = 9;
1323 1327
1324 if (max_ways_evict != INVALID_MAX_WAYS) 1328 if (max_ways_evict != INVALID_MAX_WAYS)
1325 g->ops.ltc->set_max_ways_evict_last(g, max_ways_evict); 1329 g->ops.ltc.set_max_ways_evict_last(g, max_ways_evict);
1326 1330
1327 for (gpc_index = 0; 1331 for (gpc_index = 0;
1328 gpc_index < gr_pd_dist_skip_table__size_1_v() * 4; 1332 gpc_index < gr_pd_dist_skip_table__size_1_v() * 4;
@@ -2093,7 +2097,7 @@ void gr_gk20a_load_ctxsw_ucode_boot(struct gk20a *g, u64 addr_base,
2093 gr_fecs_bootvec_vec_f(segments->boot_entry)); 2097 gr_fecs_bootvec_vec_f(segments->boot_entry));
2094} 2098}
2095 2099
2096int gr_gk20a_falcon_load_ucode(struct gk20a *g, u64 addr_base, 2100int gr_gk20a_load_ctxsw_ucode_segments(struct gk20a *g, u64 addr_base,
2097 struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset) 2101 struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset)
2098{ 2102{
2099 gk20a_writel(g, reg_offset + gr_fecs_dmactl_r(), 2103 gk20a_writel(g, reg_offset + gr_fecs_dmactl_r(),
@@ -2119,10 +2123,10 @@ static void gr_gk20a_load_falcon_with_bootloader(struct gk20a *g)
2119 2123
2120 gr_gk20a_load_falcon_bind_instblk(g); 2124 gr_gk20a_load_falcon_bind_instblk(g);
2121 2125
2122 g->ops.gr->falcon_load_ucode(g, addr_base, 2126 g->ops.gr.falcon_load_ucode(g, addr_base,
2123 &g->ctxsw_ucode_info.fecs, 0); 2127 &g->ctxsw_ucode_info.fecs, 0);
2124 2128
2125 g->ops.gr->falcon_load_ucode(g, addr_base, 2129 g->ops.gr.falcon_load_ucode(g, addr_base,
2126 &g->ctxsw_ucode_info.gpccs, 2130 &g->ctxsw_ucode_info.gpccs,
2127 gr_gpcs_gpccs_falcon_hwcfg_r() - 2131 gr_gpcs_gpccs_falcon_hwcfg_r() -
2128 gr_fecs_falcon_hwcfg_r()); 2132 gr_fecs_falcon_hwcfg_r());
@@ -2293,7 +2297,7 @@ static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g)
2293 2297
2294 gk20a_dbg_fn(""); 2298 gk20a_dbg_fn("");
2295 2299
2296 attr_buffer_size = g->ops.gr->calc_global_ctx_buffer_size(g); 2300 attr_buffer_size = g->ops.gr.calc_global_ctx_buffer_size(g);
2297 2301
2298 gk20a_dbg_info("cb_buffer_size : %d", cb_buffer_size); 2302 gk20a_dbg_info("cb_buffer_size : %d", cb_buffer_size);
2299 2303
@@ -2628,7 +2632,7 @@ void gr_gk20a_free_tsg_gr_ctx(struct tsg_gk20a *tsg)
2628 __gr_gk20a_free_gr_ctx(tsg->g, tsg->vm, tsg->tsg_gr_ctx); 2632 __gr_gk20a_free_gr_ctx(tsg->g, tsg->vm, tsg->tsg_gr_ctx);
2629} 2633}
2630 2634
2631void gr_gk20a_free_channel_gr_ctx(struct channel_gk20a *c) 2635static void gr_gk20a_free_channel_gr_ctx(struct channel_gk20a *c)
2632{ 2636{
2633 __gr_gk20a_free_gr_ctx(c->g, c->vm, c->ch_ctx.gr_ctx); 2637 __gr_gk20a_free_gr_ctx(c->g, c->vm, c->ch_ctx.gr_ctx);
2634} 2638}
@@ -2715,7 +2719,7 @@ static void gr_gk20a_free_channel_patch_ctx(struct channel_gk20a *c)
2715 } 2719 }
2716} 2720}
2717 2721
2718void gr_gk20a_free_channel_ctx(struct channel_gk20a *c) 2722void gk20a_free_channel_ctx(struct channel_gk20a *c)
2719{ 2723{
2720 gr_gk20a_unmap_global_ctx_buffers(c); 2724 gr_gk20a_unmap_global_ctx_buffers(c);
2721 gr_gk20a_free_channel_patch_ctx(c); 2725 gr_gk20a_free_channel_patch_ctx(c);
@@ -2730,7 +2734,7 @@ void gr_gk20a_free_channel_ctx(struct channel_gk20a *c)
2730 c->first_init = false; 2734 c->first_init = false;
2731} 2735}
2732 2736
2733bool gr_gk20a_is_valid_class(struct gk20a *g, u32 class_num) 2737static bool gr_gk20a_is_valid_class(struct gk20a *g, u32 class_num)
2734{ 2738{
2735 bool valid = false; 2739 bool valid = false;
2736 2740
@@ -2749,7 +2753,7 @@ bool gr_gk20a_is_valid_class(struct gk20a *g, u32 class_num)
2749 return valid; 2753 return valid;
2750} 2754}
2751 2755
2752int gr_gk20a_alloc_obj_ctx(struct channel_gk20a *c, 2756int gk20a_alloc_obj_ctx(struct channel_gk20a *c,
2753 struct nvgpu_alloc_obj_ctx_args *args) 2757 struct nvgpu_alloc_obj_ctx_args *args)
2754{ 2758{
2755 struct gk20a *g = c->g; 2759 struct gk20a *g = c->g;
@@ -2768,7 +2772,7 @@ int gr_gk20a_alloc_obj_ctx(struct channel_gk20a *c,
2768 return -EINVAL; 2772 return -EINVAL;
2769 } 2773 }
2770 2774
2771 if (!g->ops.gr->is_valid_class(g, args->class_num)) { 2775 if (!g->ops.gr.is_valid_class(g, args->class_num)) {
2772 gk20a_err(dev_from_gk20a(g), 2776 gk20a_err(dev_from_gk20a(g),
2773 "invalid obj class 0x%x", args->class_num); 2777 "invalid obj class 0x%x", args->class_num);
2774 err = -EINVAL; 2778 err = -EINVAL;
@@ -2912,7 +2916,7 @@ out:
2912 return err; 2916 return err;
2913} 2917}
2914 2918
2915int gr_gk20a_free_obj_ctx(struct channel_gk20a *c, 2919int gk20a_free_obj_ctx(struct channel_gk20a *c,
2916 struct nvgpu_free_obj_ctx_args *args) 2920 struct nvgpu_free_obj_ctx_args *args)
2917{ 2921{
2918 unsigned long timeout = gk20a_get_gr_idle_timeout(c->g); 2922 unsigned long timeout = gk20a_get_gr_idle_timeout(c->g);
@@ -3004,7 +3008,7 @@ static void gk20a_remove_gr_support(struct gr_gk20a *gr)
3004 gk20a_allocator_destroy(&gr->comp_tags); 3008 gk20a_allocator_destroy(&gr->comp_tags);
3005} 3009}
3006 3010
3007void gr_gk20a_bundle_cb_defaults(struct gk20a *g) 3011static void gr_gk20a_bundle_cb_defaults(struct gk20a *g)
3008{ 3012{
3009 struct gr_gk20a *gr = &g->gr; 3013 struct gr_gk20a *gr = &g->gr;
3010 3014
@@ -3085,9 +3089,9 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
3085 gr->gpc_ppc_count[gpc_index] = gr->pe_count_per_gpc; 3089 gr->gpc_ppc_count[gpc_index] = gr->pe_count_per_gpc;
3086 gr->ppc_count += gr->gpc_ppc_count[gpc_index]; 3090 gr->ppc_count += gr->gpc_ppc_count[gpc_index];
3087 3091
3088 if (g->ops.gr->get_gpc_tpc_mask) 3092 if (g->ops.gr.get_gpc_tpc_mask)
3089 gr->gpc_tpc_mask[gpc_index] = 3093 gr->gpc_tpc_mask[gpc_index] =
3090 g->ops.gr->get_gpc_tpc_mask(g, gpc_index); 3094 g->ops.gr.get_gpc_tpc_mask(g, gpc_index);
3091 3095
3092 for (pes_index = 0; pes_index < gr->pe_count_per_gpc; pes_index++) { 3096 for (pes_index = 0; pes_index < gr->pe_count_per_gpc; pes_index++) {
3093 3097
@@ -3170,9 +3174,9 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
3170 pes_index, gpc_index, 3174 pes_index, gpc_index,
3171 gr->pes_tpc_mask[pes_index][gpc_index]); 3175 gr->pes_tpc_mask[pes_index][gpc_index]);
3172 3176
3173 g->ops.gr->bundle_cb_defaults(g); 3177 g->ops.gr.bundle_cb_defaults(g);
3174 g->ops.gr->cb_size_default(g); 3178 g->ops.gr.cb_size_default(g);
3175 g->ops.gr->calc_global_ctx_buffer_size(g); 3179 g->ops.gr.calc_global_ctx_buffer_size(g);
3176 gr->timeslice_mode = gr_gpcs_ppcs_cbm_cfg_timeslice_mode_enable_v(); 3180 gr->timeslice_mode = gr_gpcs_ppcs_cbm_cfg_timeslice_mode_enable_v();
3177 3181
3178 gk20a_dbg_info("bundle_cb_default_size: %d", 3182 gk20a_dbg_info("bundle_cb_default_size: %d",
@@ -3502,7 +3506,7 @@ static int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
3502 } 3506 }
3503 3507
3504 /* update l2 table */ 3508 /* update l2 table */
3505 g->ops.ltc->set_zbc_color_entry(g, color_val, index); 3509 g->ops.ltc.set_zbc_color_entry(g, color_val, index);
3506 3510
3507 /* update ds table */ 3511 /* update ds table */
3508 gk20a_writel(g, gr_ds_zbc_color_r_r(), 3512 gk20a_writel(g, gr_ds_zbc_color_r_r(),
@@ -3568,7 +3572,7 @@ static int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
3568 } 3572 }
3569 3573
3570 /* update l2 table */ 3574 /* update l2 table */
3571 g->ops.ltc->set_zbc_depth_entry(g, depth_val, index); 3575 g->ops.ltc.set_zbc_depth_entry(g, depth_val, index);
3572 3576
3573 /* update ds table */ 3577 /* update ds table */
3574 gk20a_writel(g, gr_ds_zbc_z_r(), 3578 gk20a_writel(g, gr_ds_zbc_z_r(),
@@ -4168,7 +4172,7 @@ void gr_gk20a_enable_hww_exceptions(struct gk20a *g)
4168 gr_ds_hww_report_mask_sph23_err_report_f()); 4172 gr_ds_hww_report_mask_sph23_err_report_f());
4169} 4173}
4170 4174
4171void gr_gk20a_set_hww_esr_report_mask(struct gk20a *g) 4175static void gr_gk20a_set_hww_esr_report_mask(struct gk20a *g)
4172{ 4176{
4173 /* setup sm warp esr report masks */ 4177 /* setup sm warp esr report masks */
4174 gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(), 4178 gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(),
@@ -4236,8 +4240,8 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4236 fb_mmu_debug_rd_vol_false_f() | 4240 fb_mmu_debug_rd_vol_false_f() |
4237 fb_mmu_debug_rd_addr_f(addr)); 4241 fb_mmu_debug_rd_addr_f(addr));
4238 4242
4239 if (g->ops.gr->init_gpc_mmu) 4243 if (g->ops.gr.init_gpc_mmu)
4240 g->ops.gr->init_gpc_mmu(g); 4244 g->ops.gr.init_gpc_mmu(g);
4241 4245
4242 /* load gr floorsweeping registers */ 4246 /* load gr floorsweeping registers */
4243 data = gk20a_readl(g, gr_gpc0_ppc0_pes_vsc_strem_r()); 4247 data = gk20a_readl(g, gr_gpc0_ppc0_pes_vsc_strem_r());
@@ -4280,8 +4284,8 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4280 gr_fecs_host_int_enable_umimp_illegal_method_enable_f() | 4284 gr_fecs_host_int_enable_umimp_illegal_method_enable_f() |
4281 gr_fecs_host_int_enable_watchdog_enable_f()); 4285 gr_fecs_host_int_enable_watchdog_enable_f());
4282 4286
4283 g->ops.gr->enable_hww_exceptions(g); 4287 g->ops.gr.enable_hww_exceptions(g);
4284 g->ops.gr->set_hww_esr_report_mask(g); 4288 g->ops.gr.set_hww_esr_report_mask(g);
4285 4289
4286 /* enable TPC exceptions per GPC */ 4290 /* enable TPC exceptions per GPC */
4287 gk20a_gr_enable_gpc_exceptions(g); 4291 gk20a_gr_enable_gpc_exceptions(g);
@@ -4306,7 +4310,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4306 else 4310 else
4307 gr_gk20a_load_zbc_default_table(g, gr); 4311 gr_gk20a_load_zbc_default_table(g, gr);
4308 4312
4309 g->ops.ltc->init_cbc(g, gr); 4313 g->ops.ltc.init_cbc(g, gr);
4310 4314
4311 /* load ctx init */ 4315 /* load ctx init */
4312 for (i = 0; i < sw_ctx_load->count; i++) 4316 for (i = 0; i < sw_ctx_load->count; i++)
@@ -4325,11 +4329,11 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4325 gr_fe_go_idle_timeout_count_disabled_f()); 4329 gr_fe_go_idle_timeout_count_disabled_f());
4326 4330
4327 /* override a few ctx state registers */ 4331 /* override a few ctx state registers */
4328 g->ops.gr->commit_global_cb_manager(g, NULL, false); 4332 g->ops.gr.commit_global_cb_manager(g, NULL, false);
4329 gr_gk20a_commit_global_timeslice(g, NULL, false); 4333 gr_gk20a_commit_global_timeslice(g, NULL, false);
4330 4334
4331 /* floorsweep anything left */ 4335 /* floorsweep anything left */
4332 g->ops.gr->init_fs_state(g); 4336 g->ops.gr.init_fs_state(g);
4333 4337
4334 err = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); 4338 err = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT);
4335 if (err) 4339 if (err)
@@ -4450,7 +4454,7 @@ int gr_gk20a_init_ctxsw(struct gk20a *g)
4450 struct gr_gk20a *gr = &g->gr; 4454 struct gr_gk20a *gr = &g->gr;
4451 u32 err = 0; 4455 u32 err = 0;
4452 4456
4453 err = g->ops.gr->load_ctxsw_ucode(g); 4457 err = g->ops.gr.load_ctxsw_ucode(g);
4454 if (err) 4458 if (err)
4455 goto out; 4459 goto out;
4456 4460
@@ -4592,7 +4596,7 @@ static int gk20a_init_gr_setup_sw(struct gk20a *g)
4592 gk20a_dbg_info("total ram pages : %lu", totalram_pages); 4596 gk20a_dbg_info("total ram pages : %lu", totalram_pages);
4593 gr->max_comptag_mem = totalram_pages 4597 gr->max_comptag_mem = totalram_pages
4594 >> (10 - (PAGE_SHIFT - 10)); 4598 >> (10 - (PAGE_SHIFT - 10));
4595 err = g->ops.ltc->init_comptags(g, gr); 4599 err = g->ops.ltc.init_comptags(g, gr);
4596 if (err) 4600 if (err)
4597 goto clean_up; 4601 goto clean_up;
4598 4602
@@ -4809,7 +4813,7 @@ void gk20a_gr_set_shader_exceptions(struct gk20a *g, u32 data)
4809 } 4813 }
4810} 4814}
4811 4815
4812void gr_gk20a_set_circular_buffer_size(struct gk20a *g, u32 data) 4816static void gk20a_gr_set_circular_buffer_size(struct gk20a *g, u32 data)
4813{ 4817{
4814 struct gr_gk20a *gr = &g->gr; 4818 struct gr_gk20a *gr = &g->gr;
4815 u32 gpc_index, ppc_index, stride, val, offset; 4819 u32 gpc_index, ppc_index, stride, val, offset;
@@ -4860,7 +4864,7 @@ void gr_gk20a_set_circular_buffer_size(struct gk20a *g, u32 data)
4860 } 4864 }
4861} 4865}
4862 4866
4863void gr_gk20a_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) 4867static void gk20a_gr_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
4864{ 4868{
4865 struct gr_gk20a *gr = &g->gr; 4869 struct gr_gk20a *gr = &g->gr;
4866 u32 gpc_index, ppc_index, stride, val; 4870 u32 gpc_index, ppc_index, stride, val;
@@ -4969,7 +4973,7 @@ int gk20a_gr_reset(struct gk20a *g)
4969 return 0; 4973 return 0;
4970} 4974}
4971 4975
4972int gr_gk20a_handle_sw_method(struct gk20a *g, u32 addr, 4976static int gr_gk20a_handle_sw_method(struct gk20a *g, u32 addr,
4973 u32 class_num, u32 offset, u32 data) 4977 u32 class_num, u32 offset, u32 data)
4974{ 4978{
4975 gk20a_dbg_fn(""); 4979 gk20a_dbg_fn("");
@@ -4990,10 +4994,10 @@ int gr_gk20a_handle_sw_method(struct gk20a *g, u32 addr,
4990 gk20a_gr_set_shader_exceptions(g, data); 4994 gk20a_gr_set_shader_exceptions(g, data);
4991 break; 4995 break;
4992 case NVA297_SET_CIRCULAR_BUFFER_SIZE: 4996 case NVA297_SET_CIRCULAR_BUFFER_SIZE:
4993 g->ops.gr->set_circular_buffer_size(g, data); 4997 g->ops.gr.set_circular_buffer_size(g, data);
4994 break; 4998 break;
4995 case NVA297_SET_ALPHA_CIRCULAR_BUFFER_SIZE: 4999 case NVA297_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
4996 g->ops.gr->set_alpha_circular_buffer_size(g, data); 5000 g->ops.gr.set_alpha_circular_buffer_size(g, data);
4997 break; 5001 break;
4998 default: 5002 default:
4999 goto fail; 5003 goto fail;
@@ -5035,7 +5039,7 @@ static int gk20a_gr_intr_illegal_notify_pending(struct gk20a *g,
5035static int gk20a_gr_handle_illegal_method(struct gk20a *g, 5039static int gk20a_gr_handle_illegal_method(struct gk20a *g,
5036 struct gr_isr_data *isr_data) 5040 struct gr_isr_data *isr_data)
5037{ 5041{
5038 int ret = g->ops.gr->handle_sw_method(g, isr_data->addr, 5042 int ret = g->ops.gr.handle_sw_method(g, isr_data->addr,
5039 isr_data->class_num, isr_data->offset, 5043 isr_data->class_num, isr_data->offset,
5040 isr_data->data_lo); 5044 isr_data->data_lo);
5041 if (ret) 5045 if (ret)
@@ -6233,7 +6237,7 @@ int gr_gk20a_ctx_patch_smpc(struct gk20a *g,
6233 return 0; 6237 return 0;
6234} 6238}
6235 6239
6236void gr_gk20a_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset) 6240static void gr_gk20a_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset)
6237{ 6241{
6238 u32 reg; 6242 u32 reg;
6239 u32 quad_ctrl; 6243 u32 quad_ctrl;
@@ -6405,7 +6409,7 @@ static int gr_gk20a_find_priv_offset_in_ext_buffer(struct gk20a *g,
6405 * by computing it from the base gpc/tpc strides. Then make sure 6409 * by computing it from the base gpc/tpc strides. Then make sure
6406 * it is a real match. 6410 * it is a real match.
6407 */ 6411 */
6408 g->ops.gr->get_sm_dsm_perf_regs(g, &num_sm_dsm_perf_regs, 6412 g->ops.gr.get_sm_dsm_perf_regs(g, &num_sm_dsm_perf_regs,
6409 &sm_dsm_perf_regs, 6413 &sm_dsm_perf_regs,
6410 &perf_register_stride); 6414 &perf_register_stride);
6411 6415
@@ -6436,7 +6440,7 @@ static int gr_gk20a_find_priv_offset_in_ext_buffer(struct gk20a *g,
6436 6440
6437 /* Didn't find reg in supported group 1. 6441 /* Didn't find reg in supported group 1.
6438 * so try the second group now */ 6442 * so try the second group now */
6439 g->ops.gr->get_sm_dsm_perf_ctrl_regs(g, &num_sm_dsm_perf_ctrl_regs, 6443 g->ops.gr.get_sm_dsm_perf_ctrl_regs(g, &num_sm_dsm_perf_ctrl_regs,
6440 &sm_dsm_perf_ctrl_regs, 6444 &sm_dsm_perf_ctrl_regs,
6441 &control_register_stride); 6445 &control_register_stride);
6442 6446
@@ -6893,8 +6897,8 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
6893 6897
6894 /* if this is a quad access, setup for special access*/ 6898 /* if this is a quad access, setup for special access*/
6895 if (ctx_ops[i].type == REGOP(TYPE_GR_CTX_QUAD) 6899 if (ctx_ops[i].type == REGOP(TYPE_GR_CTX_QUAD)
6896 && g->ops.gr->access_smpc_reg) 6900 && g->ops.gr.access_smpc_reg)
6897 g->ops.gr->access_smpc_reg(g, 6901 g->ops.gr.access_smpc_reg(g,
6898 ctx_ops[i].quad, 6902 ctx_ops[i].quad,
6899 ctx_ops[i].offset); 6903 ctx_ops[i].offset);
6900 offset = ctx_ops[i].offset; 6904 offset = ctx_ops[i].offset;
@@ -6997,8 +7001,8 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
6997 7001
6998 /* if this is a quad access, setup for special access*/ 7002 /* if this is a quad access, setup for special access*/
6999 if (ctx_ops[i].type == REGOP(TYPE_GR_CTX_QUAD) && 7003 if (ctx_ops[i].type == REGOP(TYPE_GR_CTX_QUAD) &&
7000 g->ops.gr->access_smpc_reg) 7004 g->ops.gr.access_smpc_reg)
7001 g->ops.gr->access_smpc_reg(g, ctx_ops[i].quad, 7005 g->ops.gr.access_smpc_reg(g, ctx_ops[i].quad,
7002 ctx_ops[i].offset); 7006 ctx_ops[i].offset);
7003 7007
7004 for (j = 0; j < num_offsets; j++) { 7008 for (j = 0; j < num_offsets; j++) {
@@ -7079,7 +7083,7 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
7079 return err; 7083 return err;
7080} 7084}
7081 7085
7082void gr_gk20a_cb_size_default(struct gk20a *g) 7086static void gr_gk20a_cb_size_default(struct gk20a *g)
7083{ 7087{
7084 struct gr_gk20a *gr = &g->gr; 7088 struct gr_gk20a *gr = &g->gr;
7085 7089
@@ -7089,7 +7093,7 @@ void gr_gk20a_cb_size_default(struct gk20a *g)
7089 gr_gpc0_ppc0_cbm_cfg2_size_default_v(); 7093 gr_gpc0_ppc0_cbm_cfg2_size_default_v();
7090} 7094}
7091 7095
7092int gr_gk20a_calc_global_ctx_buffer_size(struct gk20a *g) 7096static int gr_gk20a_calc_global_ctx_buffer_size(struct gk20a *g)
7093{ 7097{
7094 struct gr_gk20a *gr = &g->gr; 7098 struct gr_gk20a *gr = &g->gr;
7095 int size; 7099 int size;
@@ -7136,37 +7140,35 @@ void gk20a_init_gr(struct gk20a *g)
7136 init_waitqueue_head(&g->gr.init_wq); 7140 init_waitqueue_head(&g->gr.init_wq);
7137} 7141}
7138 7142
7139#include "gr_ops_gk20a.h"
7140static const struct gpu_gr_ops gk20a_gr_ops = {
7141 __set_gr_gk20a_op(access_smpc_reg),
7142 __set_gr_gk20a_op(bundle_cb_defaults),
7143 __set_gr_gk20a_op(cb_size_default),
7144 __set_gr_gk20a_op(calc_global_ctx_buffer_size),
7145 __set_gr_gk20a_op(commit_global_attrib_cb),
7146 __set_gr_gk20a_op(commit_global_bundle_cb),
7147 __set_gr_gk20a_op(commit_global_cb_manager),
7148 __set_gr_gk20a_op(commit_global_pagepool),
7149 __set_gr_gk20a_op(handle_sw_method),
7150 __set_gr_gk20a_op(set_alpha_circular_buffer_size),
7151 __set_gr_gk20a_op(set_circular_buffer_size),
7152 __set_gr_gk20a_op(enable_hww_exceptions),
7153 __set_gr_gk20a_op(is_valid_class),
7154 __set_gr_gk20a_op(get_sm_dsm_perf_regs),
7155 __set_gr_gk20a_op(get_sm_dsm_perf_ctrl_regs),
7156 __set_gr_gk20a_op(init_fs_state),
7157 __set_gr_gk20a_op(set_hww_esr_report_mask),
7158 __set_gr_gk20a_op(setup_alpha_beta_tables),
7159 __set_gr_gk20a_op(falcon_load_ucode),
7160 __set_gr_gk20a_op(load_ctxsw_ucode),
7161 __set_gr_gk20a_op(get_gpc_tpc_mask),
7162 __set_gr_gk20a_op(free_channel_ctx),
7163 __set_gr_gk20a_op(alloc_obj_ctx),
7164 __set_gr_gk20a_op(free_obj_ctx),
7165 __set_gr_gk20a_op(bind_ctxsw_zcull),
7166 __set_gr_gk20a_op(get_zcull_info)
7167};
7168
7169void gk20a_init_gr_ops(struct gpu_ops *gops) 7143void gk20a_init_gr_ops(struct gpu_ops *gops)
7170{ 7144{
7171 gops->gr = &gk20a_gr_ops; 7145 gops->gr.access_smpc_reg = gr_gk20a_access_smpc_reg;
7146 gops->gr.bundle_cb_defaults = gr_gk20a_bundle_cb_defaults;
7147 gops->gr.cb_size_default = gr_gk20a_cb_size_default;
7148 gops->gr.calc_global_ctx_buffer_size =
7149 gr_gk20a_calc_global_ctx_buffer_size;
7150 gops->gr.commit_global_attrib_cb = gr_gk20a_commit_global_attrib_cb;
7151 gops->gr.commit_global_bundle_cb = gr_gk20a_commit_global_bundle_cb;
7152 gops->gr.commit_global_cb_manager = gr_gk20a_commit_global_cb_manager;
7153 gops->gr.commit_global_pagepool = gr_gk20a_commit_global_pagepool;
7154 gops->gr.handle_sw_method = gr_gk20a_handle_sw_method;
7155 gops->gr.set_alpha_circular_buffer_size =
7156 gk20a_gr_set_circular_buffer_size;
7157 gops->gr.set_circular_buffer_size =
7158 gk20a_gr_set_alpha_circular_buffer_size;
7159 gops->gr.enable_hww_exceptions = gr_gk20a_enable_hww_exceptions;
7160 gops->gr.is_valid_class = gr_gk20a_is_valid_class;
7161 gops->gr.get_sm_dsm_perf_regs = gr_gk20a_get_sm_dsm_perf_regs;
7162 gops->gr.get_sm_dsm_perf_ctrl_regs = gr_gk20a_get_sm_dsm_perf_ctrl_regs;
7163 gops->gr.init_fs_state = gr_gk20a_ctx_state_floorsweep;
7164 gops->gr.set_hww_esr_report_mask = gr_gk20a_set_hww_esr_report_mask;
7165 gops->gr.setup_alpha_beta_tables = gr_gk20a_setup_alpha_beta_tables;
7166 gops->gr.falcon_load_ucode = gr_gk20a_load_ctxsw_ucode_segments;
7167 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
7168 gops->gr.get_gpc_tpc_mask = gr_gk20a_get_gpc_tpc_mask;
7169 gops->gr.free_channel_ctx = gk20a_free_channel_ctx;
7170 gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx;
7171 gops->gr.free_obj_ctx = gk20a_free_obj_ctx;
7172 gops->gr.bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull;
7173 gops->gr.get_zcull_info = gr_gk20a_get_zcull_info;
7172} 7174}
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 508edc79..7db6bccf 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -350,11 +350,11 @@ int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr);
350struct nvgpu_alloc_obj_ctx_args; 350struct nvgpu_alloc_obj_ctx_args;
351struct nvgpu_free_obj_ctx_args; 351struct nvgpu_free_obj_ctx_args;
352 352
353int gr_gk20a_alloc_obj_ctx(struct channel_gk20a *c, 353int gk20a_alloc_obj_ctx(struct channel_gk20a *c,
354 struct nvgpu_alloc_obj_ctx_args *args); 354 struct nvgpu_alloc_obj_ctx_args *args);
355int gr_gk20a_free_obj_ctx(struct channel_gk20a *c, 355int gk20a_free_obj_ctx(struct channel_gk20a *c,
356 struct nvgpu_free_obj_ctx_args *args); 356 struct nvgpu_free_obj_ctx_args *args);
357void gr_gk20a_free_channel_ctx(struct channel_gk20a *c); 357void gk20a_free_channel_ctx(struct channel_gk20a *c);
358 358
359int gk20a_gr_isr(struct gk20a *g); 359int gk20a_gr_isr(struct gk20a *g);
360int gk20a_gr_nonstall_isr(struct gk20a *g); 360int gk20a_gr_nonstall_isr(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ops_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_ops_gk20a.h
deleted file mode 100644
index df0cf020..00000000
--- a/drivers/gpu/nvgpu/gk20a/gr_ops_gk20a.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * GPK20A GPU graphics ops
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _GR_OPS_GK20A_H_
17#define _GR_OPS_GK20A_H_
18
19#include "gr_ops.h"
20
21#define __gr_gk20a_op(X) gr_gk20a_ ## X
22#define __set_gr_gk20a_op(X) . X = gr_gk20a_ ## X
23
24int __gr_gk20a_op(init_fs_state)(struct gk20a *);
25void __gr_gk20a_op(access_smpc_reg)(struct gk20a *, u32, u32);
26void __gr_gk20a_op(bundle_cb_defaults)(struct gk20a *);
27void __gr_gk20a_op(cb_size_default)(struct gk20a *);
28int __gr_gk20a_op(calc_global_ctx_buffer_size)(struct gk20a *);
29void __gr_gk20a_op(commit_global_attrib_cb)(struct gk20a *,
30 struct channel_ctx_gk20a *, u64 , bool);
31void __gr_gk20a_op(commit_global_bundle_cb)(struct gk20a *,
32 struct channel_ctx_gk20a *, u64, u64, bool);
33int __gr_gk20a_op(commit_global_cb_manager)(struct gk20a *,
34 struct channel_gk20a *, bool);
35void __gr_gk20a_op(commit_global_pagepool)(struct gk20a *,
36 struct channel_ctx_gk20a *, u64 , u32, bool);
37void __gr_gk20a_op(init_gpc_mmu)(struct gk20a *);
38int __gr_gk20a_op(handle_sw_method)(struct gk20a *, u32 , u32, u32, u32);
39void __gr_gk20a_op(set_alpha_circular_buffer_size)(struct gk20a *, u32);
40void __gr_gk20a_op(set_circular_buffer_size)(struct gk20a *, u32);
41void __gr_gk20a_op(enable_hww_exceptions)(struct gk20a *);
42bool __gr_gk20a_op(is_valid_class)(struct gk20a *, u32);
43void __gr_gk20a_op(get_sm_dsm_perf_regs)(struct gk20a *, u32 *, u32 **, u32 *);
44void __gr_gk20a_op(get_sm_dsm_perf_ctrl_regs)(struct gk20a *,
45 u32 *, u32 **, u32 *);
46void __gr_gk20a_op(set_hww_esr_report_mask)(struct gk20a *);
47int __gr_gk20a_op(setup_alpha_beta_tables)(struct gk20a *, struct gr_gk20a *);
48int __gr_gk20a_op(falcon_load_ucode)(struct gk20a *, u64,
49 struct gk20a_ctxsw_ucode_segments *, u32);
50int __gr_gk20a_op(load_ctxsw_ucode)(struct gk20a *);
51u32 __gr_gk20a_op(get_gpc_tpc_mask)(struct gk20a *, u32);
52void __gr_gk20a_op(free_channel_ctx)(struct channel_gk20a *);
53int __gr_gk20a_op(alloc_obj_ctx)(struct channel_gk20a *c,
54 struct nvgpu_alloc_obj_ctx_args *);
55int __gr_gk20a_op(free_obj_ctx)(struct channel_gk20a *c,
56 struct nvgpu_free_obj_ctx_args *);
57int __gr_gk20a_op(bind_ctxsw_zcull)(struct gk20a *,
58 struct gr_gk20a *, struct channel_gk20a *, u64, u32);
59int __gr_gk20a_op(get_zcull_info)(struct gk20a *,
60 struct gr_gk20a *, struct gr_zcull_info *);
61
62#endif
diff --git a/drivers/gpu/nvgpu/gk20a/hal.c b/drivers/gpu/nvgpu/gk20a/hal.c
index 84b8d819..8d1a29dd 100644
--- a/drivers/gpu/nvgpu/gk20a/hal.c
+++ b/drivers/gpu/nvgpu/gk20a/hal.c
@@ -20,13 +20,13 @@
20int gpu_init_hal(struct gk20a *g) 20int gpu_init_hal(struct gk20a *g)
21{ 21{
22 u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; 22 u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl;
23 gk20a_dbg_fn("ver=0x%x", ver);
24 switch (ver) { 23 switch (ver) {
25 case NVGPU_GPUID_GK20A: 24 case GK20A_GPUID_GK20A:
26 if (gk20a_init_hal(&g->ops)) 25 gk20a_dbg_info("gk20a detected");
27 return -ENODEV; 26 gk20a_init_hal(&g->ops);
28 break; 27 break;
29 case NVGPU_GPUID_GM20B: 28 case GK20A_GPUID_GM20B:
29 gk20a_dbg_info("gm20b detected");
30 if (gm20b_init_hal(&g->ops)) 30 if (gm20b_init_hal(&g->ops))
31 return -ENODEV; 31 return -ENODEV;
32 break; 32 break;
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_common.c b/drivers/gpu/nvgpu/gk20a/ltc_common.c
index badf640e..e0ab3f9b 100644
--- a/drivers/gpu/nvgpu/gk20a/ltc_common.c
+++ b/drivers/gpu/nvgpu/gk20a/ltc_common.c
@@ -189,9 +189,9 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
189 compbit_base_post_divide++; 189 compbit_base_post_divide++;
190 190
191 /* Bug 1477079 indicates sw adjustment on the posted divided base. */ 191 /* Bug 1477079 indicates sw adjustment on the posted divided base. */
192 if (g->ops.ltc->cbc_fix_config) 192 if (g->ops.ltc.cbc_fix_config)
193 compbit_base_post_divide = 193 compbit_base_post_divide =
194 g->ops.ltc->cbc_fix_config(g, compbit_base_post_divide); 194 g->ops.ltc.cbc_fix_config(g, compbit_base_post_divide);
195 195
196 gk20a_writel(g, ltc_ltcs_ltss_cbc_base_r(), 196 gk20a_writel(g, ltc_ltcs_ltss_cbc_base_r(),
197 compbit_base_post_divide); 197 compbit_base_post_divide);
@@ -204,7 +204,7 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
204 204
205 gr->compbit_store.base_hw = compbit_base_post_divide; 205 gr->compbit_store.base_hw = compbit_base_post_divide;
206 206
207 g->ops.ltc->cbc_ctrl(g, gk20a_cbc_op_invalidate, 207 g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate,
208 0, max_comptag_lines - 1); 208 0, max_comptag_lines - 1);
209 209
210} 210}
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
index 92dac449..aa094dc7 100644
--- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
@@ -265,24 +265,19 @@ static int gk20a_determine_L2_size_bytes(struct gk20a *g)
265 return cache_size; 265 return cache_size;
266} 266}
267 267
268static const struct gpu_ltc_ops gk20a_ltc_ops = {
269 .determine_L2_size_bytes = gk20a_determine_L2_size_bytes,
270 .set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last,
271 .init_comptags = gk20a_ltc_init_comptags,
272 .cbc_ctrl = gk20a_ltc_cbc_ctrl,
273 .set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry,
274 .set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry,
275 .init_cbc = gk20a_ltc_init_cbc,
276#ifdef CONFIG_DEBUG_FS
277 .sync_debugfs = gk20a_ltc_sync_debugfs,
278#endif
279 .elpg_flush = gk20a_mm_g_elpg_flush_locked,
280 .init_fs_state = gk20a_ltc_init_fs_state,
281 .isr = gk20a_ltc_isr
282
283};
284
285void gk20a_init_ltc(struct gpu_ops *gops) 268void gk20a_init_ltc(struct gpu_ops *gops)
286{ 269{
287 gops->ltc = &gk20a_ltc_ops; 270 gops->ltc.determine_L2_size_bytes = gk20a_determine_L2_size_bytes;
271 gops->ltc.set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last;
272 gops->ltc.init_comptags = gk20a_ltc_init_comptags;
273 gops->ltc.cbc_ctrl = gk20a_ltc_cbc_ctrl;
274 gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry;
275 gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry;
276 gops->ltc.init_cbc = gk20a_ltc_init_cbc;
277#ifdef CONFIG_DEBUG_FS
278 gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs;
279#endif
280 gops->ltc.elpg_flush = gk20a_mm_g_elpg_flush_locked;
281 gops->ltc.init_fs_state = gk20a_ltc_init_fs_state;
282 gops->ltc.isr = gk20a_ltc_isr;
288} 283}
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index bd2ef845..c121d6bf 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -1100,7 +1100,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm,
1100 COMP_TAG_LINE_SIZE_SHIFT; 1100 COMP_TAG_LINE_SIZE_SHIFT;
1101 1101
1102 /* init/clear the ctag buffer */ 1102 /* init/clear the ctag buffer */
1103 g->ops.ltc->cbc_ctrl(g, gk20a_cbc_op_clear, 1103 g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_clear,
1104 ctag_offset, ctag_offset + ctag_lines - 1); 1104 ctag_offset, ctag_offset + ctag_lines - 1);
1105 } 1105 }
1106 1106
@@ -3079,7 +3079,7 @@ int gk20a_mm_suspend(struct gk20a *g)
3079{ 3079{
3080 gk20a_dbg_fn(""); 3080 gk20a_dbg_fn("");
3081 3081
3082 g->ops.ltc->elpg_flush(g); 3082 g->ops.ltc.elpg_flush(g);
3083 3083
3084 gk20a_dbg_fn("done"); 3084 gk20a_dbg_fn("done");
3085 return 0; 3085 return 0;
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 1bf4bea0..0580f19d 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -1818,7 +1818,7 @@ int gk20a_init_pmu_reset_enable_hw(struct gk20a *g)
1818 return 0; 1818 return 0;
1819} 1819}
1820 1820
1821static int gk20a_prepare_pmu_ucode(struct gk20a *g) 1821static int gk20a_prepare_ucode(struct gk20a *g)
1822{ 1822{
1823 struct pmu_gk20a *pmu = &g->pmu; 1823 struct pmu_gk20a *pmu = &g->pmu;
1824 int i, err = 0; 1824 int i, err = 0;
@@ -2259,7 +2259,7 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g)
2259 2259
2260void gk20a_init_pmu_ops(struct gpu_ops *gops) 2260void gk20a_init_pmu_ops(struct gpu_ops *gops)
2261{ 2261{
2262 gops->pmu.prepare_ucode = gk20a_prepare_pmu_ucode; 2262 gops->pmu.prepare_ucode = gk20a_prepare_ucode;
2263 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1; 2263 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1;
2264 gops->pmu.pmu_setup_elpg = NULL; 2264 gops->pmu.pmu_setup_elpg = NULL;
2265 gops->pmu.init_wpr_region = NULL; 2265 gops->pmu.init_wpr_region = NULL;
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 7b69c5c8..8a3de4e8 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * GM20B GPU GR 2 * GM20B GPC MMU
3 * 3 *
4 * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
@@ -16,7 +16,6 @@
16#include <linux/types.h> 16#include <linux/types.h>
17#include <linux/delay.h> /* for mdelay */ 17#include <linux/delay.h> /* for mdelay */
18 18
19#include "gr_ops.h"
20#include "gk20a/gk20a.h" 19#include "gk20a/gk20a.h"
21#include "gk20a/gr_gk20a.h" 20#include "gk20a/gr_gk20a.h"
22 21
@@ -29,7 +28,7 @@
29#include "pmu_gm20b.h" 28#include "pmu_gm20b.h"
30#include "acr_gm20b.h" 29#include "acr_gm20b.h"
31 30
32void gr_gm20b_init_gpc_mmu(struct gk20a *g) 31static void gr_gm20b_init_gpc_mmu(struct gk20a *g)
33{ 32{
34 u32 temp; 33 u32 temp;
35 34
@@ -65,7 +64,7 @@ void gr_gm20b_init_gpc_mmu(struct gk20a *g)
65 gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); 64 gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));
66} 65}
67 66
68void gr_gm20b_bundle_cb_defaults(struct gk20a *g) 67static void gr_gm20b_bundle_cb_defaults(struct gk20a *g)
69{ 68{
70 struct gr_gk20a *gr = &g->gr; 69 struct gr_gk20a *gr = &g->gr;
71 70
@@ -77,7 +76,7 @@ void gr_gm20b_bundle_cb_defaults(struct gk20a *g)
77 gr_pd_ab_dist_cfg2_token_limit_init_v(); 76 gr_pd_ab_dist_cfg2_token_limit_init_v();
78} 77}
79 78
80void gr_gm20b_cb_size_default(struct gk20a *g) 79static void gr_gm20b_cb_size_default(struct gk20a *g)
81{ 80{
82 struct gr_gk20a *gr = &g->gr; 81 struct gr_gk20a *gr = &g->gr;
83 82
@@ -87,7 +86,7 @@ void gr_gm20b_cb_size_default(struct gk20a *g)
87 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); 86 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
88} 87}
89 88
90int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g) 89static int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g)
91{ 90{
92 struct gr_gk20a *gr = &g->gr; 91 struct gr_gk20a *gr = &g->gr;
93 int size; 92 int size;
@@ -108,7 +107,7 @@ int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g)
108 return size; 107 return size;
109} 108}
110 109
111void gr_gm20b_commit_global_attrib_cb(struct gk20a *g, 110static void gr_gk20a_commit_global_attrib_cb(struct gk20a *g,
112 struct channel_ctx_gk20a *ch_ctx, 111 struct channel_ctx_gk20a *ch_ctx,
113 u64 addr, bool patch) 112 u64 addr, bool patch)
114{ 113{
@@ -125,7 +124,7 @@ void gr_gm20b_commit_global_attrib_cb(struct gk20a *g,
125 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch); 124 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch);
126} 125}
127 126
128void gr_gm20b_commit_global_bundle_cb(struct gk20a *g, 127static void gr_gm20b_commit_global_bundle_cb(struct gk20a *g,
129 struct channel_ctx_gk20a *ch_ctx, 128 struct channel_ctx_gk20a *ch_ctx,
130 u64 addr, u64 size, bool patch) 129 u64 addr, u64 size, bool patch)
131{ 130{
@@ -161,7 +160,7 @@ void gr_gm20b_commit_global_bundle_cb(struct gk20a *g,
161 160
162} 161}
163 162
164int gr_gm20b_commit_global_cb_manager(struct gk20a *g, 163static int gr_gm20b_commit_global_cb_manager(struct gk20a *g,
165 struct channel_gk20a *c, bool patch) 164 struct channel_gk20a *c, bool patch)
166{ 165{
167 struct gr_gk20a *gr = &g->gr; 166 struct gr_gk20a *gr = &g->gr;
@@ -248,7 +247,7 @@ int gr_gm20b_commit_global_cb_manager(struct gk20a *g,
248 return 0; 247 return 0;
249} 248}
250 249
251void gr_gm20b_commit_global_pagepool(struct gk20a *g, 250static void gr_gm20b_commit_global_pagepool(struct gk20a *g,
252 struct channel_ctx_gk20a *ch_ctx, 251 struct channel_ctx_gk20a *ch_ctx,
253 u64 addr, u32 size, bool patch) 252 u64 addr, u32 size, bool patch)
254{ 253{
@@ -260,7 +259,7 @@ void gr_gm20b_commit_global_pagepool(struct gk20a *g,
260 259
261} 260}
262 261
263int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, 262static int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr,
264 u32 class_num, u32 offset, u32 data) 263 u32 class_num, u32 offset, u32 data)
265{ 264{
266 gk20a_dbg_fn(""); 265 gk20a_dbg_fn("");
@@ -281,10 +280,10 @@ int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr,
281 gk20a_gr_set_shader_exceptions(g, data); 280 gk20a_gr_set_shader_exceptions(g, data);
282 break; 281 break;
283 case NVB197_SET_CIRCULAR_BUFFER_SIZE: 282 case NVB197_SET_CIRCULAR_BUFFER_SIZE:
284 g->ops.gr->set_circular_buffer_size(g, data); 283 g->ops.gr.set_circular_buffer_size(g, data);
285 break; 284 break;
286 case NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE: 285 case NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
287 g->ops.gr->set_alpha_circular_buffer_size(g, data); 286 g->ops.gr.set_alpha_circular_buffer_size(g, data);
288 break; 287 break;
289 default: 288 default:
290 goto fail; 289 goto fail;
@@ -296,7 +295,7 @@ fail:
296 return -EINVAL; 295 return -EINVAL;
297} 296}
298 297
299void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) 298static void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
300{ 299{
301 struct gr_gk20a *gr = &g->gr; 300 struct gr_gk20a *gr = &g->gr;
302 u32 gpc_index, ppc_index, stride, val; 301 u32 gpc_index, ppc_index, stride, val;
@@ -396,7 +395,7 @@ void gr_gm20b_set_circular_buffer_size(struct gk20a *g, u32 data)
396 } 395 }
397} 396}
398 397
399void gr_gm20b_enable_hww_exceptions(struct gk20a *g) 398static void gr_gm20b_enable_hww_exceptions(struct gk20a *g)
400{ 399{
401 gr_gk20a_enable_hww_exceptions(g); 400 gr_gk20a_enable_hww_exceptions(g);
402 401
@@ -407,7 +406,7 @@ void gr_gm20b_enable_hww_exceptions(struct gk20a *g)
407 gr_ds_hww_report_mask_2_sph24_err_report_f()); 406 gr_ds_hww_report_mask_2_sph24_err_report_f());
408} 407}
409 408
410void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g) 409static void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g)
411{ 410{
412 /* setup sm warp esr report masks */ 411 /* setup sm warp esr report masks */
413 gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(), 412 gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(),
@@ -440,7 +439,7 @@ void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g)
440 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f()); 439 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f());
441} 440}
442 441
443bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num) 442static bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num)
444{ 443{
445 bool valid = false; 444 bool valid = false;
446 445
@@ -460,7 +459,7 @@ bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num)
460 return valid; 459 return valid;
461} 460}
462 461
463void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g, 462static void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g,
464 u32 *num_sm_dsm_perf_regs, 463 u32 *num_sm_dsm_perf_regs,
465 u32 **sm_dsm_perf_regs, 464 u32 **sm_dsm_perf_regs,
466 u32 *perf_register_stride) 465 u32 *perf_register_stride)
@@ -471,7 +470,7 @@ void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g,
471 *perf_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(); 470 *perf_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v();
472} 471}
473 472
474void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, 473static void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
475 u32 *num_sm_dsm_perf_regs, 474 u32 *num_sm_dsm_perf_regs,
476 u32 **sm_dsm_perf_regs, 475 u32 **sm_dsm_perf_regs,
477 u32 *ctrl_register_stride) 476 u32 *ctrl_register_stride)
@@ -482,7 +481,7 @@ void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
482 *ctrl_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); 481 *ctrl_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v();
483} 482}
484 483
485u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) 484static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
486{ 485{
487 u32 val; 486 u32 val;
488 struct gr_gk20a *gr = &g->gr; 487 struct gr_gk20a *gr = &g->gr;
@@ -493,7 +492,7 @@ u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
493 return (~val) & ((0x1 << gr->max_tpc_per_gpc_count) - 1); 492 return (~val) & ((0x1 << gr->max_tpc_per_gpc_count) - 1);
494} 493}
495 494
496int gr_gm20b_init_fs_state(struct gk20a *g) 495static int gr_gm20b_ctx_state_floorsweep(struct gk20a *g)
497{ 496{
498 struct gr_gk20a *gr = &g->gr; 497 struct gr_gk20a *gr = &g->gr;
499 u32 tpc_index, gpc_index; 498 u32 tpc_index, gpc_index;
@@ -596,7 +595,7 @@ int gr_gm20b_init_fs_state(struct gk20a *g)
596 return 0; 595 return 0;
597} 596}
598 597
599int gr_gm20b_falcon_load_ucode(struct gk20a *g, u64 addr_base, 598static int gr_gm20b_load_ctxsw_ucode_segments(struct gk20a *g, u64 addr_base,
600 struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset) 599 struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset)
601{ 600{
602 gk20a_writel(g, reg_offset + gr_fecs_dmactl_r(), 601 gk20a_writel(g, reg_offset + gr_fecs_dmactl_r(),
@@ -623,7 +622,7 @@ static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g)
623 622
624 gr_gk20a_load_falcon_bind_instblk(g); 623 gr_gk20a_load_falcon_bind_instblk(g);
625 624
626 g->ops.gr->falcon_load_ucode(g, addr_base, 625 g->ops.gr.falcon_load_ucode(g, addr_base,
627 &g->ctxsw_ucode_info.gpccs, 626 &g->ctxsw_ucode_info.gpccs,
628 gr_gpcs_gpccs_falcon_hwcfg_r() - 627 gr_gpcs_gpccs_falcon_hwcfg_r() -
629 gr_fecs_falcon_hwcfg_r()); 628 gr_fecs_falcon_hwcfg_r());
@@ -649,7 +648,7 @@ static int gr_gm20b_ctx_wait_lsf_ready(struct gk20a *g, u32 timeout, u32 val)
649 return -ETIMEDOUT; 648 return -ETIMEDOUT;
650} 649}
651 650
652int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) 651static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
653{ 652{
654 u32 err; 653 u32 err;
655 gk20a_dbg_fn(""); 654 gk20a_dbg_fn("");
@@ -711,30 +710,42 @@ int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
711} 710}
712#else 711#else
713 712
714int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) 713static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
715{ 714{
716 return -EPERM; 715 return -EPERM;
717} 716}
718 717
719#endif 718#endif
720 719
721#include "gk20a/gr_ops_gk20a.h"
722#include "gr_ops_gm20b.h"
723
724static struct gpu_gr_ops gm20b_gr_ops = {
725 __set_gr_gm20b_ops(),
726 __set_gr_gk20a_op(load_ctxsw_ucode)
727};
728
729static struct gpu_gr_ops gm20b_gr_privsecurity_ops = {
730 __set_gr_gm20b_ops(),
731 __set_gr_gm20b_op(load_ctxsw_ucode)
732};
733
734void gm20b_init_gr(struct gpu_ops *gops) 720void gm20b_init_gr(struct gpu_ops *gops)
735{ 721{
722 gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu;
723 gops->gr.bundle_cb_defaults = gr_gm20b_bundle_cb_defaults;
724 gops->gr.cb_size_default = gr_gm20b_cb_size_default;
725 gops->gr.calc_global_ctx_buffer_size =
726 gr_gm20b_calc_global_ctx_buffer_size;
727 gops->gr.commit_global_attrib_cb = gr_gk20a_commit_global_attrib_cb;
728 gops->gr.commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb;
729 gops->gr.commit_global_cb_manager = gr_gm20b_commit_global_cb_manager;
730 gops->gr.commit_global_pagepool = gr_gm20b_commit_global_pagepool;
731 gops->gr.handle_sw_method = gr_gm20b_handle_sw_method;
732 gops->gr.set_alpha_circular_buffer_size = gr_gm20b_set_alpha_circular_buffer_size;
733 gops->gr.set_circular_buffer_size = gr_gm20b_set_circular_buffer_size;
734 gops->gr.enable_hww_exceptions = gr_gm20b_enable_hww_exceptions;
735 gops->gr.is_valid_class = gr_gm20b_is_valid_class;
736 gops->gr.get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs;
737 gops->gr.get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs;
738 gops->gr.init_fs_state = gr_gm20b_ctx_state_floorsweep;
739 gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask;
740 gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments;
736 if (gops->privsecurity) 741 if (gops->privsecurity)
737 gops->gr = &gm20b_gr_privsecurity_ops; 742 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
738 else 743 else
739 gops->gr = &gm20b_gr_ops; 744 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
745 gops->gr.get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask;
746 gops->gr.free_channel_ctx = gk20a_free_channel_ctx;
747 gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx;
748 gops->gr.free_obj_ctx = gk20a_free_obj_ctx;
749 gops->gr.bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull;
750 gops->gr.get_zcull_info = gr_gk20a_get_zcull_info;
740} 751}
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index e822b33c..8348b9d9 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * GM20B GPU GR 2 * GM20B GPC MMU
3 * 3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
@@ -13,8 +13,8 @@
13 * more details. 13 * more details.
14 */ 14 */
15 15
16#ifndef _NVGPU_GR_GM20B_H_ 16#ifndef _NVHOST_GM20B_GR_MMU_H
17#define _NVGPU_GR_GM20B_H_ 17#define _NVHOST_GM20B_GR_MMU_H
18struct gk20a; 18struct gk20a;
19 19
20enum { 20enum {
@@ -29,7 +29,5 @@ enum {
29#define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528 29#define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528
30 30
31#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 31#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0
32
33struct gpu_ops;
34void gm20b_init_gr(struct gpu_ops *gops); 32void gm20b_init_gr(struct gpu_ops *gops);
35#endif 33#endif
diff --git a/drivers/gpu/nvgpu/gm20b/gr_ops_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_ops_gm20b.h
deleted file mode 100644
index 9477da75..00000000
--- a/drivers/gpu/nvgpu/gm20b/gr_ops_gm20b.h
+++ /dev/null
@@ -1,79 +0,0 @@
1/*
2 * GM20B GPU graphics ops
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _GR_OPS_GM20B_H_
17#define _GR_OPS_GM20B_H_
18
19#include "gr_ops.h"
20
21#define __gr_gm20b_op(X) gr_gm20b_ ## X
22#define __set_gr_gm20b_op(X) . X = gr_gm20b_ ## X
23
24void __gr_gm20b_op(init_gpc_mmu)(struct gk20a *);
25void __gr_gm20b_op(bundle_cb_defaults)(struct gk20a *);
26void __gr_gm20b_op(cb_size_default)(struct gk20a *);
27int __gr_gm20b_op(calc_global_ctx_buffer_size)(struct gk20a *);
28void __gr_gm20b_op(commit_global_bundle_cb)(struct gk20a *,
29 struct channel_ctx_gk20a *, u64, u64, bool);
30int __gr_gm20b_op(commit_global_cb_manager)(struct gk20a *,
31 struct channel_gk20a *, bool);
32void __gr_gm20b_op(commit_global_pagepool)(struct gk20a *,
33 struct channel_ctx_gk20a *, u64 , u32, bool);
34int __gr_gm20b_op(handle_sw_method)(struct gk20a *, u32 , u32, u32, u32);
35void __gr_gm20b_op(set_alpha_circular_buffer_size)(struct gk20a *, u32);
36void __gr_gm20b_op(set_circular_buffer_size)(struct gk20a *, u32);
37void __gr_gm20b_op(enable_hww_exceptions)(struct gk20a *);
38bool __gr_gm20b_op(is_valid_class)(struct gk20a *, u32);
39void __gr_gm20b_op(get_sm_dsm_perf_regs)(struct gk20a *, u32 *, u32 **, u32 *);
40void __gr_gm20b_op(get_sm_dsm_perf_ctrl_regs)(struct gk20a *,
41 u32 *, u32 **, u32 *);
42int __gr_gm20b_op(init_fs_state)(struct gk20a *);
43void __gr_gm20b_op(set_hww_esr_report_mask)(struct gk20a *);
44int __gr_gm20b_op(falcon_load_ucode)(struct gk20a *,
45 u64, struct gk20a_ctxsw_ucode_segments *, u32);
46u32 __gr_gm20b_op(get_gpc_tpc_mask)(struct gk20a *, u32);
47int __gr_gm20b_op(load_ctxsw_ucode)(struct gk20a *);
48
49#define __set_gr_gm20b_ops() \
50 /* newly defined for gm20b */ \
51 __set_gr_gm20b_op(init_gpc_mmu), \
52 __set_gr_gm20b_op(bundle_cb_defaults), \
53 __set_gr_gm20b_op(cb_size_default), \
54 __set_gr_gm20b_op(calc_global_ctx_buffer_size), \
55 __set_gr_gm20b_op(commit_global_bundle_cb), \
56 __set_gr_gm20b_op(commit_global_cb_manager), \
57 __set_gr_gm20b_op(commit_global_pagepool), \
58 __set_gr_gm20b_op(handle_sw_method), \
59 __set_gr_gm20b_op(set_alpha_circular_buffer_size), \
60 __set_gr_gm20b_op(set_circular_buffer_size), \
61 __set_gr_gm20b_op(enable_hww_exceptions), \
62 __set_gr_gm20b_op(is_valid_class), \
63 __set_gr_gm20b_op(get_sm_dsm_perf_regs), \
64 __set_gr_gm20b_op(get_sm_dsm_perf_ctrl_regs), \
65 __set_gr_gm20b_op(init_fs_state), \
66 __set_gr_gm20b_op(set_hww_esr_report_mask), \
67 __set_gr_gm20b_op(falcon_load_ucode), \
68 __set_gr_gm20b_op(get_gpc_tpc_mask), \
69 \
70 /* reused from gk20a */ \
71 __set_gr_gk20a_op(access_smpc_reg), \
72 __set_gr_gk20a_op(commit_global_attrib_cb), \
73 __set_gr_gk20a_op(free_channel_ctx), \
74 __set_gr_gk20a_op(alloc_obj_ctx), \
75 __set_gr_gk20a_op(free_obj_ctx), \
76 __set_gr_gk20a_op(bind_ctxsw_zcull), \
77 __set_gr_gk20a_op(get_zcull_info)
78
79#endif
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
index 2a888e88..a089b59c 100644
--- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
@@ -388,26 +388,24 @@ static int gm20b_determine_L2_size_bytes(struct gk20a *g)
388 return cache_size; 388 return cache_size;
389} 389}
390 390
391static struct gpu_ltc_ops gm20b_ltc_ops = {
392 .determine_L2_size_bytes = gm20b_determine_L2_size_bytes,
393 .set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last,
394 .set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry,
395 .set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry,
396 .init_cbc = gk20a_ltc_init_cbc,
397#ifdef CONFIG_DEBUG_FS
398 .sync_debugfs = gk20a_ltc_sync_debugfs,
399#endif
400 /* GM20b specific ops. */
401 .init_fs_state = gm20b_ltc_init_fs_state,
402 .init_comptags = gm20b_ltc_init_comptags,
403 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
404 .elpg_flush = gm20b_ltc_g_elpg_flush_locked,
405 .isr = gm20b_ltc_isr,
406 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
407 .flush = gm20b_flush_ltc
408};
409
410void gm20b_init_ltc(struct gpu_ops *gops) 391void gm20b_init_ltc(struct gpu_ops *gops)
411{ 392{
412 gops->ltc = &gm20b_ltc_ops; 393 /* Gk20a reused ops. */
394 gops->ltc.determine_L2_size_bytes = gm20b_determine_L2_size_bytes;
395 gops->ltc.set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last;
396 gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry;
397 gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry;
398 gops->ltc.init_cbc = gk20a_ltc_init_cbc;
399
400 /* GM20b specific ops. */
401 gops->ltc.init_fs_state = gm20b_ltc_init_fs_state;
402 gops->ltc.init_comptags = gm20b_ltc_init_comptags;
403 gops->ltc.cbc_ctrl = gm20b_ltc_cbc_ctrl;
404 gops->ltc.elpg_flush = gm20b_ltc_g_elpg_flush_locked;
405 gops->ltc.isr = gm20b_ltc_isr;
406 gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config;
407 gops->ltc.flush = gm20b_flush_ltc;
408#ifdef CONFIG_DEBUG_FS
409 gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs;
410#endif
413} 411}
diff --git a/drivers/gpu/nvgpu/gr_ops.h b/drivers/gpu/nvgpu/gr_ops.h
deleted file mode 100644
index bb2d47fa..00000000
--- a/drivers/gpu/nvgpu/gr_ops.h
+++ /dev/null
@@ -1,103 +0,0 @@
1#ifndef _NVGPU_GR_OPS_H_
2#define _NVGPU_GR_OPS_H_
3
4#include <linux/types.h>
5#include <linux/printk.h>
6
7/* TBD: rename these. s/gk20a/nvgpu/g s/gpu/nvgpu/g*/
8struct gk20a;
9struct channel_ctx_gk20a;
10struct channel_gk20a;
11struct gr_gk20a;
12struct gk20a_ctxsw_ucode_segments;
13struct nvgpu_alloc_obj_ctx_args;
14struct nvgpu_free_obj_ctx_args;
15struct gr_zcull_info;
16
17typedef int (*gr_init_fs_state_fn)(struct gk20a *g);
18typedef void (*gr_access_smpc_reg_fn)(struct gk20a *g, u32 quad, u32 offset);
19typedef void (*gr_bundle_cb_defaults_fn)(struct gk20a *g);
20typedef void (*gr_cb_size_default_fn)(struct gk20a *g);
21typedef int (*gr_calc_global_ctx_buffer_size_fn)(struct gk20a *g);
22typedef void (*gr_commit_global_attrib_cb_fn)(struct gk20a *g,
23 struct channel_ctx_gk20a *ch_ctx,
24 u64 addr, bool patch);
25typedef void (*gr_commit_global_bundle_cb_fn)(struct gk20a *g,
26 struct channel_ctx_gk20a *ch_ctx,
27 u64 addr, u64 size, bool patch);
28typedef int (*gr_commit_global_cb_manager_fn)(struct gk20a *g,
29 struct channel_gk20a *ch,
30 bool patch);
31typedef void (*gr_commit_global_pagepool_fn)(struct gk20a *g,
32 struct channel_ctx_gk20a *ch_ctx,
33 u64 addr, u32 size, bool patch);
34typedef void (*gr_init_gpc_mmu_fn)(struct gk20a *g);
35typedef int (*gr_handle_sw_method_fn)(struct gk20a *g, u32 addr,
36 u32 class_num, u32 offset, u32 data);
37typedef void (*gr_set_alpha_circular_buffer_size_fn)(struct gk20a *g,
38 u32 data);
39typedef void (*gr_set_circular_buffer_size_fn)(struct gk20a *g, u32 data);
40typedef void (*gr_enable_hww_exceptions_fn)(struct gk20a *g);
41typedef bool (*gr_is_valid_class_fn)(struct gk20a *g, u32 class_num);
42typedef void (*gr_get_sm_dsm_perf_regs_fn)(struct gk20a *g,
43 u32 *num_sm_dsm_perf_regs,
44 u32 **sm_dsm_perf_regs,
45 u32 *perf_register_stride);
46typedef void (*gr_get_sm_dsm_perf_ctrl_regs_fn)(struct gk20a *g,
47 u32 *num_sm_dsm_perf_regs,
48 u32 **sm_dsm_perf_regs,
49 u32 *perf_register_stride);
50typedef void (*gr_set_hww_esr_report_mask_fn)(struct gk20a *g);
51typedef int (*gr_setup_alpha_beta_tables_fn)(struct gk20a *g,
52 struct gr_gk20a *gr);
53typedef int (*gr_falcon_load_ucode_fn)(struct gk20a *g,
54 u64 addr_base,
55 struct gk20a_ctxsw_ucode_segments *segments,
56 u32 reg_offset);
57typedef int (*gr_load_ctxsw_ucode_fn)(struct gk20a *g);
58typedef u32 (*gr_get_gpc_tpc_mask_fn)(struct gk20a *g, u32 gpc_index);
59typedef void (*gr_free_channel_ctx_fn)(struct channel_gk20a *c);
60typedef int (*gr_alloc_obj_ctx_fn)(struct channel_gk20a *c,
61 struct nvgpu_alloc_obj_ctx_args *args);
62typedef int (*gr_free_obj_ctx_fn)(struct channel_gk20a *c,
63 struct nvgpu_free_obj_ctx_args *args);
64typedef int (*gr_bind_ctxsw_zcull_fn)(struct gk20a *g, struct gr_gk20a *gr,
65 struct channel_gk20a *c, u64 zcull_va,
66 u32 mode);
67typedef int (*gr_get_zcull_info_fn)(struct gk20a *g, struct gr_gk20a *gr,
68 struct gr_zcull_info *zcull_params);
69
70#define __op_decl(X) gr_##X##_fn X
71
72struct gpu_gr_ops {
73 __op_decl(init_fs_state);
74 __op_decl(access_smpc_reg);
75 __op_decl(bundle_cb_defaults);
76 __op_decl(cb_size_default);
77 __op_decl(calc_global_ctx_buffer_size);
78 __op_decl(commit_global_attrib_cb);
79 __op_decl(commit_global_bundle_cb);
80 __op_decl(commit_global_cb_manager);
81 __op_decl(commit_global_pagepool);
82 __op_decl(init_gpc_mmu);
83 __op_decl(handle_sw_method);
84 __op_decl(set_alpha_circular_buffer_size);
85 __op_decl(set_circular_buffer_size);
86 __op_decl(enable_hww_exceptions);
87 __op_decl(is_valid_class);
88 __op_decl(get_sm_dsm_perf_regs);
89 __op_decl(get_sm_dsm_perf_ctrl_regs);
90 __op_decl(set_hww_esr_report_mask);
91 __op_decl(setup_alpha_beta_tables);
92 __op_decl(falcon_load_ucode);
93 __op_decl(load_ctxsw_ucode);
94 __op_decl(get_gpc_tpc_mask);
95 __op_decl(free_channel_ctx);
96 __op_decl(alloc_obj_ctx);
97 __op_decl(free_obj_ctx);
98 __op_decl(bind_ctxsw_zcull);
99 __op_decl(get_zcull_info);
100};
101#undef __op_decl
102
103#endif
diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid.h b/drivers/gpu/nvgpu/nvgpu_gpuid.h
deleted file mode 100644
index 391d286e..00000000
--- a/drivers/gpu/nvgpu/nvgpu_gpuid.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * NVIDIA GPU ID functions, definitions.
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15#ifndef _NVGPU_GPUID_H_
16#define _NVGPU_GPUID_H_
17
18#define NVGPU_GPU_ARCHITECTURE_SHIFT 4
19
20/* constructs unique and compact GPUID from nvgpu_gpu_characteristics
21 * arch/impl fields */
22#define NVGPU_GPUID(arch, impl) ((u32) ((arch) | (impl)))
23
24#define NVGPU_GPUID_GK20A \
25 NVGPU_GPUID(NVGPU_GPU_ARCH_GK100, NVGPU_GPU_IMPL_GK20A)
26
27#define NVGPU_GPUID_GM20B \
28 NVGPU_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM20B)
29
30#endif /* _NVGPU_GPU_ID_H_ */
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index 3e0f9dc3..6f8baa4b 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -15,7 +15,6 @@
15 15
16#include "vgpu/vgpu.h" 16#include "vgpu/vgpu.h"
17#include "gk20a/hw_gr_gk20a.h" 17#include "gk20a/hw_gr_gk20a.h"
18#include "gr_ops.h"
19 18
20static int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va) 19static int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va)
21{ 20{
@@ -105,7 +104,7 @@ static int vgpu_gr_alloc_global_ctx_buffers(struct gk20a *g)
105 104
106 gk20a_dbg_fn(""); 105 gk20a_dbg_fn("");
107 106
108 attr_buffer_size = g->ops.gr->calc_global_ctx_buffer_size(g); 107 attr_buffer_size = g->ops.gr.calc_global_ctx_buffer_size(g);
109 108
110 gk20a_dbg_info("cb_buffer_size : %d", cb_buffer_size); 109 gk20a_dbg_info("cb_buffer_size : %d", cb_buffer_size);
111 gr->global_ctx_buffer[CIRCULAR].size = cb_buffer_size; 110 gr->global_ctx_buffer[CIRCULAR].size = cb_buffer_size;
@@ -398,7 +397,7 @@ static int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c,
398 return -EINVAL; 397 return -EINVAL;
399 } 398 }
400 399
401 if (!g->ops.gr->is_valid_class(g, args->class_num)) { 400 if (!g->ops.gr.is_valid_class(g, args->class_num)) {
402 gk20a_err(dev_from_gk20a(g), 401 gk20a_err(dev_from_gk20a(g),
403 "invalid obj class 0x%x", args->class_num); 402 "invalid obj class 0x%x", args->class_num);
404 err = -EINVAL; 403 err = -EINVAL;
@@ -525,9 +524,9 @@ static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
525 &gr->max_tpc_count)) 524 &gr->max_tpc_count))
526 return -ENOMEM; 525 return -ENOMEM;
527 526
528 g->ops.gr->bundle_cb_defaults(g); 527 g->ops.gr.bundle_cb_defaults(g);
529 g->ops.gr->cb_size_default(g); 528 g->ops.gr.cb_size_default(g);
530 g->ops.gr->calc_global_ctx_buffer_size(g); 529 g->ops.gr.calc_global_ctx_buffer_size(g);
531 return 0; 530 return 0;
532} 531}
533 532
@@ -613,7 +612,7 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g)
613 if (err) 612 if (err)
614 goto clean_up; 613 goto clean_up;
615 614
616 err = g->ops.ltc->init_comptags(g, gr); 615 err = g->ops.ltc.init_comptags(g, gr);
617 if (err) 616 if (err)
618 goto clean_up; 617 goto clean_up;
619 618
@@ -678,15 +677,11 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info)
678 return 0; 677 return 0;
679} 678}
680 679
681static struct gpu_gr_ops vgpu_gr_ops = {
682 .free_channel_ctx = vgpu_gr_free_channel_ctx,
683 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
684 .free_obj_ctx = vgpu_gr_free_obj_ctx,
685 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
686 .get_zcull_info = vgpu_gr_get_zcull_info,
687};
688
689void vgpu_init_gr_ops(struct gpu_ops *gops) 680void vgpu_init_gr_ops(struct gpu_ops *gops)
690{ 681{
691 gops->gr = &vgpu_gr_ops; 682 gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx;
683 gops->gr.alloc_obj_ctx = vgpu_gr_alloc_obj_ctx;
684 gops->gr.free_obj_ctx = vgpu_gr_free_obj_ctx;
685 gops->gr.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull;
686 gops->gr.get_zcull_info = vgpu_gr_get_zcull_info;
692} 687}
diff --git a/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c
index 0a7d19c4..ddff23b7 100644
--- a/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c
@@ -48,12 +48,8 @@ static int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
48 return 0; 48 return 0;
49} 49}
50 50
51static const struct gpu_ltc_ops vgpu_ltc_ops = {
52 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
53 .init_comptags = vgpu_ltc_init_comptags,
54};
55
56void vgpu_init_ltc_ops(struct gpu_ops *gops) 51void vgpu_init_ltc_ops(struct gpu_ops *gops)
57{ 52{
58 gops->ltc = &vgpu_ltc_ops; 53 gops->ltc.determine_L2_size_bytes = vgpu_determine_L2_size_bytes;
54 gops->ltc.init_comptags = vgpu_ltc_init_comptags;
59} 55}
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c
index 11fa73c5..84fd6d18 100644
--- a/drivers/gpu/nvgpu/vgpu/vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/vgpu.c
@@ -21,7 +21,6 @@
21#include "gk20a/debug_gk20a.h" 21#include "gk20a/debug_gk20a.h"
22#include "gk20a/hal_gk20a.h" 22#include "gk20a/hal_gk20a.h"
23#include "gk20a/hw_mc_gk20a.h" 23#include "gk20a/hw_mc_gk20a.h"
24#include "nvgpu_gpuid.h"
25 24
26static inline int vgpu_comm_init(struct platform_device *pdev) 25static inline int vgpu_comm_init(struct platform_device *pdev)
27{ 26{
@@ -240,7 +239,7 @@ static int vgpu_init_hal(struct gk20a *g)
240 u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; 239 u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl;
241 240
242 switch (ver) { 241 switch (ver) {
243 case NVGPU_GPUID_GK20A: 242 case GK20A_GPUID_GK20A:
244 gk20a_dbg_info("gk20a detected"); 243 gk20a_dbg_info("gk20a detected");
245 /* init gk20a ops then override with virt extensions */ 244 /* init gk20a ops then override with virt extensions */
246 gk20a_init_hal(&g->ops); 245 gk20a_init_hal(&g->ops);
generated by cgit v1.2.2 (git 2.25.0) at 2024-06-03 02:31:37 -0400