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-rw-r--r--drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c2
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c10
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.c8
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h19
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c5
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.h5
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c32
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c20
-rw-r--r--drivers/gpu/nvgpu/gk20a/hal_gk20a.c2
-rw-r--r--drivers/gpu/nvgpu/gk20a/mm_gk20a.c13
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.c7
-rw-r--r--drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c4
-rw-r--r--drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c451
-rw-r--r--drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.h60
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c42
15 files changed, 637 insertions, 43 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
index fb15b3da..5464b88a 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
@@ -582,6 +582,8 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s,
582 false); 582 false);
583 g->ops.clock_gating.slcg_perf_load_gating_prod(g, 583 g->ops.clock_gating.slcg_perf_load_gating_prod(g,
584 false); 584 false);
585 g->ops.clock_gating.slcg_ltc_load_gating_prod(g,
586 false);
585 gr_gk20a_init_blcg_mode(g, BLCG_RUN, ENGINE_GR_GK20A); 587 gr_gk20a_init_blcg_mode(g, BLCG_RUN, ENGINE_GR_GK20A);
586 588
587 g->elcg_enabled = false; 589 g->elcg_enabled = false;
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index e6b3fd5f..230e1722 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -385,6 +385,16 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
385 gk20a_reset(g, mc_enable_pfifo_enabled_f() 385 gk20a_reset(g, mc_enable_pfifo_enabled_f()
386 | mc_enable_ce2_enabled_f()); 386 | mc_enable_ce2_enabled_f());
387 387
388 if (g->ops.clock_gating.slcg_ce2_load_gating_prod)
389 g->ops.clock_gating.slcg_ce2_load_gating_prod(g,
390 g->slcg_enabled);
391 if (g->ops.clock_gating.slcg_fifo_load_gating_prod)
392 g->ops.clock_gating.slcg_fifo_load_gating_prod(g,
393 g->slcg_enabled);
394 if (g->ops.clock_gating.blcg_fifo_load_gating_prod)
395 g->ops.clock_gating.blcg_fifo_load_gating_prod(g,
396 g->blcg_enabled);
397
388 /* enable pbdma */ 398 /* enable pbdma */
389 mask = 0; 399 mask = 0;
390 for (i = 0; i < proj_host_num_pbdma_v(); ++i) 400 for (i = 0; i < proj_host_num_pbdma_v(); ++i)
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index a6a51de5..0caef967 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -907,6 +907,13 @@ static int gk20a_pm_finalize_poweron(struct device *dev)
907 gk20a_writel(g, mc_intr_en_0_r(), 907 gk20a_writel(g, mc_intr_en_0_r(),
908 mc_intr_en_0_inta_hardware_f()); 908 mc_intr_en_0_inta_hardware_f());
909 909
910 if (g->ops.clock_gating.slcg_bus_load_gating_prod)
911 g->ops.clock_gating.slcg_bus_load_gating_prod(g,
912 g->slcg_enabled);
913 if (g->ops.clock_gating.blcg_bus_load_gating_prod)
914 g->ops.clock_gating.blcg_bus_load_gating_prod(g,
915 g->blcg_enabled);
916
910 if (!tegra_platform_is_silicon()) 917 if (!tegra_platform_is_silicon())
911 gk20a_writel(g, bus_intr_en_0_r(), 0x0); 918 gk20a_writel(g, bus_intr_en_0_r(), 0x0);
912 else 919 else
@@ -914,6 +921,7 @@ static int gk20a_pm_finalize_poweron(struct device *dev)
914 bus_intr_en_0_pri_squash_m() | 921 bus_intr_en_0_pri_squash_m() |
915 bus_intr_en_0_pri_fecserr_m() | 922 bus_intr_en_0_pri_fecserr_m() |
916 bus_intr_en_0_pri_timeout_m()); 923 bus_intr_en_0_pri_timeout_m());
924
917 gk20a_reset_priv_ring(g); 925 gk20a_reset_priv_ring(g);
918 926
919 gk20a_detect_chip(g); 927 gk20a_detect_chip(g);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index fc97fcb9..b6d73343 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -150,11 +150,28 @@ struct gpu_ops {
150 void (*init_kind_attr)(struct gk20a *g); 150 void (*init_kind_attr)(struct gk20a *g);
151 } fb; 151 } fb;
152 struct { 152 struct {
153 void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod);
154 void (*slcg_ce2_load_gating_prod)(struct gk20a *g, bool prod);
155 void (*slcg_chiplet_load_gating_prod)(struct gk20a *g, bool prod);
156 void (*slcg_ctxsw_firmware_load_gating_prod)(struct gk20a *g, bool prod);
157 void (*slcg_fb_load_gating_prod)(struct gk20a *g, bool prod);
158 void (*slcg_fifo_load_gating_prod)(struct gk20a *g, bool prod);
153 void (*slcg_gr_load_gating_prod)(struct gk20a *g, bool prod); 159 void (*slcg_gr_load_gating_prod)(struct gk20a *g, bool prod);
160 void (*slcg_ltc_load_gating_prod)(struct gk20a *g, bool prod);
154 void (*slcg_perf_load_gating_prod)(struct gk20a *g, bool prod); 161 void (*slcg_perf_load_gating_prod)(struct gk20a *g, bool prod);
162 void (*slcg_priring_load_gating_prod)(struct gk20a *g, bool prod);
163 void (*slcg_pmu_load_gating_prod)(struct gk20a *g, bool prod);
164 void (*slcg_therm_load_gating_prod)(struct gk20a *g, bool prod);
165 void (*slcg_xbar_load_gating_prod)(struct gk20a *g, bool prod);
166 void (*blcg_bus_load_gating_prod)(struct gk20a *g, bool prod);
167 void (*blcg_ctxsw_firmware_load_gating_prod)(struct gk20a *g, bool prod);
168 void (*blcg_fb_load_gating_prod)(struct gk20a *g, bool prod);
169 void (*blcg_fifo_load_gating_prod)(struct gk20a *g, bool prod);
155 void (*blcg_gr_load_gating_prod)(struct gk20a *g, bool prod); 170 void (*blcg_gr_load_gating_prod)(struct gk20a *g, bool prod);
171 void (*blcg_ltc_load_gating_prod)(struct gk20a *g, bool prod);
172 void (*blcg_pwr_csb_load_gating_prod)(struct gk20a *g, bool prod);
173 void (*blcg_pmu_load_gating_prod)(struct gk20a *g, bool prod);
156 void (*pg_gr_load_gating_prod)(struct gk20a *g, bool prod); 174 void (*pg_gr_load_gating_prod)(struct gk20a *g, bool prod);
157 void (*slcg_therm_load_gating_prod)(struct gk20a *g, bool prod);
158 } clock_gating; 175 } clock_gating;
159 struct { 176 struct {
160 void (*bind_channel)(struct channel_gk20a *ch_gk20a); 177 void (*bind_channel)(struct channel_gk20a *ch_gk20a);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c b/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c
index c6478a5e..0e3b0cb3 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.c
@@ -311,6 +311,11 @@ void gr_gk20a_slcg_gr_load_gating_prod(struct gk20a *g,
311 } 311 }
312} 312}
313 313
314void ltc_gk20a_slcg_ltc_load_gating_prod(struct gk20a *g,
315 bool prod)
316{
317}
318
314void gr_gk20a_slcg_perf_load_gating_prod(struct gk20a *g, 319void gr_gk20a_slcg_perf_load_gating_prod(struct gk20a *g,
315 bool prod) 320 bool prod)
316{ 321{
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.h b/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.h
index 40a6c545..b2a02984 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a_gating_reglist.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * drivers/video/tegra/host/gk20a/gk20a_gating_reglist.h 2 * drivers/video/tegra/host/gk20a/gk20a_gating_reglist.h
3 * 3 *
4 * Copyright (c) 2012, NVIDIA Corporation. 4 * Copyright (c) 2012-2014, NVIDIA Corporation. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -27,6 +27,9 @@ void gr_gk20a_slcg_gr_load_gating_prod(struct gk20a *g,
27void gr_gk20a_slcg_perf_load_gating_prod(struct gk20a *g, 27void gr_gk20a_slcg_perf_load_gating_prod(struct gk20a *g,
28 bool prod); 28 bool prod);
29 29
30void ltc_gk20a_slcg_ltc_load_gating_prod(struct gk20a *g,
31 bool prod);
32
30void gr_gk20a_blcg_gr_load_gating_prod(struct gk20a *g, 33void gr_gk20a_blcg_gr_load_gating_prod(struct gk20a *g,
31 bool prod); 34 bool prod);
32 35
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
index fceed5e9..687147ed 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
@@ -94,7 +94,19 @@ static ssize_t blcg_enable_store(struct device *device,
94 g->blcg_enabled = false; 94 g->blcg_enabled = false;
95 95
96 gk20a_busy(g->dev); 96 gk20a_busy(g->dev);
97 if (g->ops.clock_gating.blcg_bus_load_gating_prod)
98 g->ops.clock_gating.blcg_bus_load_gating_prod(g, g->blcg_enabled);
99 if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod)
100 g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g, g->blcg_enabled);
101 if (g->ops.clock_gating.blcg_fb_load_gating_prod)
102 g->ops.clock_gating.blcg_fb_load_gating_prod(g, g->blcg_enabled);
103 if (g->ops.clock_gating.blcg_fifo_load_gating_prod)
104 g->ops.clock_gating.blcg_fifo_load_gating_prod(g, g->blcg_enabled);
97 g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled); 105 g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled);
106 if (g->ops.clock_gating.blcg_ltc_load_gating_prod)
107 g->ops.clock_gating.blcg_ltc_load_gating_prod(g, g->blcg_enabled);
108 if (g->ops.clock_gating.blcg_pmu_load_gating_prod)
109 g->ops.clock_gating.blcg_pmu_load_gating_prod(g, g->blcg_enabled);
98 gk20a_idle(g->dev); 110 gk20a_idle(g->dev);
99 111
100 dev_info(device, "BLCG is %s.\n", g->blcg_enabled ? "enabled" : 112 dev_info(device, "BLCG is %s.\n", g->blcg_enabled ? "enabled" :
@@ -136,8 +148,28 @@ static ssize_t slcg_enable_store(struct device *device,
136 * it is added to init, we should add it here too. 148 * it is added to init, we should add it here too.
137 */ 149 */
138 gk20a_busy(g->dev); 150 gk20a_busy(g->dev);
151 if (g->ops.clock_gating.slcg_bus_load_gating_prod)
152 g->ops.clock_gating.slcg_bus_load_gating_prod(g, g->slcg_enabled);
153 if (g->ops.clock_gating.slcg_ce2_load_gating_prod)
154 g->ops.clock_gating.slcg_ce2_load_gating_prod(g, g->slcg_enabled);
155 if (g->ops.clock_gating.slcg_chiplet_load_gating_prod)
156 g->ops.clock_gating.slcg_chiplet_load_gating_prod(g, g->slcg_enabled);
157 if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod)
158 g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g, g->slcg_enabled);
159 if (g->ops.clock_gating.slcg_fb_load_gating_prod)
160 g->ops.clock_gating.slcg_fb_load_gating_prod(g, g->slcg_enabled);
161 if (g->ops.clock_gating.slcg_fifo_load_gating_prod)
162 g->ops.clock_gating.slcg_fifo_load_gating_prod(g, g->slcg_enabled);
139 g->ops.clock_gating.slcg_gr_load_gating_prod(g, g->slcg_enabled); 163 g->ops.clock_gating.slcg_gr_load_gating_prod(g, g->slcg_enabled);
164 if (g->ops.clock_gating.slcg_ltc_load_gating_prod)
165 g->ops.clock_gating.slcg_ltc_load_gating_prod(g, g->slcg_enabled);
140 g->ops.clock_gating.slcg_perf_load_gating_prod(g, g->slcg_enabled); 166 g->ops.clock_gating.slcg_perf_load_gating_prod(g, g->slcg_enabled);
167 if (g->ops.clock_gating.slcg_priring_load_gating_prod)
168 g->ops.clock_gating.slcg_priring_load_gating_prod(g, g->slcg_enabled);
169 if (g->ops.clock_gating.slcg_pmu_load_gating_prod)
170 g->ops.clock_gating.slcg_pmu_load_gating_prod(g, g->slcg_enabled);
171 if (g->ops.clock_gating.slcg_xbar_load_gating_prod)
172 g->ops.clock_gating.slcg_xbar_load_gating_prod(g, g->slcg_enabled);
141 gk20a_idle(g->dev); 173 gk20a_idle(g->dev);
142 174
143 dev_info(device, "SLCG is %s.\n", g->slcg_enabled ? "enabled" : 175 dev_info(device, "SLCG is %s.\n", g->slcg_enabled ? "enabled" :
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index cbad1292..661a2ca3 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4246,10 +4246,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4246 if (g->ops.gr.init_gpc_mmu) 4246 if (g->ops.gr.init_gpc_mmu)
4247 g->ops.gr.init_gpc_mmu(g); 4247 g->ops.gr.init_gpc_mmu(g);
4248 4248
4249 /* slcg prod values */
4250 g->ops.clock_gating.slcg_gr_load_gating_prod(g, g->slcg_enabled);
4251 g->ops.clock_gating.slcg_perf_load_gating_prod(g, g->slcg_enabled);
4252
4253 /* init mmu debug buffer */ 4249 /* init mmu debug buffer */
4254 addr = NV_MC_SMMU_VADDR_TRANSLATE(gr->mmu_wr_mem.iova); 4250 addr = NV_MC_SMMU_VADDR_TRANSLATE(gr->mmu_wr_mem.iova);
4255 addr_lo = u64_lo32(addr); 4251 addr_lo = u64_lo32(addr);
@@ -4281,9 +4277,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4281 4277
4282 gr_gk20a_zcull_init_hw(g, gr); 4278 gr_gk20a_zcull_init_hw(g, gr);
4283 4279
4284 g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled);
4285 g->ops.clock_gating.pg_gr_load_gating_prod(g, true);
4286
4287 if (g->elcg_enabled) { 4280 if (g->elcg_enabled) {
4288 gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_GR_GK20A); 4281 gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_GR_GK20A);
4289 gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_CE2_GK20A); 4282 gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_CE2_GK20A);
@@ -4426,6 +4419,19 @@ static int gk20a_init_gr_prepare(struct gk20a *g)
4426 | mc_enable_blg_enabled_f() 4419 | mc_enable_blg_enabled_f()
4427 | mc_enable_perfmon_enabled_f()); 4420 | mc_enable_perfmon_enabled_f());
4428 4421
4422 /* slcg prod values */
4423 g->ops.clock_gating.slcg_gr_load_gating_prod(g, g->slcg_enabled);
4424 if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod)
4425 g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g,
4426 g->slcg_enabled);
4427 g->ops.clock_gating.slcg_perf_load_gating_prod(g, g->slcg_enabled);
4428
4429 g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled);
4430 if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod)
4431 g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g,
4432 g->blcg_enabled);
4433 g->ops.clock_gating.pg_gr_load_gating_prod(g, true);
4434
4429 /* enable fifo access */ 4435 /* enable fifo access */
4430 gk20a_writel(g, gr_gpfifo_ctl_r(), 4436 gk20a_writel(g, gr_gpfifo_ctl_r(),
4431 gr_gpfifo_ctl_access_enabled_f() | 4437 gr_gpfifo_ctl_access_enabled_f() |
diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
index 218491ea..578b77bf 100644
--- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c
@@ -33,6 +33,8 @@ struct gpu_ops gk20a_ops = {
33 gr_gk20a_slcg_gr_load_gating_prod, 33 gr_gk20a_slcg_gr_load_gating_prod,
34 .slcg_perf_load_gating_prod = 34 .slcg_perf_load_gating_prod =
35 gr_gk20a_slcg_perf_load_gating_prod, 35 gr_gk20a_slcg_perf_load_gating_prod,
36 .slcg_ltc_load_gating_prod =
37 ltc_gk20a_slcg_ltc_load_gating_prod,
36 .blcg_gr_load_gating_prod = 38 .blcg_gr_load_gating_prod =
37 gr_gk20a_blcg_gr_load_gating_prod, 39 gr_gk20a_blcg_gr_load_gating_prod,
38 .pg_gr_load_gating_prod = 40 .pg_gr_load_gating_prod =
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index 3feb675b..173776ff 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -251,6 +251,19 @@ static int gk20a_init_mm_reset_enable_hw(struct gk20a *g)
251 if (g->ops.fb.reset) 251 if (g->ops.fb.reset)
252 g->ops.fb.reset(g); 252 g->ops.fb.reset(g);
253 253
254 if (g->ops.clock_gating.slcg_fb_load_gating_prod)
255 g->ops.clock_gating.slcg_fb_load_gating_prod(g,
256 g->slcg_enabled);
257 if (g->ops.clock_gating.slcg_ltc_load_gating_prod)
258 g->ops.clock_gating.slcg_ltc_load_gating_prod(g,
259 g->slcg_enabled);
260 if (g->ops.clock_gating.blcg_fb_load_gating_prod)
261 g->ops.clock_gating.blcg_fb_load_gating_prod(g,
262 g->blcg_enabled);
263 if (g->ops.clock_gating.blcg_ltc_load_gating_prod)
264 g->ops.clock_gating.blcg_ltc_load_gating_prod(g,
265 g->blcg_enabled);
266
254 if (g->ops.fb.init_fs_state) 267 if (g->ops.fb.init_fs_state)
255 g->ops.fb.init_fs_state(g); 268 g->ops.fb.init_fs_state(g);
256 269
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index eb62caaf..f77ad10b 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -1124,6 +1124,13 @@ static int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable)
1124 int retries = GR_IDLE_CHECK_MAX / GR_IDLE_CHECK_DEFAULT; 1124 int retries = GR_IDLE_CHECK_MAX / GR_IDLE_CHECK_DEFAULT;
1125 gk20a_enable(g, mc_enable_pwr_enabled_f()); 1125 gk20a_enable(g, mc_enable_pwr_enabled_f());
1126 1126
1127 if (g->ops.clock_gating.slcg_pmu_load_gating_prod)
1128 g->ops.clock_gating.slcg_pmu_load_gating_prod(g,
1129 g->slcg_enabled);
1130 if (g->ops.clock_gating.blcg_pmu_load_gating_prod)
1131 g->ops.clock_gating.blcg_pmu_load_gating_prod(g,
1132 g->blcg_enabled);
1133
1127 do { 1134 do {
1128 u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) & 1135 u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) &
1129 (pwr_falcon_dmactl_dmem_scrubbing_m() | 1136 (pwr_falcon_dmactl_dmem_scrubbing_m() |
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
index aea1a80b..9d82a986 100644
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
@@ -39,6 +39,10 @@ void gk20a_reset_priv_ring(struct gk20a *g)
39 39
40 gk20a_reset(g, mc_enable_priv_ring_enabled_f()); 40 gk20a_reset(g, mc_enable_priv_ring_enabled_f());
41 41
42 if (g->ops.clock_gating.slcg_priring_load_gating_prod)
43 g->ops.clock_gating.slcg_priring_load_gating_prod(g,
44 g->slcg_enabled);
45
42 gk20a_writel(g,pri_ringmaster_command_r(), 46 gk20a_writel(g,pri_ringmaster_command_r(),
43 0x4); 47 0x4);
44 48
diff --git a/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c b/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c
index 6b8648d3..fc4a94b9 100644
--- a/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c
+++ b/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c
@@ -1,6 +1,4 @@
1/* 1/*
2 * drivers/video/tegra/host/gm20b/gm20b_gating_reglist.c
3 *
4 * Copyright (c) 2014, NVIDIA Corporation. All rights reserved. 2 * Copyright (c) 2014, NVIDIA Corporation. All rights reserved.
5 * 3 *
6 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
@@ -31,6 +29,40 @@ struct gating_desc {
31 u32 prod; 29 u32 prod;
32 u32 disable; 30 u32 disable;
33}; 31};
32/* slcg bus */
33const struct gating_desc gm20b_slcg_bus[] = {
34 {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe},
35};
36
37/* slcg ce2 */
38const struct gating_desc gm20b_slcg_ce2[] = {
39 {.addr = 0x00106f28, .prod = 0x00000000, .disable = 0x000007fe},
40};
41
42/* slcg chiplet */
43const struct gating_desc gm20b_slcg_chiplet[] = {
44 {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007},
45 {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007},
46 {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007},
47 {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
48};
49
50/* slcg ctxsw firmware */
51const struct gating_desc gm20b_slcg_ctxsw_firmware[] = {
52 {.addr = 0x00005f00, .prod = 0x00020008, .disable = 0x0003fffe},
53};
54
55/* slcg fb */
56const struct gating_desc gm20b_slcg_fb[] = {
57 {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe},
58 {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe},
59};
60
61/* slcg fifo */
62const struct gating_desc gm20b_slcg_fifo[] = {
63 {.addr = 0x000026ac, .prod = 0x00000100, .disable = 0x0001fffe},
64};
65
34/* slcg gr */ 66/* slcg gr */
35const struct gating_desc gm20b_slcg_gr[] = { 67const struct gating_desc gm20b_slcg_gr[] = {
36 {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x03fffffe}, 68 {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x03fffffe},
@@ -74,8 +106,8 @@ const struct gating_desc gm20b_slcg_gr[] = {
74 {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, 106 {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe},
75 {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, 107 {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e},
76 {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, 108 {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe},
77 {.addr = 0x00419fdc, .prod = 0xfffffffe, .disable = 0xfffffffe}, 109 {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe},
78 {.addr = 0x00419fe4, .prod = 0x00000000, .disable = 0x00001ffe}, 110 {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe},
79 {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, 111 {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe},
80 {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, 112 {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe},
81 {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, 113 {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
@@ -93,6 +125,12 @@ const struct gating_desc gm20b_slcg_gr[] = {
93 {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000001ff}, 125 {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000001ff},
94}; 126};
95 127
128/* slcg ltc */
129const struct gating_desc gm20b_slcg_ltc[] = {
130 {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe},
131 {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe},
132};
133
96/* slcg perf */ 134/* slcg perf */
97const struct gating_desc gm20b_slcg_perf[] = { 135const struct gating_desc gm20b_slcg_perf[] = {
98 {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, 136 {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000},
@@ -101,6 +139,62 @@ const struct gating_desc gm20b_slcg_perf[] = {
101 {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, 139 {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000},
102}; 140};
103 141
142/* slcg PriRing */
143const struct gating_desc gm20b_slcg_priring[] = {
144 {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001},
145};
146
147/* slcg pwr_csb */
148const struct gating_desc gm20b_slcg_pwr_csb[] = {
149 {.addr = 0x0000017c, .prod = 0x00020008, .disable = 0x0003fffe},
150 {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f},
151 {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe},
152 {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f},
153};
154
155/* slcg pmu */
156const struct gating_desc gm20b_slcg_pmu[] = {
157 {.addr = 0x0010a17c, .prod = 0x00020008, .disable = 0x0003fffe},
158 {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe},
159 {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f},
160};
161
162/* therm gr */
163const struct gating_desc gm20b_slcg_therm[] = {
164 {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f},
165};
166
167/* slcg Xbar */
168const struct gating_desc gm20b_slcg_xbar[] = {
169 {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
170 {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
171};
172
173/* blcg bus */
174const struct gating_desc gm20b_blcg_bus[] = {
175 {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000},
176};
177
178/* blcg ctxsw firmware */
179const struct gating_desc gm20b_blcg_ctxsw_firmware[] = {
180 {.addr = 0x00022400, .prod = 0x00000000, .disable = 0x00000000},
181};
182
183/* blcg fb */
184const struct gating_desc gm20b_blcg_fb[] = {
185 {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000},
186 {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000},
187 {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000},
188 {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000},
189 {.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000},
190 {.addr = 0x00100c98, .prod = 0x00000242, .disable = 0x00000000},
191};
192
193/* blcg fifo */
194const struct gating_desc gm20b_blcg_fifo[] = {
195 {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000},
196};
197
104/* blcg gr */ 198/* blcg gr */
105const struct gating_desc gm20b_blcg_gr[] = { 199const struct gating_desc gm20b_blcg_gr[] = {
106 {.addr = 0x004041f0, .prod = 0x00004046, .disable = 0x00000000}, 200 {.addr = 0x004041f0, .prod = 0x00004046, .disable = 0x00000000},
@@ -143,11 +237,11 @@ const struct gating_desc gm20b_blcg_gr[] = {
143 {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, 237 {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000},
144 {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, 238 {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000},
145 {.addr = 0x00419c70, .prod = 0x00004044, .disable = 0x00000000}, 239 {.addr = 0x00419c70, .prod = 0x00004044, .disable = 0x00000000},
146 {.addr = 0x00419fd0, .prod = 0x00000044, .disable = 0x00000000}, 240 {.addr = 0x00419fd0, .prod = 0x00004044, .disable = 0x00000000},
147 {.addr = 0x00419fd8, .prod = 0x00000045, .disable = 0x00000000}, 241 {.addr = 0x00419fd8, .prod = 0x00004046, .disable = 0x00000000},
148 {.addr = 0x00419fe0, .prod = 0x00000044, .disable = 0x00000000}, 242 {.addr = 0x00419fe0, .prod = 0x00004044, .disable = 0x00000000},
149 {.addr = 0x00419fe8, .prod = 0x00000042, .disable = 0x00000000}, 243 {.addr = 0x00419fe8, .prod = 0x00000042, .disable = 0x00000000},
150 {.addr = 0x00419ff0, .prod = 0x00000045, .disable = 0x00000000}, 244 {.addr = 0x00419ff0, .prod = 0x00004045, .disable = 0x00000000},
151 {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, 245 {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000},
152 {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, 246 {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000},
153 {.addr = 0x0041be28, .prod = 0x00000042, .disable = 0x00000000}, 247 {.addr = 0x0041be28, .prod = 0x00000042, .disable = 0x00000000},
@@ -166,16 +260,126 @@ const struct gating_desc gm20b_blcg_gr[] = {
166 {.addr = 0x004089b8, .prod = 0x00004042, .disable = 0x00000000}, 260 {.addr = 0x004089b8, .prod = 0x00004042, .disable = 0x00000000},
167}; 261};
168 262
263/* blcg ltc */
264const struct gating_desc gm20b_blcg_ltc[] = {
265 {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000},
266 {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000},
267 {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000},
268 {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000},
269};
270
271/* blcg pwr_csb */
272const struct gating_desc gm20b_blcg_pwr_csb[] = {
273 {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000},
274};
275
276/* blcg pmu */
277const struct gating_desc gm20b_blcg_pmu[] = {
278 {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000},
279};
280
281/* blcg Xbar */
282const struct gating_desc gm20b_blcg_xbar[] = {
283 {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
284 {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
285};
286
169/* pg gr */ 287/* pg gr */
170const struct gating_desc gm20b_pg_gr[] = { 288const struct gating_desc gm20b_pg_gr[] = {
171}; 289};
172 290
173/* therm gr */ 291/* static inline functions */
174const struct gating_desc gm20b_slcg_therm[] = { 292void gm20b_slcg_bus_load_gating_prod(struct gk20a *g,
175 {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, 293 bool prod)
176}; 294{
295 u32 i;
296 u32 size = sizeof(gm20b_slcg_bus) / sizeof(struct gating_desc);
297 for (i = 0; i < size; i++) {
298 if (prod)
299 gk20a_writel(g, gm20b_slcg_bus[i].addr,
300 gm20b_slcg_bus[i].prod);
301 else
302 gk20a_writel(g, gm20b_slcg_bus[i].addr,
303 gm20b_slcg_bus[i].disable);
304 }
305}
177 306
178/* static inline functions */ 307/* static inline functions */
308void gm20b_slcg_ce2_load_gating_prod(struct gk20a *g,
309 bool prod)
310{
311 u32 i;
312 u32 size = sizeof(gm20b_slcg_ce2) / sizeof(struct gating_desc);
313 for (i = 0; i < size; i++) {
314 if (prod)
315 gk20a_writel(g, gm20b_slcg_ce2[i].addr,
316 gm20b_slcg_ce2[i].prod);
317 else
318 gk20a_writel(g, gm20b_slcg_ce2[i].addr,
319 gm20b_slcg_ce2[i].disable);
320 }
321}
322
323void gm20b_slcg_chiplet_load_gating_prod(struct gk20a *g,
324 bool prod)
325{
326 u32 i;
327 u32 size = sizeof(gm20b_slcg_chiplet) / sizeof(struct gating_desc);
328 for (i = 0; i < size; i++) {
329 if (prod)
330 gk20a_writel(g, gm20b_slcg_chiplet[i].addr,
331 gm20b_slcg_chiplet[i].prod);
332 else
333 gk20a_writel(g, gm20b_slcg_chiplet[i].addr,
334 gm20b_slcg_chiplet[i].disable);
335 }
336}
337
338void gm20b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
339 bool prod)
340{
341 u32 i;
342 u32 size = sizeof(gm20b_slcg_ctxsw_firmware) / sizeof(struct gating_desc);
343 for (i = 0; i < size; i++) {
344 if (prod)
345 gk20a_writel(g, gm20b_slcg_ctxsw_firmware[i].addr,
346 gm20b_slcg_ctxsw_firmware[i].prod);
347 else
348 gk20a_writel(g, gm20b_slcg_ctxsw_firmware[i].addr,
349 gm20b_slcg_ctxsw_firmware[i].disable);
350 }
351}
352
353void gm20b_slcg_fb_load_gating_prod(struct gk20a *g,
354 bool prod)
355{
356 u32 i;
357 u32 size = sizeof(gm20b_slcg_fb) / sizeof(struct gating_desc);
358 for (i = 0; i < size; i++) {
359 if (prod)
360 gk20a_writel(g, gm20b_slcg_fb[i].addr,
361 gm20b_slcg_fb[i].prod);
362 else
363 gk20a_writel(g, gm20b_slcg_fb[i].addr,
364 gm20b_slcg_fb[i].disable);
365 }
366}
367
368void gm20b_slcg_fifo_load_gating_prod(struct gk20a *g,
369 bool prod)
370{
371 u32 i;
372 u32 size = sizeof(gm20b_slcg_fifo) / sizeof(struct gating_desc);
373 for (i = 0; i < size; i++) {
374 if (prod)
375 gk20a_writel(g, gm20b_slcg_fifo[i].addr,
376 gm20b_slcg_fifo[i].prod);
377 else
378 gk20a_writel(g, gm20b_slcg_fifo[i].addr,
379 gm20b_slcg_fifo[i].disable);
380 }
381}
382
179void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g, 383void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g,
180 bool prod) 384 bool prod)
181{ 385{
@@ -191,7 +395,22 @@ void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g,
191 } 395 }
192} 396}
193 397
194void gr_gm20b_slcg_perf_load_gating_prod(struct gk20a *g, 398void ltc_gm20b_slcg_ltc_load_gating_prod(struct gk20a *g,
399 bool prod)
400{
401 u32 i;
402 u32 size = sizeof(gm20b_slcg_ltc) / sizeof(struct gating_desc);
403 for (i = 0; i < size; i++) {
404 if (prod)
405 gk20a_writel(g, gm20b_slcg_ltc[i].addr,
406 gm20b_slcg_ltc[i].prod);
407 else
408 gk20a_writel(g, gm20b_slcg_ltc[i].addr,
409 gm20b_slcg_ltc[i].disable);
410 }
411}
412
413void gm20b_slcg_perf_load_gating_prod(struct gk20a *g,
195 bool prod) 414 bool prod)
196{ 415{
197 u32 i; 416 u32 i;
@@ -206,37 +425,52 @@ void gr_gm20b_slcg_perf_load_gating_prod(struct gk20a *g,
206 } 425 }
207} 426}
208 427
209void gr_gm20b_blcg_gr_load_gating_prod(struct gk20a *g, 428void gm20b_slcg_priring_load_gating_prod(struct gk20a *g,
210 bool prod) 429 bool prod)
211{ 430{
212 u32 i; 431 u32 i;
213 u32 size = sizeof(gm20b_blcg_gr) / sizeof(struct gating_desc); 432 u32 size = sizeof(gm20b_slcg_priring) / sizeof(struct gating_desc);
214 for (i = 0; i < size; i++) { 433 for (i = 0; i < size; i++) {
215 if (prod) 434 if (prod)
216 gk20a_writel(g, gm20b_blcg_gr[i].addr, 435 gk20a_writel(g, gm20b_slcg_priring[i].addr,
217 gm20b_blcg_gr[i].prod); 436 gm20b_slcg_priring[i].prod);
218 else 437 else
219 gk20a_writel(g, gm20b_blcg_gr[i].addr, 438 gk20a_writel(g, gm20b_slcg_priring[i].addr,
220 gm20b_blcg_gr[i].disable); 439 gm20b_slcg_priring[i].disable);
221 } 440 }
222} 441}
223 442
224void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g, 443void gm20b_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
225 bool prod) 444 bool prod)
226{ 445{
227 u32 i; 446 u32 i;
228 u32 size = sizeof(gm20b_pg_gr) / sizeof(struct gating_desc); 447 u32 size = sizeof(gm20b_slcg_pwr_csb) / sizeof(struct gating_desc);
229 for (i = 0; i < size; i++) { 448 for (i = 0; i < size; i++) {
230 if (prod) 449 if (prod)
231 gk20a_writel(g, gm20b_pg_gr[i].addr, 450 gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr,
232 gm20b_pg_gr[i].prod); 451 gm20b_slcg_pwr_csb[i].prod);
233 else 452 else
234 gk20a_writel(g, gm20b_pg_gr[i].addr, 453 gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr,
235 gm20b_pg_gr[i].disable); 454 gm20b_slcg_pwr_csb[i].disable);
236 } 455 }
237} 456}
238 457
239void gr_gm20b_slcg_therm_load_gating_prod(struct gk20a *g, 458void gm20b_slcg_pmu_load_gating_prod(struct gk20a *g,
459 bool prod)
460{
461 u32 i;
462 u32 size = sizeof(gm20b_slcg_pmu) / sizeof(struct gating_desc);
463 for (i = 0; i < size; i++) {
464 if (prod)
465 gk20a_writel(g, gm20b_slcg_pmu[i].addr,
466 gm20b_slcg_pmu[i].prod);
467 else
468 gk20a_writel(g, gm20b_slcg_pmu[i].addr,
469 gm20b_slcg_pmu[i].disable);
470 }
471}
472
473void gm20b_slcg_therm_load_gating_prod(struct gk20a *g,
240 bool prod) 474 bool prod)
241{ 475{
242 u32 i; 476 u32 i;
@@ -251,4 +485,169 @@ void gr_gm20b_slcg_therm_load_gating_prod(struct gk20a *g,
251 } 485 }
252} 486}
253 487
488void gm20b_slcg_xbar_load_gating_prod(struct gk20a *g,
489 bool prod)
490{
491 u32 i;
492 u32 size = sizeof(gm20b_slcg_xbar) / sizeof(struct gating_desc);
493 for (i = 0; i < size; i++) {
494 if (prod)
495 gk20a_writel(g, gm20b_slcg_xbar[i].addr,
496 gm20b_slcg_xbar[i].prod);
497 else
498 gk20a_writel(g, gm20b_slcg_xbar[i].addr,
499 gm20b_slcg_xbar[i].disable);
500 }
501}
502
503void gm20b_blcg_bus_load_gating_prod(struct gk20a *g,
504 bool prod)
505{
506 u32 i;
507 u32 size = sizeof(gm20b_blcg_bus) / sizeof(struct gating_desc);
508 for (i = 0; i < size; i++) {
509 if (prod)
510 gk20a_writel(g, gm20b_blcg_bus[i].addr,
511 gm20b_blcg_bus[i].prod);
512 else
513 gk20a_writel(g, gm20b_blcg_bus[i].addr,
514 gm20b_blcg_bus[i].disable);
515 }
516}
517
518void gm20b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
519 bool prod)
520{
521 u32 i;
522 u32 size = sizeof(gm20b_blcg_ctxsw_firmware) / sizeof(struct gating_desc);
523 for (i = 0; i < size; i++) {
524 if (prod)
525 gk20a_writel(g, gm20b_blcg_ctxsw_firmware[i].addr,
526 gm20b_blcg_ctxsw_firmware[i].prod);
527 else
528 gk20a_writel(g, gm20b_blcg_ctxsw_firmware[i].addr,
529 gm20b_blcg_ctxsw_firmware[i].disable);
530 }
531}
532
533void gm20b_blcg_fb_load_gating_prod(struct gk20a *g,
534 bool prod)
535{
536 u32 i;
537 u32 size = sizeof(gm20b_blcg_fb) / sizeof(struct gating_desc);
538 for (i = 0; i < size; i++) {
539 if (prod)
540 gk20a_writel(g, gm20b_blcg_fb[i].addr,
541 gm20b_blcg_fb[i].prod);
542 else
543 gk20a_writel(g, gm20b_blcg_fb[i].addr,
544 gm20b_blcg_fb[i].disable);
545 }
546}
547
548void gm20b_blcg_fifo_load_gating_prod(struct gk20a *g,
549 bool prod)
550{
551 u32 i;
552 u32 size = sizeof(gm20b_blcg_fifo) / sizeof(struct gating_desc);
553 for (i = 0; i < size; i++) {
554 if (prod)
555 gk20a_writel(g, gm20b_blcg_fifo[i].addr,
556 gm20b_blcg_fifo[i].prod);
557 else
558 gk20a_writel(g, gm20b_blcg_fifo[i].addr,
559 gm20b_blcg_fifo[i].disable);
560 }
561}
562
563void gm20b_blcg_gr_load_gating_prod(struct gk20a *g,
564 bool prod)
565{
566 u32 i;
567 u32 size = sizeof(gm20b_blcg_gr) / sizeof(struct gating_desc);
568 for (i = 0; i < size; i++) {
569 if (prod)
570 gk20a_writel(g, gm20b_blcg_gr[i].addr,
571 gm20b_blcg_gr[i].prod);
572 else
573 gk20a_writel(g, gm20b_blcg_gr[i].addr,
574 gm20b_blcg_gr[i].disable);
575 }
576}
577
578void gm20b_blcg_ltc_load_gating_prod(struct gk20a *g,
579 bool prod)
580{
581 u32 i;
582 u32 size = sizeof(gm20b_blcg_ltc) / sizeof(struct gating_desc);
583 for (i = 0; i < size; i++) {
584 if (prod)
585 gk20a_writel(g, gm20b_blcg_ltc[i].addr,
586 gm20b_blcg_ltc[i].prod);
587 else
588 gk20a_writel(g, gm20b_blcg_ltc[i].addr,
589 gm20b_blcg_ltc[i].disable);
590 }
591}
592
593void gm20b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
594 bool prod)
595{
596 u32 i;
597 u32 size = sizeof(gm20b_blcg_pwr_csb) / sizeof(struct gating_desc);
598 for (i = 0; i < size; i++) {
599 if (prod)
600 gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr,
601 gm20b_blcg_pwr_csb[i].prod);
602 else
603 gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr,
604 gm20b_blcg_pwr_csb[i].disable);
605 }
606}
607
608void gm20b_blcg_pmu_load_gating_prod(struct gk20a *g,
609 bool prod)
610{
611 u32 i;
612 u32 size = sizeof(gm20b_blcg_pmu) / sizeof(struct gating_desc);
613 for (i = 0; i < size; i++) {
614 if (prod)
615 gk20a_writel(g, gm20b_blcg_pmu[i].addr,
616 gm20b_blcg_pmu[i].prod);
617 else
618 gk20a_writel(g, gm20b_blcg_pmu[i].addr,
619 gm20b_blcg_pmu[i].disable);
620 }
621}
622
623void gm20b_blcg_xbar_load_gating_prod(struct gk20a *g,
624 bool prod)
625{
626 u32 i;
627 u32 size = sizeof(gm20b_blcg_xbar) / sizeof(struct gating_desc);
628 for (i = 0; i < size; i++) {
629 if (prod)
630 gk20a_writel(g, gm20b_blcg_xbar[i].addr,
631 gm20b_blcg_xbar[i].prod);
632 else
633 gk20a_writel(g, gm20b_blcg_xbar[i].addr,
634 gm20b_blcg_xbar[i].disable);
635 }
636}
637
638void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g,
639 bool prod)
640{
641 u32 i;
642 u32 size = sizeof(gm20b_pg_gr) / sizeof(struct gating_desc);
643 for (i = 0; i < size; i++) {
644 if (prod)
645 gk20a_writel(g, gm20b_pg_gr[i].addr,
646 gm20b_pg_gr[i].prod);
647 else
648 gk20a_writel(g, gm20b_pg_gr[i].addr,
649 gm20b_pg_gr[i].disable);
650 }
651}
652
254#endif /* __gm20b_gating_reglist_h__ */ 653#endif /* __gm20b_gating_reglist_h__ */
diff --git a/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.h b/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.h
index 4097fad2..6f51e50d 100644
--- a/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.h
+++ b/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.h
@@ -21,17 +21,69 @@
21 21
22#include "gk20a/gk20a.h" 22#include "gk20a/gk20a.h"
23 23
24void gm20b_slcg_bus_load_gating_prod(struct gk20a *g,
25 bool prod);
26
27void gm20b_slcg_ce2_load_gating_prod(struct gk20a *g,
28 bool prod);
29
30void gm20b_slcg_chiplet_load_gating_prod(struct gk20a *g,
31 bool prod);
32
33void gm20b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
34 bool prod);
35
36void gm20b_slcg_fb_load_gating_prod(struct gk20a *g,
37 bool prod);
38
39void gm20b_slcg_fifo_load_gating_prod(struct gk20a *g,
40 bool prod);
41
24void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g, 42void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g,
25 bool prod); 43 bool prod);
26 44
27void gr_gm20b_slcg_perf_load_gating_prod(struct gk20a *g, 45void ltc_gm20b_slcg_ltc_load_gating_prod(struct gk20a *g,
28 bool prod); 46 bool prod);
29 47
30void gr_gm20b_blcg_gr_load_gating_prod(struct gk20a *g, 48void gm20b_slcg_perf_load_gating_prod(struct gk20a *g,
31 bool prod); 49 bool prod);
32 50
33void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g, 51void gm20b_slcg_priring_load_gating_prod(struct gk20a *g,
52 bool prod);
53
54void gm20b_slcg_pmu_load_gating_prod(struct gk20a *g,
55 bool prod);
56
57void gm20b_slcg_therm_load_gating_prod(struct gk20a *g,
58 bool prod);
59
60void gm20b_slcg_xbar_load_gating_prod(struct gk20a *g,
34 bool prod); 61 bool prod);
35 62
36void gr_gm20b_slcg_therm_load_gating_prod(struct gk20a *g, 63void gm20b_blcg_bus_load_gating_prod(struct gk20a *g,
37 bool prod); 64 bool prod);
65
66void gm20b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
67 bool prod);
68
69void gm20b_blcg_fb_load_gating_prod(struct gk20a *g,
70 bool prod);
71
72void gm20b_blcg_fifo_load_gating_prod(struct gk20a *g,
73 bool prod);
74
75void gm20b_blcg_gr_load_gating_prod(struct gk20a *g,
76 bool prod);
77
78void gm20b_blcg_ltc_load_gating_prod(struct gk20a *g,
79 bool prod);
80
81void gm20b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
82 bool prod);
83
84void gm20b_blcg_pmu_load_gating_prod(struct gk20a *g,
85 bool prod);
86
87void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g,
88 bool prod);
89
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 6ded6925..ec786a44 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -35,16 +35,50 @@
35 35
36struct gpu_ops gm20b_ops = { 36struct gpu_ops gm20b_ops = {
37 .clock_gating = { 37 .clock_gating = {
38 .slcg_bus_load_gating_prod =
39 gm20b_slcg_bus_load_gating_prod,
40 .slcg_ce2_load_gating_prod =
41 gm20b_slcg_ce2_load_gating_prod,
42 .slcg_chiplet_load_gating_prod =
43 gm20b_slcg_chiplet_load_gating_prod,
44 .slcg_ctxsw_firmware_load_gating_prod =
45 gm20b_slcg_ctxsw_firmware_load_gating_prod,
46 .slcg_fb_load_gating_prod =
47 gm20b_slcg_fb_load_gating_prod,
48 .slcg_fifo_load_gating_prod =
49 gm20b_slcg_fifo_load_gating_prod,
38 .slcg_gr_load_gating_prod = 50 .slcg_gr_load_gating_prod =
39 gr_gm20b_slcg_gr_load_gating_prod, 51 gr_gm20b_slcg_gr_load_gating_prod,
52 .slcg_ltc_load_gating_prod =
53 ltc_gm20b_slcg_ltc_load_gating_prod,
40 .slcg_perf_load_gating_prod = 54 .slcg_perf_load_gating_prod =
41 gr_gm20b_slcg_perf_load_gating_prod, 55 gm20b_slcg_perf_load_gating_prod,
56 .slcg_priring_load_gating_prod =
57 gm20b_slcg_priring_load_gating_prod,
58 .slcg_pmu_load_gating_prod =
59 gm20b_slcg_pmu_load_gating_prod,
60 .slcg_therm_load_gating_prod =
61 gm20b_slcg_therm_load_gating_prod,
62 .slcg_xbar_load_gating_prod =
63 gm20b_slcg_xbar_load_gating_prod,
64 .blcg_bus_load_gating_prod =
65 gm20b_blcg_bus_load_gating_prod,
66 .blcg_ctxsw_firmware_load_gating_prod =
67 gm20b_blcg_ctxsw_firmware_load_gating_prod,
68 .blcg_fb_load_gating_prod =
69 gm20b_blcg_fb_load_gating_prod,
70 .blcg_fifo_load_gating_prod =
71 gm20b_blcg_fifo_load_gating_prod,
42 .blcg_gr_load_gating_prod = 72 .blcg_gr_load_gating_prod =
43 gr_gm20b_blcg_gr_load_gating_prod, 73 gm20b_blcg_gr_load_gating_prod,
74 .blcg_ltc_load_gating_prod =
75 gm20b_blcg_ltc_load_gating_prod,
76 .blcg_pwr_csb_load_gating_prod =
77 gm20b_blcg_pwr_csb_load_gating_prod,
78 .blcg_pmu_load_gating_prod =
79 gm20b_blcg_pmu_load_gating_prod,
44 .pg_gr_load_gating_prod = 80 .pg_gr_load_gating_prod =
45 gr_gm20b_pg_gr_load_gating_prod, 81 gr_gm20b_pg_gr_load_gating_prod,
46 .slcg_therm_load_gating_prod =
47 gr_gm20b_slcg_therm_load_gating_prod,
48 } 82 }
49}; 83};
50 84
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 14:34:07 -0400