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-rw-r--r--drivers/gpu/nvgpu/Makefile.nvgpu3
-rw-r--r--drivers/gpu/nvgpu/common/linux/debug.c3
-rw-r--r--drivers/gpu/nvgpu/common/linux/debug_xve.c176
-rw-r--r--drivers/gpu/nvgpu/common/linux/debug_xve.h21
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.c1
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h2
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c2
-rw-r--r--drivers/gpu/nvgpu/gp106/xve_gp106.c170
-rw-r--r--drivers/gpu/nvgpu/gp106/xve_gp106.h51
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/xve.h58
10 files changed, 269 insertions, 218 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu
index 87199316..e60dc0b6 100644
--- a/drivers/gpu/nvgpu/Makefile.nvgpu
+++ b/drivers/gpu/nvgpu/Makefile.nvgpu
@@ -132,7 +132,8 @@ nvgpu-$(CONFIG_DEBUG_FS) += \
132 common/linux/debug_allocator.o \ 132 common/linux/debug_allocator.o \
133 common/linux/debug_hal.o \ 133 common/linux/debug_hal.o \
134 common/linux/debug_kmem.o \ 134 common/linux/debug_kmem.o \
135 common/linux/debug_clk.o 135 common/linux/debug_clk.o \
136 common/linux/debug_xve.o
136 137
137nvgpu-$(CONFIG_TEGRA_GK20A) += common/linux/platform_gk20a_tegra.o 138nvgpu-$(CONFIG_TEGRA_GK20A) += common/linux/platform_gk20a_tegra.o
138nvgpu-$(CONFIG_SYNC) += gk20a/sync_gk20a.o 139nvgpu-$(CONFIG_SYNC) += gk20a/sync_gk20a.o
diff --git a/drivers/gpu/nvgpu/common/linux/debug.c b/drivers/gpu/nvgpu/common/linux/debug.c
index abc8b907..5750800f 100644
--- a/drivers/gpu/nvgpu/common/linux/debug.c
+++ b/drivers/gpu/nvgpu/common/linux/debug.c
@@ -22,6 +22,7 @@
22#include "debug_pmu.h" 22#include "debug_pmu.h"
23#include "debug_sched.h" 23#include "debug_sched.h"
24#include "debug_hal.h" 24#include "debug_hal.h"
25#include "debug_xve.h"
25#include "os_linux.h" 26#include "os_linux.h"
26 27
27#include "gk20a/gk20a.h" 28#include "gk20a/gk20a.h"
@@ -394,6 +395,8 @@ void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink)
394#ifdef CONFIG_NVGPU_TRACK_MEM_USAGE 395#ifdef CONFIG_NVGPU_TRACK_MEM_USAGE
395 nvgpu_kmem_debugfs_init(g); 396 nvgpu_kmem_debugfs_init(g);
396#endif 397#endif
398 if (g->pci_vendor_id)
399 nvgpu_xve_debugfs_init(g);
397} 400}
398 401
399void gk20a_debug_deinit(struct gk20a *g) 402void gk20a_debug_deinit(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/common/linux/debug_xve.c b/drivers/gpu/nvgpu/common/linux/debug_xve.c
new file mode 100644
index 00000000..743702a2
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/linux/debug_xve.c
@@ -0,0 +1,176 @@
1/*
2 * Copyright (C) 2017 NVIDIA Corporation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <nvgpu/types.h>
16#include <nvgpu/xve.h>
17
18#include "debug_xve.h"
19#include "os_linux.h"
20
21#include <linux/debugfs.h>
22#include <linux/uaccess.h>
23
24static ssize_t xve_link_speed_write(struct file *filp,
25 const char __user *buff,
26 size_t len, loff_t *off)
27{
28 struct gk20a *g = ((struct seq_file *)filp->private_data)->private;
29 char kbuff[16];
30 u32 buff_size, check_len;
31 u32 link_speed = 0;
32 int ret;
33
34 buff_size = min_t(size_t, 16, len);
35
36 memset(kbuff, 0, 16);
37 if (copy_from_user(kbuff, buff, buff_size))
38 return -EFAULT;
39
40 check_len = strlen("Gen1");
41 if (strncmp(kbuff, "Gen1", check_len) == 0)
42 link_speed = GPU_XVE_SPEED_2P5;
43 else if (strncmp(kbuff, "Gen2", check_len) == 0)
44 link_speed = GPU_XVE_SPEED_5P0;
45 else if (strncmp(kbuff, "Gen3", check_len) == 0)
46 link_speed = GPU_XVE_SPEED_8P0;
47 else
48 nvgpu_err(g, "%s: Unknown PCIe speed: %s",
49 __func__, kbuff);
50
51 if (!link_speed)
52 return -EINVAL;
53
54 /* Brief pause... To help rate limit this. */
55 nvgpu_msleep(250);
56
57 /*
58 * And actually set the speed. Yay.
59 */
60 ret = g->ops.xve.set_speed(g, link_speed);
61 if (ret)
62 return ret;
63
64 return len;
65}
66
67static int xve_link_speed_show(struct seq_file *s, void *unused)
68{
69 struct gk20a *g = s->private;
70 u32 speed;
71 int err;
72
73 err = g->ops.xve.get_speed(g, &speed);
74 if (err)
75 return err;
76
77 seq_printf(s, "Current PCIe speed:\n %s\n", xve_speed_to_str(speed));
78
79 return 0;
80}
81
82static int xve_link_speed_open(struct inode *inode, struct file *file)
83{
84 return single_open(file, xve_link_speed_show, inode->i_private);
85}
86
87static const struct file_operations xve_link_speed_fops = {
88 .open = xve_link_speed_open,
89 .read = seq_read,
90 .write = xve_link_speed_write,
91 .llseek = seq_lseek,
92 .release = single_release,
93};
94
95static int xve_available_speeds_show(struct seq_file *s, void *unused)
96{
97 struct gk20a *g = s->private;
98 u32 available_speeds;
99
100 g->ops.xve.available_speeds(g, &available_speeds);
101
102 seq_puts(s, "Available PCIe bus speeds:\n");
103 if (available_speeds & GPU_XVE_SPEED_2P5)
104 seq_puts(s, " Gen1\n");
105 if (available_speeds & GPU_XVE_SPEED_5P0)
106 seq_puts(s, " Gen2\n");
107 if (available_speeds & GPU_XVE_SPEED_8P0)
108 seq_puts(s, " Gen3\n");
109
110 return 0;
111}
112
113static int xve_available_speeds_open(struct inode *inode, struct file *file)
114{
115 return single_open(file, xve_available_speeds_show, inode->i_private);
116}
117
118static const struct file_operations xve_available_speeds_fops = {
119 .open = xve_available_speeds_open,
120 .read = seq_read,
121 .llseek = seq_lseek,
122 .release = single_release,
123};
124
125static int xve_link_control_status_show(struct seq_file *s, void *unused)
126{
127 struct gk20a *g = s->private;
128 u32 link_status;
129
130 link_status = g->ops.xve.get_link_control_status(g);
131 seq_printf(s, "0x%08x\n", link_status);
132
133 return 0;
134}
135
136static int xve_link_control_status_open(struct inode *inode, struct file *file)
137{
138 return single_open(file, xve_link_control_status_show, inode->i_private);
139}
140
141static const struct file_operations xve_link_control_status_fops = {
142 .open = xve_link_control_status_open,
143 .read = seq_read,
144 .llseek = seq_lseek,
145 .release = single_release,
146};
147
148int nvgpu_xve_debugfs_init(struct gk20a *g)
149{
150 int err = -ENODEV;
151
152 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
153 struct dentry *gpu_root = l->debugfs;
154
155 l->debugfs_xve = debugfs_create_dir("xve", gpu_root);
156 if (IS_ERR_OR_NULL(l->debugfs_xve))
157 goto fail;
158
159 /*
160 * These are just debug nodes. If they fail to get made it's not worth
161 * worrying the higher level SW.
162 */
163 debugfs_create_file("link_speed", S_IRUGO,
164 l->debugfs_xve, g,
165 &xve_link_speed_fops);
166 debugfs_create_file("available_speeds", S_IRUGO,
167 l->debugfs_xve, g,
168 &xve_available_speeds_fops);
169 debugfs_create_file("link_control_status", S_IRUGO,
170 l->debugfs_xve, g,
171 &xve_link_control_status_fops);
172
173 err = 0;
174fail:
175 return err;
176}
diff --git a/drivers/gpu/nvgpu/common/linux/debug_xve.h b/drivers/gpu/nvgpu/common/linux/debug_xve.h
new file mode 100644
index 00000000..f3b1ac54
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/linux/debug_xve.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) 2017 NVIDIA Corporation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#ifndef __NVGPU_DEBUG_XVE_H__
16#define __NVGPU_DEBUG_XVE_H__
17
18struct gk20a;
19int nvgpu_xve_debugfs_init(struct gk20a *g);
20
21#endif /* __NVGPU_DEBUG_SVE_H__ */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 63ea5bc4..455fa238 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -329,7 +329,6 @@ int gk20a_finalize_poweron(struct gk20a *g)
329 if (platform->disable_aspm && g->ops.xve.disable_aspm) 329 if (platform->disable_aspm && g->ops.xve.disable_aspm)
330 g->ops.xve.disable_aspm(g); 330 g->ops.xve.disable_aspm(g);
331 331
332 g->ops.xve.sw_init(g);
333 g->ops.xve.available_speeds(g, &speed); 332 g->ops.xve.available_speeds(g, &speed);
334 333
335 /* Set to max speed */ 334 /* Set to max speed */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 69cb2253..d2a752d7 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -971,7 +971,6 @@ struct gpu_ops {
971 } css; 971 } css;
972#endif 972#endif
973 struct { 973 struct {
974 int (*sw_init)(struct gk20a *g);
975 int (*get_speed)(struct gk20a *g, u32 *xve_link_speed); 974 int (*get_speed)(struct gk20a *g, u32 *xve_link_speed);
976 int (*set_speed)(struct gk20a *g, u32 xve_link_speed); 975 int (*set_speed)(struct gk20a *g, u32 xve_link_speed);
977 void (*available_speeds)(struct gk20a *g, u32 *speed_mask); 976 void (*available_speeds)(struct gk20a *g, u32 *speed_mask);
@@ -984,6 +983,7 @@ struct gpu_ops {
984#endif 983#endif
985 void (*enable_shadow_rom)(struct gk20a *g); 984 void (*enable_shadow_rom)(struct gk20a *g);
986 void (*disable_shadow_rom)(struct gk20a *g); 985 void (*disable_shadow_rom)(struct gk20a *g);
986 u32 (*get_link_control_status)(struct gk20a *g);
987 } xve; 987 } xve;
988 struct { 988 struct {
989 void (*falcon_hal_sw_init)(struct nvgpu_falcon *flcn); 989 void (*falcon_hal_sw_init)(struct nvgpu_falcon *flcn);
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 7e7fc195..b33e80ec 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -660,7 +660,6 @@ static const struct gpu_ops gp106_ops = {
660 }, 660 },
661#endif 661#endif
662 .xve = { 662 .xve = {
663 .sw_init = xve_sw_init_gp106,
664 .get_speed = xve_get_speed_gp106, 663 .get_speed = xve_get_speed_gp106,
665 .set_speed = xve_set_speed_gp106, 664 .set_speed = xve_set_speed_gp106,
666 .available_speeds = xve_available_speeds_gp106, 665 .available_speeds = xve_available_speeds_gp106,
@@ -673,6 +672,7 @@ static const struct gpu_ops gp106_ops = {
673#endif 672#endif
674 .enable_shadow_rom = xve_enable_shadow_rom_gp106, 673 .enable_shadow_rom = xve_enable_shadow_rom_gp106,
675 .disable_shadow_rom = xve_disable_shadow_rom_gp106, 674 .disable_shadow_rom = xve_disable_shadow_rom_gp106,
675 .get_link_control_status = xve_get_link_control_status,
676 }, 676 },
677 .falcon = { 677 .falcon = {
678 .falcon_hal_sw_init = gp106_falcon_hal_sw_init, 678 .falcon_hal_sw_init = gp106_falcon_hal_sw_init,
diff --git a/drivers/gpu/nvgpu/gp106/xve_gp106.c b/drivers/gpu/nvgpu/gp106/xve_gp106.c
index a3514fc0..3a84ca17 100644
--- a/drivers/gpu/nvgpu/gp106/xve_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/xve_gp106.c
@@ -14,17 +14,13 @@
14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */ 15 */
16 16
17#ifdef CONFIG_DEBUG_FS
18#include <linux/debugfs.h>
19#include <linux/uaccess.h>
20#endif
21
22#include "gk20a/gk20a.h" 17#include "gk20a/gk20a.h"
23#include "gm206/bios_gm206.h" 18#include "gm206/bios_gm206.h"
24#include "gp106/xve_gp106.h" 19#include "gp106/xve_gp106.h"
25#include "common/linux/os_linux.h" 20#include "common/linux/os_linux.h"
26 21
27#include <nvgpu/bug.h> 22#include <nvgpu/bug.h>
23#include <nvgpu/xve.h>
28 24
29#include <nvgpu/hw/gp106/hw_xp_gp106.h> 25#include <nvgpu/hw/gp106/hw_xp_gp106.h>
30#include <nvgpu/hw/gp106/hw_xve_gp106.h> 26#include <nvgpu/hw/gp106/hw_xve_gp106.h>
@@ -475,165 +471,6 @@ void xve_available_speeds_gp106(struct gk20a *g, u32 *speed_mask)
475 *speed_mask = GPU_XVE_SPEED_2P5 | GPU_XVE_SPEED_5P0; 471 *speed_mask = GPU_XVE_SPEED_2P5 | GPU_XVE_SPEED_5P0;
476} 472}
477 473
478#ifdef CONFIG_DEBUG_FS
479static ssize_t xve_link_speed_write(struct file *filp,
480 const char __user *buff,
481 size_t len, loff_t *off)
482{
483 struct gk20a *g = ((struct seq_file *)filp->private_data)->private;
484 char kbuff[16];
485 u32 buff_size, check_len;
486 u32 link_speed = 0;
487 int ret;
488
489 buff_size = min_t(size_t, 16, len);
490
491 memset(kbuff, 0, 16);
492 if (copy_from_user(kbuff, buff, buff_size))
493 return -EFAULT;
494
495 check_len = strlen("Gen1");
496 if (strncmp(kbuff, "Gen1", check_len) == 0)
497 link_speed = GPU_XVE_SPEED_2P5;
498 else if (strncmp(kbuff, "Gen2", check_len) == 0)
499 link_speed = GPU_XVE_SPEED_5P0;
500 else if (strncmp(kbuff, "Gen3", check_len) == 0)
501 link_speed = GPU_XVE_SPEED_8P0;
502 else
503 nvgpu_err(g, "%s: Unknown PCIe speed: %s",
504 __func__, kbuff);
505
506 if (!link_speed)
507 return -EINVAL;
508
509 /* Brief pause... To help rate limit this. */
510 nvgpu_msleep(250);
511
512 /*
513 * And actually set the speed. Yay.
514 */
515 ret = g->ops.xve.set_speed(g, link_speed);
516 if (ret)
517 return ret;
518
519 return len;
520}
521
522static int xve_link_speed_show(struct seq_file *s, void *unused)
523{
524 struct gk20a *g = s->private;
525 u32 speed;
526 int err;
527
528 err = g->ops.xve.get_speed(g, &speed);
529 if (err)
530 return err;
531
532 seq_printf(s, "Current PCIe speed:\n %s\n", xve_speed_to_str(speed));
533
534 return 0;
535}
536
537static int xve_link_speed_open(struct inode *inode, struct file *file)
538{
539 return single_open(file, xve_link_speed_show, inode->i_private);
540}
541
542static const struct file_operations xve_link_speed_fops = {
543 .open = xve_link_speed_open,
544 .read = seq_read,
545 .write = xve_link_speed_write,
546 .llseek = seq_lseek,
547 .release = single_release,
548};
549
550static int xve_available_speeds_show(struct seq_file *s, void *unused)
551{
552 struct gk20a *g = s->private;
553 u32 available_speeds;
554
555 g->ops.xve.available_speeds(g, &available_speeds);
556
557 seq_puts(s, "Available PCIe bus speeds:\n");
558 if (available_speeds & GPU_XVE_SPEED_2P5)
559 seq_puts(s, " Gen1\n");
560 if (available_speeds & GPU_XVE_SPEED_5P0)
561 seq_puts(s, " Gen2\n");
562 if (available_speeds & GPU_XVE_SPEED_8P0)
563 seq_puts(s, " Gen3\n");
564
565 return 0;
566}
567
568static int xve_available_speeds_open(struct inode *inode, struct file *file)
569{
570 return single_open(file, xve_available_speeds_show, inode->i_private);
571}
572
573static const struct file_operations xve_available_speeds_fops = {
574 .open = xve_available_speeds_open,
575 .read = seq_read,
576 .llseek = seq_lseek,
577 .release = single_release,
578};
579
580static int xve_link_control_status_show(struct seq_file *s, void *unused)
581{
582 struct gk20a *g = s->private;
583 u32 link_status;
584
585 link_status = g->ops.xve.xve_readl(g, xve_link_control_status_r());
586 seq_printf(s, "0x%08x\n", link_status);
587
588 return 0;
589}
590
591static int xve_link_control_status_open(struct inode *inode, struct file *file)
592{
593 return single_open(file, xve_link_control_status_show, inode->i_private);
594}
595
596static const struct file_operations xve_link_control_status_fops = {
597 .open = xve_link_control_status_open,
598 .read = seq_read,
599 .llseek = seq_lseek,
600 .release = single_release,
601};
602#endif
603
604int xve_sw_init_gp106(struct gk20a *g)
605{
606 int err = -ENODEV;
607#ifdef CONFIG_DEBUG_FS
608 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
609 struct dentry *gpu_root = l->debugfs;
610
611 l->debugfs_xve = debugfs_create_dir("xve", gpu_root);
612 if (IS_ERR_OR_NULL(l->debugfs_xve))
613 goto fail;
614
615 /*
616 * These are just debug nodes. If they fail to get made it's not worth
617 * worrying the higher level SW.
618 */
619 debugfs_create_file("link_speed", S_IRUGO,
620 l->debugfs_xve, g,
621 &xve_link_speed_fops);
622 debugfs_create_file("available_speeds", S_IRUGO,
623 l->debugfs_xve, g,
624 &xve_available_speeds_fops);
625 debugfs_create_file("link_control_status", S_IRUGO,
626 l->debugfs_xve, g,
627 &xve_link_control_status_fops);
628
629 err = 0;
630fail:
631 return err;
632#else
633 return err;
634#endif
635}
636
637#if defined(CONFIG_PCI_MSI) 474#if defined(CONFIG_PCI_MSI)
638void xve_rearm_msi_gp106(struct gk20a *g) 475void xve_rearm_msi_gp106(struct gk20a *g)
639{ 476{
@@ -653,3 +490,8 @@ void xve_disable_shadow_rom_gp106(struct gk20a *g)
653 g->ops.xve.xve_writel(g, xve_rom_ctrl_r(), 490 g->ops.xve.xve_writel(g, xve_rom_ctrl_r(),
654 xve_rom_ctrl_rom_shadow_disabled_f()); 491 xve_rom_ctrl_rom_shadow_disabled_f());
655} 492}
493
494u32 xve_get_link_control_status(struct gk20a *g)
495{
496 return g->ops.xve.xve_readl(g, xve_link_control_status_r());
497}
diff --git a/drivers/gpu/nvgpu/gp106/xve_gp106.h b/drivers/gpu/nvgpu/gp106/xve_gp106.h
index 37ead910..55192fc8 100644
--- a/drivers/gpu/nvgpu/gp106/xve_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/xve_gp106.h
@@ -29,55 +29,6 @@ int gp106_init_xve_ops(struct gpu_ops *gops);
29#define GPU_XVE_TIMEOUT_MS 500 29#define GPU_XVE_TIMEOUT_MS 500
30 30
31/* 31/*
32 * For the available speeds bitmap.
33 */
34#define GPU_XVE_SPEED_2P5 (1 << 0)
35#define GPU_XVE_SPEED_5P0 (1 << 1)
36#define GPU_XVE_SPEED_8P0 (1 << 2)
37#define GPU_XVE_NR_SPEEDS 3
38
39#define GPU_XVE_SPEED_MASK (GPU_XVE_SPEED_2P5 | \
40 GPU_XVE_SPEED_5P0 | \
41 GPU_XVE_SPEED_8P0)
42
43/*
44 * The HW uses a 2 bit field where speed is defined by a number:
45 *
46 * NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_2P5 = 1
47 * NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_5P0 = 2
48 * NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_8P0 = 3
49 *
50 * This isn't ideal for a bitmap with available speeds. So the external
51 * APIs think about speeds as a bit in a bitmap and this function converts
52 * from those bits to the actual HW speed setting.
53 *
54 * @speed_bit must have only 1 bit set and must be one of the 3 available
55 * HW speeds. Not all chips support all speeds so use available_speeds() to
56 * determine what a given chip supports.
57 */
58static inline u32 xve_speed_to_hw_speed_setting(u32 speed_bit)
59{
60 if (!speed_bit ||
61 !is_power_of_2(speed_bit) ||
62 !(speed_bit & GPU_XVE_SPEED_MASK))
63 return -EINVAL;
64
65 return ilog2(speed_bit) + 1;
66}
67
68static inline const char *xve_speed_to_str(u32 speed)
69{
70 if (!speed || !is_power_of_2(speed) ||
71 !(speed & GPU_XVE_SPEED_MASK))
72 return "Unknown ???";
73
74 return speed & GPU_XVE_SPEED_2P5 ? "Gen1" :
75 speed & GPU_XVE_SPEED_5P0 ? "Gen2" :
76 speed & GPU_XVE_SPEED_8P0 ? "Gen3" :
77 "Unknown ???";
78}
79
80/*
81 * Debugging for the speed change. 32 * Debugging for the speed change.
82 */ 33 */
83enum xv_speed_change_steps { 34enum xv_speed_change_steps {
@@ -104,7 +55,7 @@ int xve_get_speed_gp106(struct gk20a *g, u32 *xve_link_speed);
104void xve_disable_aspm_gp106(struct gk20a *g); 55void xve_disable_aspm_gp106(struct gk20a *g);
105int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed); 56int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed);
106void xve_available_speeds_gp106(struct gk20a *g, u32 *speed_mask); 57void xve_available_speeds_gp106(struct gk20a *g, u32 *speed_mask);
107int xve_sw_init_gp106(struct gk20a *g); 58u32 xve_get_link_control_status(struct gk20a *g);
108#if defined(CONFIG_PCI_MSI) 59#if defined(CONFIG_PCI_MSI)
109void xve_rearm_msi_gp106(struct gk20a *g); 60void xve_rearm_msi_gp106(struct gk20a *g);
110#endif 61#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/xve.h b/drivers/gpu/nvgpu/include/nvgpu/xve.h
new file mode 100644
index 00000000..ee599300
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/xve.h
@@ -0,0 +1,58 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13#ifndef __NVGPU_XVE_H__
14#define __NVGPU_XVE_H__
15
16#include <nvgpu/types.h>
17#include <nvgpu/log2.h>
18
19/*
20 * For the available speeds bitmap.
21 */
22#define GPU_XVE_SPEED_2P5 (1 << 0)
23#define GPU_XVE_SPEED_5P0 (1 << 1)
24#define GPU_XVE_SPEED_8P0 (1 << 2)
25#define GPU_XVE_NR_SPEEDS 3
26
27#define GPU_XVE_SPEED_MASK (GPU_XVE_SPEED_2P5 | \
28 GPU_XVE_SPEED_5P0 | \
29 GPU_XVE_SPEED_8P0)
30
31/*
32 * The HW uses a 2 bit field where speed is defined by a number:
33 *
34 * NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_2P5 = 1
35 * NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_5P0 = 2
36 * NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_8P0 = 3
37 *
38 * This isn't ideal for a bitmap with available speeds. So the external
39 * APIs think about speeds as a bit in a bitmap and this function converts
40 * from those bits to the actual HW speed setting.
41 *
42 * @speed_bit must have only 1 bit set and must be one of the 3 available
43 * HW speeds. Not all chips support all speeds so use available_speeds() to
44 * determine what a given chip supports.
45 */
46static inline const char *xve_speed_to_str(u32 speed)
47{
48 if (!speed || !is_power_of_2(speed) ||
49 !(speed & GPU_XVE_SPEED_MASK))
50 return "Unknown ???";
51
52 return speed & GPU_XVE_SPEED_2P5 ? "Gen1" :
53 speed & GPU_XVE_SPEED_5P0 ? "Gen2" :
54 speed & GPU_XVE_SPEED_8P0 ? "Gen3" :
55 "Unknown ???";
56}
57
58#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-05 00:01:43 -0400