diff options
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 27 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 1 |
2 files changed, 17 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index b6aa40e6..ee64b90f 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1386,7 +1386,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1386 | gm20b_init_pmu_setup_hw1(g, desc, acr->hsbl_ucode.size); | 1386 | gm20b_init_pmu_setup_hw1(g, desc, acr->hsbl_ucode.size); |
1387 | /* Poll for HALT */ | 1387 | /* Poll for HALT */ |
1388 | if (b_wait_for_halt) { | 1388 | if (b_wait_for_halt) { |
1389 | err = pmu_wait_for_halt(g, gk20a_get_gr_idle_timeout(g)); | 1389 | err = pmu_wait_for_halt(g, ACR_COMPLETION_TIMEOUT_MS); |
1390 | if (err == 0) { | 1390 | if (err == 0) { |
1391 | /* Clear the HALT interrupt */ | 1391 | /* Clear the HALT interrupt */ |
1392 | if (clear_halt_interrupt_status(g, gk20a_get_gr_idle_timeout(g))) | 1392 | if (clear_halt_interrupt_status(g, gk20a_get_gr_idle_timeout(g))) |
@@ -1414,31 +1414,36 @@ err_done: | |||
1414 | /*! | 1414 | /*! |
1415 | * Wait for PMU to halt | 1415 | * Wait for PMU to halt |
1416 | * @param[in] g GPU object pointer | 1416 | * @param[in] g GPU object pointer |
1417 | * @param[in] timeout_us Timeout in msec for PMU to halt | 1417 | * @param[in] timeout Timeout in msec for PMU to halt |
1418 | * @return '0' if PMU halts | 1418 | * @return '0' if PMU halts |
1419 | */ | 1419 | */ |
1420 | int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout) | 1420 | int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout) |
1421 | { | 1421 | { |
1422 | u32 data = 0; | 1422 | u32 data = 0; |
1423 | int completion = -EBUSY; | ||
1423 | unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout); | 1424 | unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout); |
1424 | 1425 | ||
1425 | while (time_before(jiffies, end_jiffies) || | 1426 | while (time_before(jiffies, end_jiffies) || |
1426 | !tegra_platform_is_silicon()) { | 1427 | !tegra_platform_is_silicon()) { |
1427 | data = gk20a_readl(g, pwr_falcon_cpuctl_r()); | 1428 | data = gk20a_readl(g, pwr_falcon_cpuctl_r()); |
1428 | if (data & pwr_falcon_cpuctl_halt_intr_m()) | 1429 | if (data & pwr_falcon_cpuctl_halt_intr_m()) { |
1429 | /*CPU is halted break*/ | 1430 | /*CPU is halted break*/ |
1431 | completion = 0; | ||
1430 | break; | 1432 | break; |
1431 | timeout--; | 1433 | } |
1432 | udelay(1); | 1434 | udelay(1); |
1433 | } | 1435 | } |
1434 | if (timeout == 0) | 1436 | if (completion) |
1435 | return -EBUSY; | 1437 | gk20a_err(dev_from_gk20a(g), "ACR boot timed out"); |
1436 | data = gk20a_readl(g, pwr_falcon_mailbox0_r()); | 1438 | else { |
1437 | if (data) { | 1439 | data = gk20a_readl(g, pwr_falcon_mailbox0_r()); |
1438 | gk20a_err(dev_from_gk20a(g), "ACR boot failed, err %x", data); | 1440 | if (data) { |
1439 | return -EAGAIN; | 1441 | gk20a_err(dev_from_gk20a(g), |
1442 | "ACR boot failed, err %x", data); | ||
1443 | completion = -EAGAIN; | ||
1444 | } | ||
1440 | } | 1445 | } |
1441 | return 0; | 1446 | return completion; |
1442 | } | 1447 | } |
1443 | 1448 | ||
1444 | /*! | 1449 | /*! |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index 83a0babd..58800c09 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h | |||
@@ -19,6 +19,7 @@ | |||
19 | #include "mm_gm20b.h" | 19 | #include "mm_gm20b.h" |
20 | 20 | ||
21 | /*Defines*/ | 21 | /*Defines*/ |
22 | #define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */ | ||
22 | 23 | ||
23 | /*chip specific defines*/ | 24 | /*chip specific defines*/ |
24 | #define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/ | 25 | #define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/ |