diff options
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 20 | ||||
-rw-r--r-- | include/linux/tegra_vgpu.h | 9 |
2 files changed, 28 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index a7e9eed8..e636d5ae 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -570,6 +570,25 @@ static int vgpu_fifo_set_runlist_interleave(struct gk20a *g, | |||
570 | return err ? err : msg.ret; | 570 | return err ? err : msg.ret; |
571 | } | 571 | } |
572 | 572 | ||
573 | int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) | ||
574 | { | ||
575 | struct gk20a_platform *platform = gk20a_get_platform(ch->g->dev); | ||
576 | struct tegra_vgpu_cmd_msg msg; | ||
577 | struct tegra_vgpu_channel_timeslice_params *p = | ||
578 | &msg.params.channel_timeslice; | ||
579 | int err; | ||
580 | |||
581 | gk20a_dbg_fn(""); | ||
582 | |||
583 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE; | ||
584 | msg.handle = platform->virt_handle; | ||
585 | p->handle = ch->virt_ctx; | ||
586 | p->timeslice_us = timeslice; | ||
587 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
588 | WARN_ON(err || msg.ret); | ||
589 | return err ? err : msg.ret; | ||
590 | } | ||
591 | |||
573 | static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, | 592 | static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, |
574 | struct channel_gk20a *ch) | 593 | struct channel_gk20a *ch) |
575 | { | 594 | { |
@@ -656,4 +675,5 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops) | |||
656 | gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle; | 675 | gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle; |
657 | gops->fifo.channel_set_priority = vgpu_channel_set_priority; | 676 | gops->fifo.channel_set_priority = vgpu_channel_set_priority; |
658 | gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave; | 677 | gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave; |
678 | gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice; | ||
659 | } | 679 | } |
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 5f697e78..d84d0c63 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -75,7 +75,8 @@ enum { | |||
75 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE, | 75 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE, |
76 | TEGRA_VGPU_CMD_REG_OPS, | 76 | TEGRA_VGPU_CMD_REG_OPS, |
77 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY, | 77 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY, |
78 | TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE | 78 | TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE, |
79 | TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE | ||
79 | }; | 80 | }; |
80 | 81 | ||
81 | struct tegra_vgpu_connect_params { | 82 | struct tegra_vgpu_connect_params { |
@@ -305,6 +306,11 @@ struct tegra_vgpu_channel_runlist_interleave_params { | |||
305 | u32 level; | 306 | u32 level; |
306 | }; | 307 | }; |
307 | 308 | ||
309 | struct tegra_vgpu_channel_timeslice_params { | ||
310 | u64 handle; | ||
311 | u32 timeslice_us; | ||
312 | }; | ||
313 | |||
308 | struct tegra_vgpu_cmd_msg { | 314 | struct tegra_vgpu_cmd_msg { |
309 | u32 cmd; | 315 | u32 cmd; |
310 | int ret; | 316 | int ret; |
@@ -334,6 +340,7 @@ struct tegra_vgpu_cmd_msg { | |||
334 | struct tegra_vgpu_reg_ops_params reg_ops; | 340 | struct tegra_vgpu_reg_ops_params reg_ops; |
335 | struct tegra_vgpu_channel_priority_params channel_priority; | 341 | struct tegra_vgpu_channel_priority_params channel_priority; |
336 | struct tegra_vgpu_channel_runlist_interleave_params channel_interleave; | 342 | struct tegra_vgpu_channel_runlist_interleave_params channel_interleave; |
343 | struct tegra_vgpu_channel_timeslice_params channel_timeslice; | ||
337 | char padding[192]; | 344 | char padding[192]; |
338 | } params; | 345 | } params; |
339 | }; | 346 | }; |