diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 31 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 1 | ||||
-rw-r--r-- | include/uapi/linux/nvgpu.h | 10 |
5 files changed, 44 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 654388cb..9b1f2987 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -44,6 +44,9 @@ | |||
44 | 44 | ||
45 | #define NVGPU_BEGIN_AGGRESSIVE_SYNC_DESTROY_LIMIT 64 /* channels */ | 45 | #define NVGPU_BEGIN_AGGRESSIVE_SYNC_DESTROY_LIMIT 64 /* channels */ |
46 | 46 | ||
47 | #define NVGPU_CHANNEL_MIN_TIMESLICE_US 1000 | ||
48 | #define NVGPU_CHANNEL_MAX_TIMESLICE_US 50000 | ||
49 | |||
47 | static struct channel_gk20a *allocate_channel(struct fifo_gk20a *f); | 50 | static struct channel_gk20a *allocate_channel(struct fifo_gk20a *f); |
48 | static void free_channel(struct fifo_gk20a *f, struct channel_gk20a *c); | 51 | static void free_channel(struct fifo_gk20a *f, struct channel_gk20a *c); |
49 | 52 | ||
@@ -2633,6 +2636,21 @@ int gk20a_channel_set_priority(struct channel_gk20a *ch, u32 priority) | |||
2633 | timeslice_timeout); | 2636 | timeslice_timeout); |
2634 | } | 2637 | } |
2635 | 2638 | ||
2639 | int gk20a_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) | ||
2640 | { | ||
2641 | if (gk20a_is_channel_marked_as_tsg(ch)) { | ||
2642 | gk20a_err(dev_from_gk20a(ch->g), | ||
2643 | "invalid operation for TSG!\n"); | ||
2644 | return -EINVAL; | ||
2645 | } | ||
2646 | |||
2647 | if (timeslice < NVGPU_CHANNEL_MIN_TIMESLICE_US || | ||
2648 | timeslice > NVGPU_CHANNEL_MAX_TIMESLICE_US) | ||
2649 | return -EINVAL; | ||
2650 | |||
2651 | return channel_gk20a_set_schedule_params(ch, timeslice); | ||
2652 | } | ||
2653 | |||
2636 | static int gk20a_channel_zcull_bind(struct channel_gk20a *ch, | 2654 | static int gk20a_channel_zcull_bind(struct channel_gk20a *ch, |
2637 | struct nvgpu_zcull_bind_args *args) | 2655 | struct nvgpu_zcull_bind_args *args) |
2638 | { | 2656 | { |
@@ -2785,6 +2803,7 @@ void gk20a_init_channel(struct gpu_ops *gops) | |||
2785 | gops->fifo.free_inst = channel_gk20a_free_inst; | 2803 | gops->fifo.free_inst = channel_gk20a_free_inst; |
2786 | gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc; | 2804 | gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc; |
2787 | gops->fifo.channel_set_priority = gk20a_channel_set_priority; | 2805 | gops->fifo.channel_set_priority = gk20a_channel_set_priority; |
2806 | gops->fifo.channel_set_timeslice = gk20a_channel_set_timeslice; | ||
2788 | } | 2807 | } |
2789 | 2808 | ||
2790 | long gk20a_channel_ioctl(struct file *filp, | 2809 | long gk20a_channel_ioctl(struct file *filp, |
@@ -3047,6 +3066,18 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3047 | ((struct nvgpu_runlist_interleave_args *)buf)->level); | 3066 | ((struct nvgpu_runlist_interleave_args *)buf)->level); |
3048 | gk20a_idle(dev); | 3067 | gk20a_idle(dev); |
3049 | break; | 3068 | break; |
3069 | case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE: | ||
3070 | err = gk20a_busy(dev); | ||
3071 | if (err) { | ||
3072 | dev_err(&dev->dev, | ||
3073 | "%s: failed to host gk20a for ioctl cmd: 0x%x", | ||
3074 | __func__, cmd); | ||
3075 | break; | ||
3076 | } | ||
3077 | err = ch->g->ops.fifo.channel_set_timeslice(ch, | ||
3078 | ((struct nvgpu_timeslice_args *)buf)->timeslice_us); | ||
3079 | gk20a_idle(dev); | ||
3080 | break; | ||
3050 | default: | 3081 | default: |
3051 | dev_dbg(&dev->dev, "unrecognized ioctl cmd: 0x%x", cmd); | 3082 | dev_dbg(&dev->dev, "unrecognized ioctl cmd: 0x%x", cmd); |
3052 | err = -ENOTTY; | 3083 | err = -ENOTTY; |
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index 3f5a657a..e3fbba3e 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -275,5 +275,6 @@ int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, | |||
275 | int timeslice_period, | 275 | int timeslice_period, |
276 | int *__timeslice_timeout, int *__timeslice_scale); | 276 | int *__timeslice_timeout, int *__timeslice_scale); |
277 | int gk20a_channel_set_priority(struct channel_gk20a *ch, u32 priority); | 277 | int gk20a_channel_set_priority(struct channel_gk20a *ch, u32 priority); |
278 | int gk20a_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice); | ||
278 | 279 | ||
279 | #endif /* CHANNEL_GK20A_H */ | 280 | #endif /* CHANNEL_GK20A_H */ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index faccf04a..8b87c7aa 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -269,6 +269,8 @@ struct gpu_ops { | |||
269 | int (*set_runlist_interleave)(struct gk20a *g, u32 id, | 269 | int (*set_runlist_interleave)(struct gk20a *g, u32 id, |
270 | bool is_tsg, u32 runlist_id, | 270 | bool is_tsg, u32 runlist_id, |
271 | u32 new_level); | 271 | u32 new_level); |
272 | int (*channel_set_timeslice)(struct channel_gk20a *ch, | ||
273 | u32 timeslice); | ||
272 | } fifo; | 274 | } fifo; |
273 | struct pmu_v { | 275 | struct pmu_v { |
274 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ | 276 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 3fded03c..b9763224 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -114,6 +114,7 @@ void gm20b_init_fifo(struct gpu_ops *gops) | |||
114 | gops->fifo.free_inst = channel_gk20a_free_inst; | 114 | gops->fifo.free_inst = channel_gk20a_free_inst; |
115 | gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc; | 115 | gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc; |
116 | gops->fifo.channel_set_priority = gk20a_channel_set_priority; | 116 | gops->fifo.channel_set_priority = gk20a_channel_set_priority; |
117 | gops->fifo.channel_set_timeslice = gk20a_channel_set_timeslice; | ||
117 | 118 | ||
118 | gops->fifo.preempt_channel = gk20a_fifo_preempt_channel; | 119 | gops->fifo.preempt_channel = gk20a_fifo_preempt_channel; |
119 | gops->fifo.update_runlist = gk20a_fifo_update_runlist; | 120 | gops->fifo.update_runlist = gk20a_fifo_update_runlist; |
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 68c1c4e0..0c8de87f 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -880,6 +880,12 @@ struct nvgpu_runlist_interleave_args { | |||
880 | #define NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH 2 | 880 | #define NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH 2 |
881 | #define NVGPU_RUNLIST_INTERLEAVE_NUM_LEVELS 3 | 881 | #define NVGPU_RUNLIST_INTERLEAVE_NUM_LEVELS 3 |
882 | 882 | ||
883 | /* controls how long a channel occupies an engine uninterrupted */ | ||
884 | struct nvgpu_timeslice_args { | ||
885 | __u32 timeslice_us; | ||
886 | __u32 reserved; | ||
887 | }; | ||
888 | |||
883 | #define NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD \ | 889 | #define NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD \ |
884 | _IOW(NVGPU_IOCTL_MAGIC, 5, struct nvgpu_set_nvmap_fd_args) | 890 | _IOW(NVGPU_IOCTL_MAGIC, 5, struct nvgpu_set_nvmap_fd_args) |
885 | #define NVGPU_IOCTL_CHANNEL_SET_TIMEOUT \ | 891 | #define NVGPU_IOCTL_CHANNEL_SET_TIMEOUT \ |
@@ -924,9 +930,11 @@ struct nvgpu_runlist_interleave_args { | |||
924 | _IOW(NVGPU_IOCTL_MAGIC, 119, struct nvgpu_channel_wdt_args) | 930 | _IOW(NVGPU_IOCTL_MAGIC, 119, struct nvgpu_channel_wdt_args) |
925 | #define NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE \ | 931 | #define NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE \ |
926 | _IOW(NVGPU_IOCTL_MAGIC, 120, struct nvgpu_runlist_interleave_args) | 932 | _IOW(NVGPU_IOCTL_MAGIC, 120, struct nvgpu_runlist_interleave_args) |
933 | #define NVGPU_IOCTL_CHANNEL_SET_TIMESLICE \ | ||
934 | _IOW(NVGPU_IOCTL_MAGIC, 121, struct nvgpu_timeslice_args) | ||
927 | 935 | ||
928 | #define NVGPU_IOCTL_CHANNEL_LAST \ | 936 | #define NVGPU_IOCTL_CHANNEL_LAST \ |
929 | _IOC_NR(NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE) | 937 | _IOC_NR(NVGPU_IOCTL_CHANNEL_SET_TIMESLICE) |
930 | #define NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvgpu_submit_gpfifo_args) | 938 | #define NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvgpu_submit_gpfifo_args) |
931 | 939 | ||
932 | /* | 940 | /* |