diff options
20 files changed, 591 insertions, 554 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 4def6ee4..ae169a1d 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -178,7 +178,8 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | |||
178 | common/linux/vgpu/gm20b/vgpu_gr_gm20b.o \ | 178 | common/linux/vgpu/gm20b/vgpu_gr_gm20b.o \ |
179 | common/linux/vgpu/sysfs_vgpu.o \ | 179 | common/linux/vgpu/sysfs_vgpu.o \ |
180 | common/linux/vgpu/vgpu_ivc.o \ | 180 | common/linux/vgpu/vgpu_ivc.o \ |
181 | common/linux/vgpu/vgpu_ivm.o | 181 | common/linux/vgpu/vgpu_ivm.o \ |
182 | common/linux/vgpu/vgpu_linux.o | ||
182 | 183 | ||
183 | nvgpu-$(CONFIG_COMMON_CLK) += \ | 184 | nvgpu-$(CONFIG_COMMON_CLK) += \ |
184 | common/linux/clk.o | 185 | common/linux/clk.o |
diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c index 5dfd8ff7..b103fcea 100644 --- a/drivers/gpu/nvgpu/common/linux/module.c +++ b/drivers/gpu/nvgpu/common/linux/module.c | |||
@@ -42,7 +42,7 @@ | |||
42 | 42 | ||
43 | #include "platform_gk20a.h" | 43 | #include "platform_gk20a.h" |
44 | #include "sysfs.h" | 44 | #include "sysfs.h" |
45 | #include "vgpu/vgpu.h" | 45 | #include "vgpu/vgpu_linux.h" |
46 | #include "scale.h" | 46 | #include "scale.h" |
47 | #include "pci.h" | 47 | #include "pci.h" |
48 | #include "module.h" | 48 | #include "module.h" |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/ce2_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/ce2_vgpu.c index ffb85f16..5da6f88a 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/ce2_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/ce2_vgpu.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU CE2 | 2 | * Virtualized GPU CE2 |
3 | * | 3 | * |
4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -17,6 +17,7 @@ | |||
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include "vgpu.h" | 19 | #include "vgpu.h" |
20 | #include "gk20a/channel_gk20a.h" | ||
20 | 21 | ||
21 | #include <nvgpu/bug.h> | 22 | #include <nvgpu/bug.h> |
22 | 23 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.c index bcdf8ee9..285cd481 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU Clock Interface | 2 | * Virtualized GPU Clock Interface |
3 | * | 3 | * |
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -16,8 +16,11 @@ | |||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include "gk20a/gk20a.h" | ||
19 | #include "vgpu.h" | 20 | #include "vgpu.h" |
20 | #include "clk_vgpu.h" | 21 | #include "clk_vgpu.h" |
22 | #include "ctrl/ctrlclk.h" | ||
23 | #include "common/linux/platform_gk20a.h" | ||
21 | 24 | ||
22 | static unsigned long | 25 | static unsigned long |
23 | vgpu_freq_table[TEGRA_VGPU_GPU_FREQ_TABLE_SIZE]; | 26 | vgpu_freq_table[TEGRA_VGPU_GPU_FREQ_TABLE_SIZE]; |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c index 6a0da7dc..bace705d 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include "common/linux/platform_gk20a.h" | 25 | #include "common/linux/platform_gk20a.h" |
26 | #include "common/linux/vgpu/vgpu.h" | 26 | #include "common/linux/vgpu/vgpu.h" |
27 | #include "common/linux/vgpu/css_vgpu.h" | 27 | #include "common/linux/vgpu/css_vgpu.h" |
28 | #include "common/linux/os_linux.h" | ||
28 | 29 | ||
29 | static struct tegra_hv_ivm_cookie *css_cookie; | 30 | static struct tegra_hv_ivm_cookie *css_cookie; |
30 | 31 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.c index f7e24382..f0558106 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <nvgpu/vgpu/tegra_vgpu.h> | 24 | #include <nvgpu/vgpu/tegra_vgpu.h> |
25 | 25 | ||
26 | #include "gk20a/gk20a.h" | 26 | #include "gk20a/gk20a.h" |
27 | #include "common/linux/os_linux.h" | ||
27 | #include "vgpu.h" | 28 | #include "vgpu.h" |
28 | #include "fecs_trace_vgpu.h" | 29 | #include "fecs_trace_vgpu.h" |
29 | 30 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c index 9b82ba8f..29f08d4b 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c | |||
@@ -25,11 +25,14 @@ | |||
25 | #include <nvgpu/bug.h> | 25 | #include <nvgpu/bug.h> |
26 | #include <nvgpu/barrier.h> | 26 | #include <nvgpu/barrier.h> |
27 | #include <nvgpu/error_notifier.h> | 27 | #include <nvgpu/error_notifier.h> |
28 | #include <nvgpu/vgpu/vgpu_ivc.h> | ||
28 | 29 | ||
30 | #include "gk20a/gk20a.h" | ||
29 | #include "vgpu.h" | 31 | #include "vgpu.h" |
30 | #include "fifo_vgpu.h" | 32 | #include "fifo_vgpu.h" |
31 | 33 | ||
32 | #include "common/linux/channel.h" | 34 | #include "common/linux/channel.h" |
35 | #include "common/linux/os_linux.h" | ||
33 | 36 | ||
34 | #include <nvgpu/hw/gk20a/hw_fifo_gk20a.h> | 37 | #include <nvgpu/hw/gk20a/hw_fifo_gk20a.h> |
35 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> | 38 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c index 161a69e9..64db07b5 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c | |||
@@ -24,6 +24,7 @@ | |||
24 | 24 | ||
25 | #include <nvgpu/bug.h> | 25 | #include <nvgpu/bug.h> |
26 | #include <nvgpu/dma.h> | 26 | #include <nvgpu/dma.h> |
27 | #include <nvgpu/vgpu/vgpu_ivc.h> | ||
27 | 28 | ||
28 | int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) | 29 | int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) |
29 | { | 30 | { |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c index 66e40647..816d5dd8 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c | |||
@@ -23,9 +23,11 @@ | |||
23 | #include <nvgpu/dma.h> | 23 | #include <nvgpu/dma.h> |
24 | #include <nvgpu/error_notifier.h> | 24 | #include <nvgpu/error_notifier.h> |
25 | #include <nvgpu/dma.h> | 25 | #include <nvgpu/dma.h> |
26 | #include <nvgpu/vgpu/vgpu_ivc.h> | ||
26 | 27 | ||
27 | #include "vgpu.h" | 28 | #include "vgpu.h" |
28 | #include "gr_vgpu.h" | 29 | #include "gr_vgpu.h" |
30 | #include "gk20a/gk20a.h" | ||
29 | #include "gk20a/dbg_gpu_gk20a.h" | 31 | #include "gk20a/dbg_gpu_gk20a.h" |
30 | #include "gk20a/channel_gk20a.h" | 32 | #include "gk20a/channel_gk20a.h" |
31 | #include "gk20a/tsg_gk20a.h" | 33 | #include "gk20a/tsg_gk20a.h" |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h index 4b81da91..efd9e09b 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h | |||
@@ -26,6 +26,7 @@ struct gr_zcull_info; | |||
26 | struct zbc_entry; | 26 | struct zbc_entry; |
27 | struct zbc_query_params; | 27 | struct zbc_query_params; |
28 | struct dbg_session_gk20a; | 28 | struct dbg_session_gk20a; |
29 | struct tsg_gk20a; | ||
29 | 30 | ||
30 | void vgpu_gr_detect_sm_arch(struct gk20a *g); | 31 | void vgpu_gr_detect_sm_arch(struct gk20a *g); |
31 | void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg); | 32 | void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg); |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.c index 627ad1a8..eacbbf9e 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU L2 | 2 | * Virtualized GPU L2 |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017 NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018 NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -16,6 +16,7 @@ | |||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include "gk20a/gk20a.h" | ||
19 | #include "vgpu.h" | 20 | #include "vgpu.h" |
20 | #include "ltc_vgpu.h" | 21 | #include "ltc_vgpu.h" |
21 | 22 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c index 7d73594d..708de769 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c | |||
@@ -31,6 +31,7 @@ | |||
31 | 31 | ||
32 | #include "vgpu.h" | 32 | #include "vgpu.h" |
33 | #include "mm_vgpu.h" | 33 | #include "mm_vgpu.h" |
34 | #include "gk20a/gk20a.h" | ||
34 | #include "gk20a/mm_gk20a.h" | 35 | #include "gk20a/mm_gk20a.h" |
35 | #include "gm20b/mm_gm20b.h" | 36 | #include "gm20b/mm_gm20b.h" |
36 | 37 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h index bb38fa27..b0937495 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h +++ b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -17,6 +17,11 @@ | |||
17 | #ifndef _MM_VGPU_H_ | 17 | #ifndef _MM_VGPU_H_ |
18 | #define _MM_VGPU_H_ | 18 | #define _MM_VGPU_H_ |
19 | 19 | ||
20 | struct nvgpu_mem; | ||
21 | struct channel_gk20a; | ||
22 | struct vm_gk20a_mapping_batch; | ||
23 | struct gk20a_as_share; | ||
24 | |||
20 | void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm, | 25 | void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm, |
21 | u64 vaddr, | 26 | u64 vaddr, |
22 | u64 size, | 27 | u64 size, |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/sysfs_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/sysfs_vgpu.c index 4025aabd..c8435efd 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/sysfs_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/sysfs_vgpu.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -17,6 +17,7 @@ | |||
17 | #include <linux/device.h> | 17 | #include <linux/device.h> |
18 | 18 | ||
19 | #include "vgpu.h" | 19 | #include "vgpu.h" |
20 | #include "common/linux/platform_gk20a.h" | ||
20 | 21 | ||
21 | static ssize_t vgpu_load_show(struct device *dev, | 22 | static ssize_t vgpu_load_show(struct device *dev, |
22 | struct device_attribute *attr, | 23 | struct device_attribute *attr, |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c index 7cf161e0..7915a599 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c | |||
@@ -1,6 +1,4 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU | ||
3 | * | ||
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 3 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
@@ -16,40 +14,15 @@ | |||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
17 | */ | 15 | */ |
18 | 16 | ||
19 | #include <linux/mm.h> | ||
20 | #include <linux/dma-mapping.h> | ||
21 | #include <linux/pm_runtime.h> | ||
22 | #include <linux/pm_qos.h> | ||
23 | #include <linux/platform_device.h> | ||
24 | #include <soc/tegra/chip-id.h> | ||
25 | #include <uapi/linux/nvgpu.h> | ||
26 | |||
27 | #include <nvgpu/kmem.h> | ||
28 | #include <nvgpu/bug.h> | ||
29 | #include <nvgpu/enabled.h> | 17 | #include <nvgpu/enabled.h> |
30 | #include <nvgpu/debug.h> | ||
31 | #include <nvgpu/bus.h> | 18 | #include <nvgpu/bus.h> |
32 | #include <nvgpu/soc.h> | 19 | #include <nvgpu/vgpu/vgpu_ivc.h> |
33 | #include <nvgpu/ctxsw_trace.h> | ||
34 | #include <nvgpu/defaults.h> | ||
35 | 20 | ||
21 | #include "gk20a/gk20a.h" | ||
36 | #include "vgpu.h" | 22 | #include "vgpu.h" |
37 | #include "fecs_trace_vgpu.h" | 23 | #include "fecs_trace_vgpu.h" |
38 | #include "clk_vgpu.h" | ||
39 | #include "gk20a/tsg_gk20a.h" | ||
40 | #include "gk20a/channel_gk20a.h" | ||
41 | #include "gk20a/regops_gk20a.h" | ||
42 | #include "gm20b/hal_gm20b.h" | ||
43 | |||
44 | #include "common/linux/module.h" | ||
45 | #include "common/linux/os_linux.h" | ||
46 | #include "common/linux/ioctl.h" | ||
47 | #include "common/linux/scale.h" | ||
48 | #include "common/linux/driver_common.h" | ||
49 | 24 | ||
50 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 25 | int vgpu_comm_init(struct gk20a *g) |
51 | |||
52 | static inline int vgpu_comm_init(struct gk20a *g) | ||
53 | { | 26 | { |
54 | size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES }; | 27 | size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES }; |
55 | 28 | ||
@@ -57,7 +30,7 @@ static inline int vgpu_comm_init(struct gk20a *g) | |||
57 | ARRAY_SIZE(queue_sizes)); | 30 | ARRAY_SIZE(queue_sizes)); |
58 | } | 31 | } |
59 | 32 | ||
60 | static inline void vgpu_comm_deinit(void) | 33 | void vgpu_comm_deinit(void) |
61 | { | 34 | { |
62 | size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES }; | 35 | size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES }; |
63 | 36 | ||
@@ -83,7 +56,7 @@ int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, | |||
83 | return err; | 56 | return err; |
84 | } | 57 | } |
85 | 58 | ||
86 | static u64 vgpu_connect(void) | 59 | u64 vgpu_connect(void) |
87 | { | 60 | { |
88 | struct tegra_vgpu_cmd_msg msg; | 61 | struct tegra_vgpu_cmd_msg msg; |
89 | struct tegra_vgpu_connect_params *p = &msg.params.connect; | 62 | struct tegra_vgpu_connect_params *p = &msg.params.connect; |
@@ -125,7 +98,7 @@ static void vgpu_handle_channel_event(struct gk20a *g, | |||
125 | } | 98 | } |
126 | 99 | ||
127 | if (info->id >= g->fifo.num_channels || | 100 | if (info->id >= g->fifo.num_channels || |
128 | info->event_id >= NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX) { | 101 | info->event_id >= TEGRA_VGPU_CHANNEL_EVENT_ID_MAX) { |
129 | nvgpu_err(g, "invalid channel event"); | 102 | nvgpu_err(g, "invalid channel event"); |
130 | return; | 103 | return; |
131 | } | 104 | } |
@@ -135,9 +108,7 @@ static void vgpu_handle_channel_event(struct gk20a *g, | |||
135 | gk20a_tsg_event_id_post_event(tsg, info->event_id); | 108 | gk20a_tsg_event_id_post_event(tsg, info->event_id); |
136 | } | 109 | } |
137 | 110 | ||
138 | 111 | int vgpu_intr_thread(void *dev_id) | |
139 | |||
140 | static int vgpu_intr_thread(void *dev_id) | ||
141 | { | 112 | { |
142 | struct gk20a *g = dev_id; | 113 | struct gk20a *g = dev_id; |
143 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | 114 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); |
@@ -201,11 +172,9 @@ static int vgpu_intr_thread(void *dev_id) | |||
201 | return 0; | 172 | return 0; |
202 | } | 173 | } |
203 | 174 | ||
204 | static void vgpu_remove_support(struct gk20a *g) | 175 | void vgpu_remove_support_common(struct gk20a *g) |
205 | { | 176 | { |
206 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 177 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); |
207 | struct vgpu_priv_data *priv = | ||
208 | vgpu_get_priv_data_from_dev(dev_from_gk20a(g)); | ||
209 | struct tegra_vgpu_intr_msg msg; | 178 | struct tegra_vgpu_intr_msg msg; |
210 | int err; | 179 | int err; |
211 | 180 | ||
@@ -229,104 +198,9 @@ static void vgpu_remove_support(struct gk20a *g) | |||
229 | &msg, sizeof(msg)); | 198 | &msg, sizeof(msg)); |
230 | WARN_ON(err); | 199 | WARN_ON(err); |
231 | nvgpu_thread_stop(&priv->intr_handler); | 200 | nvgpu_thread_stop(&priv->intr_handler); |
232 | |||
233 | /* free mappings to registers, etc*/ | ||
234 | |||
235 | if (l->bar1) { | ||
236 | iounmap(l->bar1); | ||
237 | l->bar1 = NULL; | ||
238 | } | ||
239 | } | ||
240 | |||
241 | static void vgpu_init_vars(struct gk20a *g, struct gk20a_platform *platform) | ||
242 | { | ||
243 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
244 | |||
245 | nvgpu_mutex_init(&g->poweron_lock); | ||
246 | nvgpu_mutex_init(&g->poweroff_lock); | ||
247 | l->regs_saved = l->regs; | ||
248 | l->bar1_saved = l->bar1; | ||
249 | |||
250 | nvgpu_init_list_node(&g->pending_sema_waits); | ||
251 | nvgpu_raw_spinlock_init(&g->pending_sema_waits_lock); | ||
252 | |||
253 | g->aggressive_sync_destroy = platform->aggressive_sync_destroy; | ||
254 | g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh; | ||
255 | g->has_syncpoints = platform->has_syncpoints; | ||
256 | g->ptimer_src_freq = platform->ptimer_src_freq; | ||
257 | g->can_railgate = platform->can_railgate_init; | ||
258 | g->railgate_delay = platform->railgate_delay_init; | ||
259 | |||
260 | __nvgpu_set_enabled(g, NVGPU_MM_UNIFY_ADDRESS_SPACES, | ||
261 | platform->unify_address_spaces); | ||
262 | } | ||
263 | |||
264 | static int vgpu_init_support(struct platform_device *pdev) | ||
265 | { | ||
266 | struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
267 | struct gk20a *g = get_gk20a(&pdev->dev); | ||
268 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
269 | void __iomem *regs; | ||
270 | int err = 0; | ||
271 | |||
272 | if (!r) { | ||
273 | nvgpu_err(g, "failed to get gk20a bar1"); | ||
274 | err = -ENXIO; | ||
275 | goto fail; | ||
276 | } | ||
277 | |||
278 | if (r->name && !strcmp(r->name, "/vgpu")) { | ||
279 | regs = devm_ioremap_resource(&pdev->dev, r); | ||
280 | if (IS_ERR(regs)) { | ||
281 | nvgpu_err(g, "failed to remap gk20a bar1"); | ||
282 | err = PTR_ERR(regs); | ||
283 | goto fail; | ||
284 | } | ||
285 | l->bar1 = regs; | ||
286 | l->bar1_mem = r; | ||
287 | } | ||
288 | |||
289 | nvgpu_mutex_init(&g->dbg_sessions_lock); | ||
290 | nvgpu_mutex_init(&g->client_lock); | ||
291 | |||
292 | nvgpu_init_list_node(&g->profiler_objects); | ||
293 | |||
294 | g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K); | ||
295 | if (!g->dbg_regops_tmp_buf) { | ||
296 | nvgpu_err(g, "couldn't allocate regops tmp buf"); | ||
297 | return -ENOMEM; | ||
298 | } | ||
299 | g->dbg_regops_tmp_buf_ops = | ||
300 | SZ_4K / sizeof(g->dbg_regops_tmp_buf[0]); | ||
301 | |||
302 | g->remove_support = vgpu_remove_support; | ||
303 | return 0; | ||
304 | |||
305 | fail: | ||
306 | vgpu_remove_support(g); | ||
307 | return err; | ||
308 | } | ||
309 | |||
310 | int vgpu_pm_prepare_poweroff(struct device *dev) | ||
311 | { | ||
312 | struct gk20a *g = get_gk20a(dev); | ||
313 | int ret = 0; | ||
314 | |||
315 | gk20a_dbg_fn(""); | ||
316 | |||
317 | if (!g->power_on) | ||
318 | return 0; | ||
319 | |||
320 | ret = gk20a_channel_suspend(g); | ||
321 | if (ret) | ||
322 | return ret; | ||
323 | |||
324 | g->power_on = false; | ||
325 | |||
326 | return ret; | ||
327 | } | 201 | } |
328 | 202 | ||
329 | static void vgpu_detect_chip(struct gk20a *g) | 203 | void vgpu_detect_chip(struct gk20a *g) |
330 | { | 204 | { |
331 | struct nvgpu_gpu_params *p = &g->params; | 205 | struct nvgpu_gpu_params *p = &g->params; |
332 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | 206 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); |
@@ -417,7 +291,7 @@ int vgpu_get_timestamps_zipper(struct gk20a *g, | |||
417 | return err; | 291 | return err; |
418 | } | 292 | } |
419 | 293 | ||
420 | static int vgpu_init_hal(struct gk20a *g) | 294 | int vgpu_init_hal(struct gk20a *g) |
421 | { | 295 | { |
422 | u32 ver = g->params.gpu_arch + g->params.gpu_impl; | 296 | u32 ver = g->params.gpu_arch + g->params.gpu_impl; |
423 | int err; | 297 | int err; |
@@ -439,158 +313,7 @@ static int vgpu_init_hal(struct gk20a *g) | |||
439 | return err; | 313 | return err; |
440 | } | 314 | } |
441 | 315 | ||
442 | int vgpu_pm_finalize_poweron(struct device *dev) | 316 | int vgpu_get_constants(struct gk20a *g) |
443 | { | ||
444 | struct gk20a *g = get_gk20a(dev); | ||
445 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
446 | int err; | ||
447 | |||
448 | gk20a_dbg_fn(""); | ||
449 | |||
450 | if (g->power_on) | ||
451 | return 0; | ||
452 | |||
453 | g->power_on = true; | ||
454 | |||
455 | vgpu_detect_chip(g); | ||
456 | err = vgpu_init_hal(g); | ||
457 | if (err) | ||
458 | goto done; | ||
459 | |||
460 | if (g->ops.ltc.init_fs_state) | ||
461 | g->ops.ltc.init_fs_state(g); | ||
462 | |||
463 | err = vgpu_init_mm_support(g); | ||
464 | if (err) { | ||
465 | nvgpu_err(g, "failed to init gk20a mm"); | ||
466 | goto done; | ||
467 | } | ||
468 | |||
469 | err = vgpu_init_fifo_support(g); | ||
470 | if (err) { | ||
471 | nvgpu_err(g, "failed to init gk20a fifo"); | ||
472 | goto done; | ||
473 | } | ||
474 | |||
475 | err = vgpu_init_gr_support(g); | ||
476 | if (err) { | ||
477 | nvgpu_err(g, "failed to init gk20a gr"); | ||
478 | goto done; | ||
479 | } | ||
480 | |||
481 | err = g->ops.chip_init_gpu_characteristics(g); | ||
482 | if (err) { | ||
483 | nvgpu_err(g, "failed to init gk20a gpu characteristics"); | ||
484 | goto done; | ||
485 | } | ||
486 | |||
487 | err = nvgpu_finalize_poweron_linux(l); | ||
488 | if (err) | ||
489 | goto done; | ||
490 | |||
491 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
492 | gk20a_ctxsw_trace_init(g); | ||
493 | #endif | ||
494 | gk20a_sched_ctrl_init(g); | ||
495 | gk20a_channel_resume(g); | ||
496 | |||
497 | g->sw_ready = true; | ||
498 | |||
499 | done: | ||
500 | return err; | ||
501 | } | ||
502 | |||
503 | static int vgpu_qos_notify(struct notifier_block *nb, | ||
504 | unsigned long n, void *data) | ||
505 | { | ||
506 | struct gk20a_scale_profile *profile = | ||
507 | container_of(nb, struct gk20a_scale_profile, | ||
508 | qos_notify_block); | ||
509 | struct gk20a *g = get_gk20a(profile->dev); | ||
510 | u32 max_freq; | ||
511 | int err; | ||
512 | |||
513 | gk20a_dbg_fn(""); | ||
514 | |||
515 | max_freq = (u32)pm_qos_read_max_bound(PM_QOS_GPU_FREQ_BOUNDS); | ||
516 | err = vgpu_clk_cap_rate(profile->dev, max_freq); | ||
517 | if (err) | ||
518 | nvgpu_err(g, "%s failed, err=%d", __func__, err); | ||
519 | |||
520 | return NOTIFY_OK; /* need notify call further */ | ||
521 | } | ||
522 | |||
523 | static int vgpu_pm_qos_init(struct device *dev) | ||
524 | { | ||
525 | struct gk20a *g = get_gk20a(dev); | ||
526 | struct gk20a_scale_profile *profile = g->scale_profile; | ||
527 | |||
528 | if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) { | ||
529 | if (!profile) | ||
530 | return -EINVAL; | ||
531 | } else { | ||
532 | profile = nvgpu_kzalloc(g, sizeof(*profile)); | ||
533 | if (!profile) | ||
534 | return -ENOMEM; | ||
535 | g->scale_profile = profile; | ||
536 | } | ||
537 | |||
538 | profile->dev = dev; | ||
539 | profile->qos_notify_block.notifier_call = vgpu_qos_notify; | ||
540 | pm_qos_add_max_notifier(PM_QOS_GPU_FREQ_BOUNDS, | ||
541 | &profile->qos_notify_block); | ||
542 | return 0; | ||
543 | } | ||
544 | |||
545 | static void vgpu_pm_qos_remove(struct device *dev) | ||
546 | { | ||
547 | struct gk20a *g = get_gk20a(dev); | ||
548 | |||
549 | pm_qos_remove_max_notifier(PM_QOS_GPU_FREQ_BOUNDS, | ||
550 | &g->scale_profile->qos_notify_block); | ||
551 | nvgpu_kfree(g, g->scale_profile); | ||
552 | g->scale_profile = NULL; | ||
553 | } | ||
554 | |||
555 | static int vgpu_pm_init(struct device *dev) | ||
556 | { | ||
557 | struct gk20a *g = get_gk20a(dev); | ||
558 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
559 | unsigned long *freqs; | ||
560 | int num_freqs; | ||
561 | int err = 0; | ||
562 | |||
563 | gk20a_dbg_fn(""); | ||
564 | |||
565 | if (nvgpu_platform_is_simulation(g)) | ||
566 | return 0; | ||
567 | |||
568 | __pm_runtime_disable(dev, false); | ||
569 | |||
570 | if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) | ||
571 | gk20a_scale_init(dev); | ||
572 | |||
573 | if (l->devfreq) { | ||
574 | /* set min/max frequency based on frequency table */ | ||
575 | err = vgpu_clk_get_freqs(dev, &freqs, &num_freqs); | ||
576 | if (err) | ||
577 | return err; | ||
578 | |||
579 | if (num_freqs < 1) | ||
580 | return -EINVAL; | ||
581 | |||
582 | l->devfreq->min_freq = freqs[0]; | ||
583 | l->devfreq->max_freq = freqs[num_freqs - 1]; | ||
584 | } | ||
585 | |||
586 | err = vgpu_pm_qos_init(dev); | ||
587 | if (err) | ||
588 | return err; | ||
589 | |||
590 | return err; | ||
591 | } | ||
592 | |||
593 | static int vgpu_get_constants(struct gk20a *g) | ||
594 | { | 317 | { |
595 | struct tegra_vgpu_cmd_msg msg = {}; | 318 | struct tegra_vgpu_cmd_msg msg = {}; |
596 | struct tegra_vgpu_constants_params *p = &msg.params.constants; | 319 | struct tegra_vgpu_constants_params *p = &msg.params.constants; |
@@ -619,153 +342,3 @@ static int vgpu_get_constants(struct gk20a *g) | |||
619 | priv->constants = *p; | 342 | priv->constants = *p; |
620 | return 0; | 343 | return 0; |
621 | } | 344 | } |
622 | |||
623 | int vgpu_probe(struct platform_device *pdev) | ||
624 | { | ||
625 | struct nvgpu_os_linux *l; | ||
626 | struct gk20a *gk20a; | ||
627 | int err; | ||
628 | struct device *dev = &pdev->dev; | ||
629 | struct gk20a_platform *platform = gk20a_get_platform(dev); | ||
630 | struct vgpu_priv_data *priv; | ||
631 | |||
632 | if (!platform) { | ||
633 | dev_err(dev, "no platform data\n"); | ||
634 | return -ENODATA; | ||
635 | } | ||
636 | |||
637 | gk20a_dbg_fn(""); | ||
638 | |||
639 | l = kzalloc(sizeof(*l), GFP_KERNEL); | ||
640 | if (!l) { | ||
641 | dev_err(dev, "couldn't allocate gk20a support"); | ||
642 | return -ENOMEM; | ||
643 | } | ||
644 | gk20a = &l->g; | ||
645 | nvgpu_init_gk20a(gk20a); | ||
646 | |||
647 | nvgpu_kmem_init(gk20a); | ||
648 | |||
649 | err = nvgpu_init_enabled_flags(gk20a); | ||
650 | if (err) { | ||
651 | kfree(gk20a); | ||
652 | return err; | ||
653 | } | ||
654 | |||
655 | l->dev = dev; | ||
656 | if (tegra_platform_is_vdk()) | ||
657 | __nvgpu_set_enabled(gk20a, NVGPU_IS_FMODEL, true); | ||
658 | |||
659 | gk20a->is_virtual = true; | ||
660 | |||
661 | priv = nvgpu_kzalloc(gk20a, sizeof(*priv)); | ||
662 | if (!priv) { | ||
663 | kfree(gk20a); | ||
664 | return -ENOMEM; | ||
665 | } | ||
666 | |||
667 | platform->g = gk20a; | ||
668 | platform->vgpu_priv = priv; | ||
669 | |||
670 | err = gk20a_user_init(dev, INTERFACE_NAME, &nvgpu_class); | ||
671 | if (err) | ||
672 | return err; | ||
673 | |||
674 | vgpu_init_support(pdev); | ||
675 | |||
676 | vgpu_init_vars(gk20a, platform); | ||
677 | |||
678 | init_rwsem(&l->busy_lock); | ||
679 | |||
680 | nvgpu_spinlock_init(&gk20a->mc_enable_lock); | ||
681 | |||
682 | gk20a->ch_wdt_timeout_ms = platform->ch_wdt_timeout_ms; | ||
683 | |||
684 | /* Initialize the platform interface. */ | ||
685 | err = platform->probe(dev); | ||
686 | if (err) { | ||
687 | if (err == -EPROBE_DEFER) | ||
688 | nvgpu_info(gk20a, "platform probe failed"); | ||
689 | else | ||
690 | nvgpu_err(gk20a, "platform probe failed"); | ||
691 | return err; | ||
692 | } | ||
693 | |||
694 | if (platform->late_probe) { | ||
695 | err = platform->late_probe(dev); | ||
696 | if (err) { | ||
697 | nvgpu_err(gk20a, "late probe failed"); | ||
698 | return err; | ||
699 | } | ||
700 | } | ||
701 | |||
702 | err = vgpu_comm_init(gk20a); | ||
703 | if (err) { | ||
704 | nvgpu_err(gk20a, "failed to init comm interface"); | ||
705 | return -ENOSYS; | ||
706 | } | ||
707 | |||
708 | priv->virt_handle = vgpu_connect(); | ||
709 | if (!priv->virt_handle) { | ||
710 | nvgpu_err(gk20a, "failed to connect to server node"); | ||
711 | vgpu_comm_deinit(); | ||
712 | return -ENOSYS; | ||
713 | } | ||
714 | |||
715 | err = vgpu_get_constants(gk20a); | ||
716 | if (err) { | ||
717 | vgpu_comm_deinit(); | ||
718 | return err; | ||
719 | } | ||
720 | |||
721 | err = vgpu_pm_init(dev); | ||
722 | if (err) { | ||
723 | nvgpu_err(gk20a, "pm init failed"); | ||
724 | return err; | ||
725 | } | ||
726 | |||
727 | err = nvgpu_thread_create(&priv->intr_handler, gk20a, | ||
728 | vgpu_intr_thread, "gk20a"); | ||
729 | if (err) | ||
730 | return err; | ||
731 | |||
732 | gk20a_debug_init(gk20a, "gpu.0"); | ||
733 | |||
734 | /* Set DMA parameters to allow larger sgt lists */ | ||
735 | dev->dma_parms = &l->dma_parms; | ||
736 | dma_set_max_seg_size(dev, UINT_MAX); | ||
737 | |||
738 | gk20a->gr_idle_timeout_default = NVGPU_DEFAULT_GR_IDLE_TIMEOUT; | ||
739 | gk20a->timeouts_enabled = true; | ||
740 | |||
741 | vgpu_create_sysfs(dev); | ||
742 | gk20a_init_gr(gk20a); | ||
743 | |||
744 | gk20a_dbg_info("total ram pages : %lu", totalram_pages); | ||
745 | gk20a->gr.max_comptag_mem = totalram_pages | ||
746 | >> (10 - (PAGE_SHIFT - 10)); | ||
747 | |||
748 | nvgpu_ref_init(&gk20a->refcount); | ||
749 | |||
750 | return 0; | ||
751 | } | ||
752 | |||
753 | int vgpu_remove(struct platform_device *pdev) | ||
754 | { | ||
755 | struct device *dev = &pdev->dev; | ||
756 | struct gk20a *g = get_gk20a(dev); | ||
757 | gk20a_dbg_fn(""); | ||
758 | |||
759 | vgpu_pm_qos_remove(dev); | ||
760 | if (g->remove_support) | ||
761 | g->remove_support(g); | ||
762 | |||
763 | vgpu_comm_deinit(); | ||
764 | gk20a_sched_ctrl_cleanup(g); | ||
765 | gk20a_user_deinit(dev, &nvgpu_class); | ||
766 | vgpu_remove_sysfs(dev); | ||
767 | gk20a_get_platform(dev)->g = NULL; | ||
768 | gk20a_put(g); | ||
769 | |||
770 | return 0; | ||
771 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h index eafe503c..66d993fc 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h +++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h | |||
@@ -1,6 +1,4 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU Interfaces | ||
3 | * | ||
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 3 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
@@ -16,24 +14,23 @@ | |||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
17 | */ | 15 | */ |
18 | 16 | ||
19 | #ifndef _VIRT_H_ | 17 | #ifndef __VGPU_COMMON_H__ |
20 | #define _VIRT_H_ | 18 | #define __VGPU_COMMON_H__ |
19 | |||
20 | #include <nvgpu/types.h> | ||
21 | #include <nvgpu/thread.h> | ||
22 | #include <nvgpu/log.h> | ||
23 | #include <nvgpu/vgpu/tegra_vgpu.h> | ||
21 | 24 | ||
22 | struct device; | 25 | struct device; |
23 | struct tegra_vgpu_gr_intr_info; | 26 | struct tegra_vgpu_gr_intr_info; |
24 | struct tegra_vgpu_fifo_intr_info; | 27 | struct tegra_vgpu_fifo_intr_info; |
25 | struct tegra_vgpu_cmd_msg; | 28 | struct tegra_vgpu_cmd_msg; |
26 | struct gk20a_platform; | ||
27 | struct nvgpu_mem; | 29 | struct nvgpu_mem; |
28 | 30 | struct gk20a; | |
29 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | 31 | struct vm_gk20a; |
30 | #include <nvgpu/vgpu/vgpu_ivc.h> | 32 | struct nvgpu_gr_ctx; |
31 | #include <nvgpu/vgpu/tegra_vgpu.h> | 33 | struct nvgpu_cpu_time_correlation_sample; |
32 | #include <nvgpu/thread.h> | ||
33 | |||
34 | #include "gk20a/gk20a.h" | ||
35 | #include "common/linux/platform_gk20a.h" | ||
36 | #include "common/linux/os_linux.h" | ||
37 | 34 | ||
38 | struct vgpu_priv_data { | 35 | struct vgpu_priv_data { |
39 | u64 virt_handle; | 36 | u64 virt_handle; |
@@ -41,18 +38,7 @@ struct vgpu_priv_data { | |||
41 | struct tegra_vgpu_constants_params constants; | 38 | struct tegra_vgpu_constants_params constants; |
42 | }; | 39 | }; |
43 | 40 | ||
44 | static inline | 41 | struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g); |
45 | struct vgpu_priv_data *vgpu_get_priv_data_from_dev(struct device *dev) | ||
46 | { | ||
47 | struct gk20a_platform *plat = gk20a_get_platform(dev); | ||
48 | |||
49 | return (struct vgpu_priv_data *)plat->vgpu_priv; | ||
50 | } | ||
51 | |||
52 | static inline struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g) | ||
53 | { | ||
54 | return vgpu_get_priv_data_from_dev(dev_from_gk20a(g)); | ||
55 | } | ||
56 | 42 | ||
57 | static inline u64 vgpu_get_handle(struct gk20a *g) | 43 | static inline u64 vgpu_get_handle(struct gk20a *g) |
58 | { | 44 | { |
@@ -66,10 +52,22 @@ static inline u64 vgpu_get_handle(struct gk20a *g) | |||
66 | return priv->virt_handle; | 52 | return priv->virt_handle; |
67 | } | 53 | } |
68 | 54 | ||
69 | int vgpu_pm_prepare_poweroff(struct device *dev); | 55 | int vgpu_comm_init(struct gk20a *g); |
70 | int vgpu_pm_finalize_poweron(struct device *dev); | 56 | void vgpu_comm_deinit(void); |
71 | int vgpu_probe(struct platform_device *dev); | 57 | int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, |
72 | int vgpu_remove(struct platform_device *dev); | 58 | size_t size_out); |
59 | u64 vgpu_connect(void); | ||
60 | int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value); | ||
61 | int vgpu_intr_thread(void *dev_id); | ||
62 | void vgpu_remove_support_common(struct gk20a *g); | ||
63 | void vgpu_detect_chip(struct gk20a *g); | ||
64 | int vgpu_init_gpu_characteristics(struct gk20a *g); | ||
65 | int vgpu_read_ptimer(struct gk20a *g, u64 *value); | ||
66 | int vgpu_get_timestamps_zipper(struct gk20a *g, | ||
67 | u32 source_id, u32 count, | ||
68 | struct nvgpu_cpu_time_correlation_sample *samples); | ||
69 | int vgpu_init_hal(struct gk20a *g); | ||
70 | int vgpu_get_constants(struct gk20a *g); | ||
73 | u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem); | 71 | u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem); |
74 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); | 72 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); |
75 | int vgpu_gr_nonstall_isr(struct gk20a *g, | 73 | int vgpu_gr_nonstall_isr(struct gk20a *g, |
@@ -94,90 +92,12 @@ int vgpu_init_mm_support(struct gk20a *g); | |||
94 | int vgpu_init_gr_support(struct gk20a *g); | 92 | int vgpu_init_gr_support(struct gk20a *g); |
95 | int vgpu_init_fifo_support(struct gk20a *g); | 93 | int vgpu_init_fifo_support(struct gk20a *g); |
96 | 94 | ||
97 | int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value); | ||
98 | int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, | ||
99 | size_t size_out); | ||
100 | |||
101 | int vgpu_gp10b_init_hal(struct gk20a *g); | 95 | int vgpu_gp10b_init_hal(struct gk20a *g); |
102 | int vgpu_gv11b_init_hal(struct gk20a *g); | 96 | int vgpu_gv11b_init_hal(struct gk20a *g); |
103 | 97 | ||
104 | int vgpu_init_gpu_characteristics(struct gk20a *g); | ||
105 | |||
106 | void vgpu_create_sysfs(struct device *dev); | ||
107 | void vgpu_remove_sysfs(struct device *dev); | ||
108 | int vgpu_read_ptimer(struct gk20a *g, u64 *value); | 98 | int vgpu_read_ptimer(struct gk20a *g, u64 *value); |
109 | int vgpu_get_timestamps_zipper(struct gk20a *g, | 99 | int vgpu_get_timestamps_zipper(struct gk20a *g, |
110 | u32 source_id, u32 count, | 100 | u32 source_id, u32 count, |
111 | struct nvgpu_cpu_time_correlation_sample *samples); | 101 | struct nvgpu_cpu_time_correlation_sample *samples); |
112 | #else | ||
113 | static inline int vgpu_pm_prepare_poweroff(struct device *dev) | ||
114 | { | ||
115 | return -ENOSYS; | ||
116 | } | ||
117 | static inline int vgpu_pm_finalize_poweron(struct device *dev) | ||
118 | { | ||
119 | return -ENOSYS; | ||
120 | } | ||
121 | static inline int vgpu_probe(struct platform_device *dev) | ||
122 | { | ||
123 | return -ENOSYS; | ||
124 | } | ||
125 | static inline int vgpu_remove(struct platform_device *dev) | ||
126 | { | ||
127 | return -ENOSYS; | ||
128 | } | ||
129 | static inline u64 vgpu_bar1_map(struct gk20a *g, struct nvgpu_mem *mem) | ||
130 | { | ||
131 | return 0; | ||
132 | } | ||
133 | static inline int vgpu_gr_isr(struct gk20a *g, | ||
134 | struct tegra_vgpu_gr_intr_info *info) | ||
135 | { | ||
136 | return 0; | ||
137 | } | ||
138 | static inline int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | ||
139 | struct nvgpu_gr_ctx *gr_ctx, | ||
140 | struct vm_gk20a *vm, | ||
141 | u32 class, | ||
142 | u32 flags) | ||
143 | { | ||
144 | return -ENOSYS; | ||
145 | } | ||
146 | static inline void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | ||
147 | struct nvgpu_gr_ctx *gr_ctx) | ||
148 | { | ||
149 | } | ||
150 | static inline int vgpu_gr_init_ctx_state(struct gk20a *g) | ||
151 | { | ||
152 | return -ENOSYS; | ||
153 | } | ||
154 | static inline int vgpu_fifo_isr(struct gk20a *g, | ||
155 | struct tegra_vgpu_fifo_intr_info *info) | ||
156 | { | ||
157 | return 0; | ||
158 | } | ||
159 | static inline int vgpu_init_mm_support(struct gk20a *g) | ||
160 | { | ||
161 | return -ENOSYS; | ||
162 | } | ||
163 | static inline int vgpu_init_gr_support(struct gk20a *g) | ||
164 | { | ||
165 | return -ENOSYS; | ||
166 | } | ||
167 | static inline int vgpu_init_fifo_support(struct gk20a *g) | ||
168 | { | ||
169 | return -ENOSYS; | ||
170 | } | ||
171 | |||
172 | static inline int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value) | ||
173 | { | ||
174 | return -ENOSYS; | ||
175 | } | ||
176 | static inline int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, | ||
177 | size_t size_out) | ||
178 | { | ||
179 | return -ENOSYS; | ||
180 | } | ||
181 | #endif | ||
182 | 102 | ||
183 | #endif | 103 | #endif |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.c b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.c new file mode 100644 index 00000000..69bf22ee --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.c | |||
@@ -0,0 +1,463 @@ | |||
1 | /* | ||
2 | * Virtualized GPU for Linux | ||
3 | * | ||
4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include <linux/mm.h> | ||
20 | #include <linux/dma-mapping.h> | ||
21 | #include <linux/pm_runtime.h> | ||
22 | #include <linux/pm_qos.h> | ||
23 | #include <linux/platform_device.h> | ||
24 | #include <soc/tegra/chip-id.h> | ||
25 | #include <uapi/linux/nvgpu.h> | ||
26 | |||
27 | #include <nvgpu/kmem.h> | ||
28 | #include <nvgpu/bug.h> | ||
29 | #include <nvgpu/enabled.h> | ||
30 | #include <nvgpu/debug.h> | ||
31 | #include <nvgpu/bus.h> | ||
32 | #include <nvgpu/soc.h> | ||
33 | #include <nvgpu/ctxsw_trace.h> | ||
34 | #include <nvgpu/defaults.h> | ||
35 | |||
36 | #include "vgpu.h" | ||
37 | #include "vgpu_linux.h" | ||
38 | #include "fecs_trace_vgpu.h" | ||
39 | #include "clk_vgpu.h" | ||
40 | #include "gk20a/tsg_gk20a.h" | ||
41 | #include "gk20a/channel_gk20a.h" | ||
42 | #include "gk20a/regops_gk20a.h" | ||
43 | #include "gm20b/hal_gm20b.h" | ||
44 | |||
45 | #include "common/linux/module.h" | ||
46 | #include "common/linux/os_linux.h" | ||
47 | #include "common/linux/ioctl.h" | ||
48 | #include "common/linux/scale.h" | ||
49 | #include "common/linux/driver_common.h" | ||
50 | #include "common/linux/platform_gk20a.h" | ||
51 | |||
52 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
53 | |||
54 | struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g) | ||
55 | { | ||
56 | struct gk20a_platform *plat = gk20a_get_platform(dev_from_gk20a(g)); | ||
57 | |||
58 | return (struct vgpu_priv_data *)plat->vgpu_priv; | ||
59 | } | ||
60 | |||
61 | static void vgpu_remove_support(struct gk20a *g) | ||
62 | { | ||
63 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
64 | |||
65 | vgpu_remove_support_common(g); | ||
66 | |||
67 | /* free mappings to registers, etc*/ | ||
68 | |||
69 | if (l->bar1) { | ||
70 | iounmap(l->bar1); | ||
71 | l->bar1 = NULL; | ||
72 | } | ||
73 | } | ||
74 | |||
75 | static void vgpu_init_vars(struct gk20a *g, struct gk20a_platform *platform) | ||
76 | { | ||
77 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
78 | |||
79 | nvgpu_mutex_init(&g->poweron_lock); | ||
80 | nvgpu_mutex_init(&g->poweroff_lock); | ||
81 | l->regs_saved = l->regs; | ||
82 | l->bar1_saved = l->bar1; | ||
83 | |||
84 | nvgpu_init_list_node(&g->pending_sema_waits); | ||
85 | nvgpu_raw_spinlock_init(&g->pending_sema_waits_lock); | ||
86 | |||
87 | g->aggressive_sync_destroy = platform->aggressive_sync_destroy; | ||
88 | g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh; | ||
89 | g->has_syncpoints = platform->has_syncpoints; | ||
90 | g->ptimer_src_freq = platform->ptimer_src_freq; | ||
91 | g->can_railgate = platform->can_railgate_init; | ||
92 | g->railgate_delay = platform->railgate_delay_init; | ||
93 | |||
94 | __nvgpu_set_enabled(g, NVGPU_MM_UNIFY_ADDRESS_SPACES, | ||
95 | platform->unify_address_spaces); | ||
96 | } | ||
97 | |||
98 | static int vgpu_init_support(struct platform_device *pdev) | ||
99 | { | ||
100 | struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
101 | struct gk20a *g = get_gk20a(&pdev->dev); | ||
102 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
103 | void __iomem *regs; | ||
104 | int err = 0; | ||
105 | |||
106 | if (!r) { | ||
107 | nvgpu_err(g, "failed to get gk20a bar1"); | ||
108 | err = -ENXIO; | ||
109 | goto fail; | ||
110 | } | ||
111 | |||
112 | if (r->name && !strcmp(r->name, "/vgpu")) { | ||
113 | regs = devm_ioremap_resource(&pdev->dev, r); | ||
114 | if (IS_ERR(regs)) { | ||
115 | nvgpu_err(g, "failed to remap gk20a bar1"); | ||
116 | err = PTR_ERR(regs); | ||
117 | goto fail; | ||
118 | } | ||
119 | l->bar1 = regs; | ||
120 | l->bar1_mem = r; | ||
121 | } | ||
122 | |||
123 | nvgpu_mutex_init(&g->dbg_sessions_lock); | ||
124 | nvgpu_mutex_init(&g->client_lock); | ||
125 | |||
126 | nvgpu_init_list_node(&g->profiler_objects); | ||
127 | |||
128 | g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K); | ||
129 | if (!g->dbg_regops_tmp_buf) { | ||
130 | nvgpu_err(g, "couldn't allocate regops tmp buf"); | ||
131 | return -ENOMEM; | ||
132 | } | ||
133 | g->dbg_regops_tmp_buf_ops = | ||
134 | SZ_4K / sizeof(g->dbg_regops_tmp_buf[0]); | ||
135 | |||
136 | g->remove_support = vgpu_remove_support; | ||
137 | return 0; | ||
138 | |||
139 | fail: | ||
140 | vgpu_remove_support(g); | ||
141 | return err; | ||
142 | } | ||
143 | |||
144 | int vgpu_pm_prepare_poweroff(struct device *dev) | ||
145 | { | ||
146 | struct gk20a *g = get_gk20a(dev); | ||
147 | int ret = 0; | ||
148 | |||
149 | gk20a_dbg_fn(""); | ||
150 | |||
151 | if (!g->power_on) | ||
152 | return 0; | ||
153 | |||
154 | ret = gk20a_channel_suspend(g); | ||
155 | if (ret) | ||
156 | return ret; | ||
157 | |||
158 | g->power_on = false; | ||
159 | |||
160 | return ret; | ||
161 | } | ||
162 | |||
163 | int vgpu_pm_finalize_poweron(struct device *dev) | ||
164 | { | ||
165 | struct gk20a *g = get_gk20a(dev); | ||
166 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
167 | int err; | ||
168 | |||
169 | gk20a_dbg_fn(""); | ||
170 | |||
171 | if (g->power_on) | ||
172 | return 0; | ||
173 | |||
174 | g->power_on = true; | ||
175 | |||
176 | vgpu_detect_chip(g); | ||
177 | err = vgpu_init_hal(g); | ||
178 | if (err) | ||
179 | goto done; | ||
180 | |||
181 | if (g->ops.ltc.init_fs_state) | ||
182 | g->ops.ltc.init_fs_state(g); | ||
183 | |||
184 | err = vgpu_init_mm_support(g); | ||
185 | if (err) { | ||
186 | nvgpu_err(g, "failed to init gk20a mm"); | ||
187 | goto done; | ||
188 | } | ||
189 | |||
190 | err = vgpu_init_fifo_support(g); | ||
191 | if (err) { | ||
192 | nvgpu_err(g, "failed to init gk20a fifo"); | ||
193 | goto done; | ||
194 | } | ||
195 | |||
196 | err = vgpu_init_gr_support(g); | ||
197 | if (err) { | ||
198 | nvgpu_err(g, "failed to init gk20a gr"); | ||
199 | goto done; | ||
200 | } | ||
201 | |||
202 | err = g->ops.chip_init_gpu_characteristics(g); | ||
203 | if (err) { | ||
204 | nvgpu_err(g, "failed to init gk20a gpu characteristics"); | ||
205 | goto done; | ||
206 | } | ||
207 | |||
208 | err = nvgpu_finalize_poweron_linux(l); | ||
209 | if (err) | ||
210 | goto done; | ||
211 | |||
212 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
213 | gk20a_ctxsw_trace_init(g); | ||
214 | #endif | ||
215 | gk20a_sched_ctrl_init(g); | ||
216 | gk20a_channel_resume(g); | ||
217 | |||
218 | g->sw_ready = true; | ||
219 | |||
220 | done: | ||
221 | return err; | ||
222 | } | ||
223 | |||
224 | static int vgpu_qos_notify(struct notifier_block *nb, | ||
225 | unsigned long n, void *data) | ||
226 | { | ||
227 | struct gk20a_scale_profile *profile = | ||
228 | container_of(nb, struct gk20a_scale_profile, | ||
229 | qos_notify_block); | ||
230 | struct gk20a *g = get_gk20a(profile->dev); | ||
231 | u32 max_freq; | ||
232 | int err; | ||
233 | |||
234 | gk20a_dbg_fn(""); | ||
235 | |||
236 | max_freq = (u32)pm_qos_read_max_bound(PM_QOS_GPU_FREQ_BOUNDS); | ||
237 | err = vgpu_clk_cap_rate(profile->dev, max_freq); | ||
238 | if (err) | ||
239 | nvgpu_err(g, "%s failed, err=%d", __func__, err); | ||
240 | |||
241 | return NOTIFY_OK; /* need notify call further */ | ||
242 | } | ||
243 | |||
244 | static int vgpu_pm_qos_init(struct device *dev) | ||
245 | { | ||
246 | struct gk20a *g = get_gk20a(dev); | ||
247 | struct gk20a_scale_profile *profile = g->scale_profile; | ||
248 | |||
249 | if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) { | ||
250 | if (!profile) | ||
251 | return -EINVAL; | ||
252 | } else { | ||
253 | profile = nvgpu_kzalloc(g, sizeof(*profile)); | ||
254 | if (!profile) | ||
255 | return -ENOMEM; | ||
256 | g->scale_profile = profile; | ||
257 | } | ||
258 | |||
259 | profile->dev = dev; | ||
260 | profile->qos_notify_block.notifier_call = vgpu_qos_notify; | ||
261 | pm_qos_add_max_notifier(PM_QOS_GPU_FREQ_BOUNDS, | ||
262 | &profile->qos_notify_block); | ||
263 | return 0; | ||
264 | } | ||
265 | |||
266 | static void vgpu_pm_qos_remove(struct device *dev) | ||
267 | { | ||
268 | struct gk20a *g = get_gk20a(dev); | ||
269 | |||
270 | pm_qos_remove_max_notifier(PM_QOS_GPU_FREQ_BOUNDS, | ||
271 | &g->scale_profile->qos_notify_block); | ||
272 | nvgpu_kfree(g, g->scale_profile); | ||
273 | g->scale_profile = NULL; | ||
274 | } | ||
275 | |||
276 | static int vgpu_pm_init(struct device *dev) | ||
277 | { | ||
278 | struct gk20a *g = get_gk20a(dev); | ||
279 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
280 | unsigned long *freqs; | ||
281 | int num_freqs; | ||
282 | int err = 0; | ||
283 | |||
284 | gk20a_dbg_fn(""); | ||
285 | |||
286 | if (nvgpu_platform_is_simulation(g)) | ||
287 | return 0; | ||
288 | |||
289 | __pm_runtime_disable(dev, false); | ||
290 | |||
291 | if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) | ||
292 | gk20a_scale_init(dev); | ||
293 | |||
294 | if (l->devfreq) { | ||
295 | /* set min/max frequency based on frequency table */ | ||
296 | err = vgpu_clk_get_freqs(dev, &freqs, &num_freqs); | ||
297 | if (err) | ||
298 | return err; | ||
299 | |||
300 | if (num_freqs < 1) | ||
301 | return -EINVAL; | ||
302 | |||
303 | l->devfreq->min_freq = freqs[0]; | ||
304 | l->devfreq->max_freq = freqs[num_freqs - 1]; | ||
305 | } | ||
306 | |||
307 | err = vgpu_pm_qos_init(dev); | ||
308 | if (err) | ||
309 | return err; | ||
310 | |||
311 | return err; | ||
312 | } | ||
313 | |||
314 | int vgpu_probe(struct platform_device *pdev) | ||
315 | { | ||
316 | struct nvgpu_os_linux *l; | ||
317 | struct gk20a *gk20a; | ||
318 | int err; | ||
319 | struct device *dev = &pdev->dev; | ||
320 | struct gk20a_platform *platform = gk20a_get_platform(dev); | ||
321 | struct vgpu_priv_data *priv; | ||
322 | |||
323 | if (!platform) { | ||
324 | dev_err(dev, "no platform data\n"); | ||
325 | return -ENODATA; | ||
326 | } | ||
327 | |||
328 | gk20a_dbg_fn(""); | ||
329 | |||
330 | l = kzalloc(sizeof(*l), GFP_KERNEL); | ||
331 | if (!l) { | ||
332 | dev_err(dev, "couldn't allocate gk20a support"); | ||
333 | return -ENOMEM; | ||
334 | } | ||
335 | gk20a = &l->g; | ||
336 | nvgpu_init_gk20a(gk20a); | ||
337 | |||
338 | nvgpu_kmem_init(gk20a); | ||
339 | |||
340 | err = nvgpu_init_enabled_flags(gk20a); | ||
341 | if (err) { | ||
342 | kfree(gk20a); | ||
343 | return err; | ||
344 | } | ||
345 | |||
346 | l->dev = dev; | ||
347 | if (tegra_platform_is_vdk()) | ||
348 | __nvgpu_set_enabled(gk20a, NVGPU_IS_FMODEL, true); | ||
349 | |||
350 | gk20a->is_virtual = true; | ||
351 | |||
352 | priv = nvgpu_kzalloc(gk20a, sizeof(*priv)); | ||
353 | if (!priv) { | ||
354 | kfree(gk20a); | ||
355 | return -ENOMEM; | ||
356 | } | ||
357 | |||
358 | platform->g = gk20a; | ||
359 | platform->vgpu_priv = priv; | ||
360 | |||
361 | err = gk20a_user_init(dev, INTERFACE_NAME, &nvgpu_class); | ||
362 | if (err) | ||
363 | return err; | ||
364 | |||
365 | vgpu_init_support(pdev); | ||
366 | |||
367 | vgpu_init_vars(gk20a, platform); | ||
368 | |||
369 | init_rwsem(&l->busy_lock); | ||
370 | |||
371 | nvgpu_spinlock_init(&gk20a->mc_enable_lock); | ||
372 | |||
373 | gk20a->ch_wdt_timeout_ms = platform->ch_wdt_timeout_ms; | ||
374 | |||
375 | /* Initialize the platform interface. */ | ||
376 | err = platform->probe(dev); | ||
377 | if (err) { | ||
378 | if (err == -EPROBE_DEFER) | ||
379 | nvgpu_info(gk20a, "platform probe failed"); | ||
380 | else | ||
381 | nvgpu_err(gk20a, "platform probe failed"); | ||
382 | return err; | ||
383 | } | ||
384 | |||
385 | if (platform->late_probe) { | ||
386 | err = platform->late_probe(dev); | ||
387 | if (err) { | ||
388 | nvgpu_err(gk20a, "late probe failed"); | ||
389 | return err; | ||
390 | } | ||
391 | } | ||
392 | |||
393 | err = vgpu_comm_init(gk20a); | ||
394 | if (err) { | ||
395 | nvgpu_err(gk20a, "failed to init comm interface"); | ||
396 | return -ENOSYS; | ||
397 | } | ||
398 | |||
399 | priv->virt_handle = vgpu_connect(); | ||
400 | if (!priv->virt_handle) { | ||
401 | nvgpu_err(gk20a, "failed to connect to server node"); | ||
402 | vgpu_comm_deinit(); | ||
403 | return -ENOSYS; | ||
404 | } | ||
405 | |||
406 | err = vgpu_get_constants(gk20a); | ||
407 | if (err) { | ||
408 | vgpu_comm_deinit(); | ||
409 | return err; | ||
410 | } | ||
411 | |||
412 | err = vgpu_pm_init(dev); | ||
413 | if (err) { | ||
414 | nvgpu_err(gk20a, "pm init failed"); | ||
415 | return err; | ||
416 | } | ||
417 | |||
418 | err = nvgpu_thread_create(&priv->intr_handler, gk20a, | ||
419 | vgpu_intr_thread, "gk20a"); | ||
420 | if (err) | ||
421 | return err; | ||
422 | |||
423 | gk20a_debug_init(gk20a, "gpu.0"); | ||
424 | |||
425 | /* Set DMA parameters to allow larger sgt lists */ | ||
426 | dev->dma_parms = &l->dma_parms; | ||
427 | dma_set_max_seg_size(dev, UINT_MAX); | ||
428 | |||
429 | gk20a->gr_idle_timeout_default = NVGPU_DEFAULT_GR_IDLE_TIMEOUT; | ||
430 | gk20a->timeouts_enabled = true; | ||
431 | |||
432 | vgpu_create_sysfs(dev); | ||
433 | gk20a_init_gr(gk20a); | ||
434 | |||
435 | gk20a_dbg_info("total ram pages : %lu", totalram_pages); | ||
436 | gk20a->gr.max_comptag_mem = totalram_pages | ||
437 | >> (10 - (PAGE_SHIFT - 10)); | ||
438 | |||
439 | nvgpu_ref_init(&gk20a->refcount); | ||
440 | |||
441 | return 0; | ||
442 | } | ||
443 | |||
444 | int vgpu_remove(struct platform_device *pdev) | ||
445 | { | ||
446 | struct device *dev = &pdev->dev; | ||
447 | struct gk20a *g = get_gk20a(dev); | ||
448 | |||
449 | gk20a_dbg_fn(""); | ||
450 | |||
451 | vgpu_pm_qos_remove(dev); | ||
452 | if (g->remove_support) | ||
453 | g->remove_support(g); | ||
454 | |||
455 | vgpu_comm_deinit(); | ||
456 | gk20a_sched_ctrl_cleanup(g); | ||
457 | gk20a_user_deinit(dev, &nvgpu_class); | ||
458 | vgpu_remove_sysfs(dev); | ||
459 | gk20a_get_platform(dev)->g = NULL; | ||
460 | gk20a_put(g); | ||
461 | |||
462 | return 0; | ||
463 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.h b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.h new file mode 100644 index 00000000..8fcc121f --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_linux.h | |||
@@ -0,0 +1,57 @@ | |||
1 | /* | ||
2 | * Virtualized GPU Linux Interfaces | ||
3 | * | ||
4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #ifndef __VGPU_LINUX_H__ | ||
20 | #define __VGPU_LINUX_H__ | ||
21 | |||
22 | struct device; | ||
23 | struct platform_device; | ||
24 | |||
25 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | ||
26 | |||
27 | #include "vgpu.h" | ||
28 | |||
29 | int vgpu_pm_prepare_poweroff(struct device *dev); | ||
30 | int vgpu_pm_finalize_poweron(struct device *dev); | ||
31 | int vgpu_probe(struct platform_device *dev); | ||
32 | int vgpu_remove(struct platform_device *dev); | ||
33 | |||
34 | void vgpu_create_sysfs(struct device *dev); | ||
35 | void vgpu_remove_sysfs(struct device *dev); | ||
36 | #else | ||
37 | /* define placeholders for functions used outside of vgpu */ | ||
38 | |||
39 | static inline int vgpu_pm_prepare_poweroff(struct device *dev) | ||
40 | { | ||
41 | return -ENOSYS; | ||
42 | } | ||
43 | static inline int vgpu_pm_finalize_poweron(struct device *dev) | ||
44 | { | ||
45 | return -ENOSYS; | ||
46 | } | ||
47 | static inline int vgpu_probe(struct platform_device *dev) | ||
48 | { | ||
49 | return -ENOSYS; | ||
50 | } | ||
51 | static inline int vgpu_remove(struct platform_device *dev) | ||
52 | { | ||
53 | return -ENOSYS; | ||
54 | } | ||
55 | #endif | ||
56 | |||
57 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index fa0a4c2d..5c638a8d 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -28,6 +28,7 @@ | |||
28 | #include "mm_gk20a.h" | 28 | #include "mm_gk20a.h" |
29 | 29 | ||
30 | #include <nvgpu/comptags.h> | 30 | #include <nvgpu/comptags.h> |
31 | #include <nvgpu/cond.h> | ||
31 | 32 | ||
32 | #define GR_IDLE_CHECK_DEFAULT 10 /* usec */ | 33 | #define GR_IDLE_CHECK_DEFAULT 10 /* usec */ |
33 | #define GR_IDLE_CHECK_MAX 200 /* usec */ | 34 | #define GR_IDLE_CHECK_MAX 200 /* usec */ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index ae32a406..882dd342 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | |||
@@ -687,6 +687,7 @@ struct tegra_vgpu_fecs_trace_event_info { | |||
687 | u32 type; | 687 | u32 type; |
688 | }; | 688 | }; |
689 | 689 | ||
690 | #define TEGRA_VGPU_CHANNEL_EVENT_ID_MAX 6 | ||
690 | struct tegra_vgpu_channel_event_info { | 691 | struct tegra_vgpu_channel_event_info { |
691 | u32 event_id; | 692 | u32 event_id; |
692 | u32 is_tsg; | 693 | u32 is_tsg; |