diff options
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/falcon.h | 2 |
5 files changed, 15 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index a22350ce..9427d3bf 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -621,9 +621,9 @@ static const struct gpu_ops gp106_ops = { | |||
621 | .alloc_blob_space = gp106_alloc_blob_space, | 621 | .alloc_blob_space = gp106_alloc_blob_space, |
622 | .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, | 622 | .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, |
623 | .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, | 623 | .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, |
624 | .falcon_wait_for_halt = sec2_wait_for_halt, | 624 | .falcon_wait_for_halt = gp106_sec2_wait_for_halt, |
625 | .falcon_clear_halt_interrupt_status = | 625 | .falcon_clear_halt_interrupt_status = |
626 | sec2_clear_halt_interrupt_status, | 626 | gp106_sec2_clear_halt_interrupt_status, |
627 | .init_falcon_setup_hw = init_sec2_setup_hw1, | 627 | .init_falcon_setup_hw = init_sec2_setup_hw1, |
628 | .pmu_queue_tail = gk20a_pmu_queue_tail, | 628 | .pmu_queue_tail = gk20a_pmu_queue_tail, |
629 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | 629 | .pmu_get_queue_head = pwr_pmu_queue_head_r, |
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 1c959022..d480d875 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -34,7 +34,8 @@ | |||
34 | #define gm20b_dbg_pmu(g, fmt, arg...) \ | 34 | #define gm20b_dbg_pmu(g, fmt, arg...) \ |
35 | nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) | 35 | nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) |
36 | 36 | ||
37 | int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout) | 37 | int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g, |
38 | unsigned int timeout) | ||
38 | { | 39 | { |
39 | int status = 0; | 40 | int status = 0; |
40 | 41 | ||
@@ -44,7 +45,7 @@ int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout) | |||
44 | return status; | 45 | return status; |
45 | } | 46 | } |
46 | 47 | ||
47 | int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) | 48 | int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) |
48 | { | 49 | { |
49 | u32 data = 0; | 50 | u32 data = 0; |
50 | int completion = 0; | 51 | int completion = 0; |
@@ -55,9 +56,10 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) | |||
55 | goto exit; | 56 | goto exit; |
56 | } | 57 | } |
57 | 58 | ||
58 | g->acr.capabilities = gk20a_readl(g, psec_falcon_mailbox1_r()); | 59 | g->acr.capabilities = nvgpu_flcn_mailbox_read(&g->sec2_flcn, |
60 | FALCON_MAILBOX_1); | ||
59 | gm20b_dbg_pmu(g, "ACR capabilities %x\n", g->acr.capabilities); | 61 | gm20b_dbg_pmu(g, "ACR capabilities %x\n", g->acr.capabilities); |
60 | data = gk20a_readl(g, psec_falcon_mailbox0_r()); | 62 | data = nvgpu_flcn_mailbox_read(&g->sec2_flcn, FALCON_MAILBOX_0); |
61 | if (data) { | 63 | if (data) { |
62 | nvgpu_err(g, "ACR boot failed, err %x", data); | 64 | nvgpu_err(g, "ACR boot failed, err %x", data); |
63 | completion = -EAGAIN; | 65 | completion = -EAGAIN; |
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.h b/drivers/gpu/nvgpu/gp106/sec2_gp106.h index 1fe94bb8..cab3ca5d 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.h +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.h | |||
@@ -23,8 +23,9 @@ | |||
23 | #ifndef __SEC2_H_ | 23 | #ifndef __SEC2_H_ |
24 | #define __SEC2_H_ | 24 | #define __SEC2_H_ |
25 | 25 | ||
26 | int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout); | 26 | int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g, |
27 | int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout); | 27 | unsigned int timeout); |
28 | int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout); | ||
28 | int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, | 29 | int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, |
29 | void *desc, u32 bl_sz); | 30 | void *desc, u32 bl_sz); |
30 | void init_pmu_setup_hw1(struct gk20a *g); | 31 | void init_pmu_setup_hw1(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9d059b72..801a76a3 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -708,9 +708,9 @@ static const struct gpu_ops gv100_ops = { | |||
708 | .alloc_blob_space = gp106_alloc_blob_space, | 708 | .alloc_blob_space = gp106_alloc_blob_space, |
709 | .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, | 709 | .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, |
710 | .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, | 710 | .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, |
711 | .falcon_wait_for_halt = sec2_wait_for_halt, | 711 | .falcon_wait_for_halt = gp106_sec2_wait_for_halt, |
712 | .falcon_clear_halt_interrupt_status = | 712 | .falcon_clear_halt_interrupt_status = |
713 | sec2_clear_halt_interrupt_status, | 713 | gp106_sec2_clear_halt_interrupt_status, |
714 | .init_falcon_setup_hw = init_sec2_setup_hw1, | 714 | .init_falcon_setup_hw = init_sec2_setup_hw1, |
715 | .pmu_queue_tail = gk20a_pmu_queue_tail, | 715 | .pmu_queue_tail = gk20a_pmu_queue_tail, |
716 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | 716 | .pmu_get_queue_head = pwr_pmu_queue_head_r, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index 31587ee7..a08c0c31 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h | |||
@@ -80,6 +80,8 @@ | |||
80 | #define FALCON_REG_RSVD2 (31) | 80 | #define FALCON_REG_RSVD2 (31) |
81 | #define FALCON_REG_SIZE (32) | 81 | #define FALCON_REG_SIZE (32) |
82 | 82 | ||
83 | #define FALCON_MAILBOX_0 0x0 | ||
84 | #define FALCON_MAILBOX_1 0x1 | ||
83 | #define FALCON_MAILBOX_COUNT 0x02 | 85 | #define FALCON_MAILBOX_COUNT 0x02 |
84 | #define FALCON_BLOCK_SIZE 0x100 | 86 | #define FALCON_BLOCK_SIZE 0x100 |
85 | 87 | ||