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-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index a96bc4e1..4d3f5068 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4885,6 +4885,7 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
4885 struct gr_gk20a_isr_data *isr_data) 4885 struct gr_gk20a_isr_data *isr_data)
4886{ 4886{
4887 u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r()); 4887 u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r());
4888 int ret = 0;
4888 4889
4889 gk20a_dbg_fn(""); 4890 gk20a_dbg_fn("");
4890 4891
@@ -4897,10 +4898,11 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
4897 "firmware method error 0x%08x for offset 0x%04x", 4898 "firmware method error 0x%08x for offset 0x%04x",
4898 gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)), 4899 gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)),
4899 isr_data->data_lo); 4900 isr_data->data_lo);
4901 ret = -1;
4900 } 4902 }
4901 4903
4902 gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr); 4904 gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr);
4903 return -EINVAL; 4905 return ret;
4904} 4906}
4905 4907
4906static int gk20a_gr_handle_class_error(struct gk20a *g, 4908static int gk20a_gr_handle_class_error(struct gk20a *g,