diff options
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 31 | ||||
-rw-r--r-- | include/linux/tegra_vgpu.h | 12 |
2 files changed, 40 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index b4bb7f38..a7e9eed8 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -541,6 +541,35 @@ static int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority) | |||
541 | return err ? err : msg.ret; | 541 | return err ? err : msg.ret; |
542 | } | 542 | } |
543 | 543 | ||
544 | static int vgpu_fifo_set_runlist_interleave(struct gk20a *g, | ||
545 | u32 id, | ||
546 | bool is_tsg, | ||
547 | u32 runlist_id, | ||
548 | u32 new_level) | ||
549 | { | ||
550 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
551 | struct tegra_vgpu_cmd_msg msg; | ||
552 | struct tegra_vgpu_channel_runlist_interleave_params *p = | ||
553 | &msg.params.channel_interleave; | ||
554 | struct channel_gk20a *ch; | ||
555 | int err; | ||
556 | |||
557 | gk20a_dbg_fn(""); | ||
558 | |||
559 | /* FIXME: add support for TSGs */ | ||
560 | if (is_tsg) | ||
561 | return -ENOSYS; | ||
562 | |||
563 | ch = &g->fifo.channel[id]; | ||
564 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE; | ||
565 | msg.handle = platform->virt_handle; | ||
566 | p->handle = ch->virt_ctx; | ||
567 | p->level = new_level; | ||
568 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
569 | WARN_ON(err || msg.ret); | ||
570 | return err ? err : msg.ret; | ||
571 | } | ||
572 | |||
544 | static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, | 573 | static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, |
545 | struct channel_gk20a *ch) | 574 | struct channel_gk20a *ch) |
546 | { | 575 | { |
@@ -626,5 +655,5 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops) | |||
626 | gops->fifo.update_runlist = vgpu_fifo_update_runlist; | 655 | gops->fifo.update_runlist = vgpu_fifo_update_runlist; |
627 | gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle; | 656 | gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle; |
628 | gops->fifo.channel_set_priority = vgpu_channel_set_priority; | 657 | gops->fifo.channel_set_priority = vgpu_channel_set_priority; |
658 | gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave; | ||
629 | } | 659 | } |
630 | |||
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 280ca9c0..5f697e78 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GPU Virtualization Interfaces to Server | 2 | * Tegra GPU Virtualization Interfaces to Server |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2015, NVIDIA Corporation. All rights reserved. | 4 | * Copyright (c) 2014-2016, NVIDIA Corporation. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -74,7 +74,8 @@ enum { | |||
74 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE, | 74 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE, |
75 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE, | 75 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE, |
76 | TEGRA_VGPU_CMD_REG_OPS, | 76 | TEGRA_VGPU_CMD_REG_OPS, |
77 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY | 77 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY, |
78 | TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE | ||
78 | }; | 79 | }; |
79 | 80 | ||
80 | struct tegra_vgpu_connect_params { | 81 | struct tegra_vgpu_connect_params { |
@@ -298,6 +299,12 @@ struct tegra_vgpu_channel_priority_params { | |||
298 | u32 priority; | 299 | u32 priority; |
299 | }; | 300 | }; |
300 | 301 | ||
302 | /* level follows nvgpu.h definitions */ | ||
303 | struct tegra_vgpu_channel_runlist_interleave_params { | ||
304 | u64 handle; | ||
305 | u32 level; | ||
306 | }; | ||
307 | |||
301 | struct tegra_vgpu_cmd_msg { | 308 | struct tegra_vgpu_cmd_msg { |
302 | u32 cmd; | 309 | u32 cmd; |
303 | int ret; | 310 | int ret; |
@@ -326,6 +333,7 @@ struct tegra_vgpu_cmd_msg { | |||
326 | struct tegra_vgpu_sm_debug_mode sm_debug_mode; | 333 | struct tegra_vgpu_sm_debug_mode sm_debug_mode; |
327 | struct tegra_vgpu_reg_ops_params reg_ops; | 334 | struct tegra_vgpu_reg_ops_params reg_ops; |
328 | struct tegra_vgpu_channel_priority_params channel_priority; | 335 | struct tegra_vgpu_channel_priority_params channel_priority; |
336 | struct tegra_vgpu_channel_runlist_interleave_params channel_interleave; | ||
329 | char padding[192]; | 337 | char padding[192]; |
330 | } params; | 338 | } params; |
331 | }; | 339 | }; |