diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 10 | ||||
-rw-r--r-- | include/uapi/linux/nvgpu.h | 3 |
2 files changed, 12 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 35e4f0b8..a3448b2c 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5436,6 +5436,16 @@ static int gk20a_gr_handle_semaphore_pending(struct gk20a *g, | |||
5436 | struct fifo_gk20a *f = &g->fifo; | 5436 | struct fifo_gk20a *f = &g->fifo; |
5437 | struct channel_gk20a *ch = &f->channel[isr_data->chid]; | 5437 | struct channel_gk20a *ch = &f->channel[isr_data->chid]; |
5438 | 5438 | ||
5439 | if (gk20a_is_channel_marked_as_tsg(ch)) { | ||
5440 | struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; | ||
5441 | |||
5442 | gk20a_tsg_event_id_post_event(tsg, | ||
5443 | NVGPU_IOCTL_CHANNEL_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN); | ||
5444 | } else { | ||
5445 | gk20a_channel_event_id_post_event(ch, | ||
5446 | NVGPU_IOCTL_CHANNEL_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN); | ||
5447 | } | ||
5448 | |||
5439 | wake_up_interruptible_all(&ch->semaphore_wq); | 5449 | wake_up_interruptible_all(&ch->semaphore_wq); |
5440 | 5450 | ||
5441 | return 0; | 5451 | return 0; |
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index fe4e6de9..e65c8d74 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -1138,7 +1138,8 @@ struct nvgpu_event_id_ctrl_args { | |||
1138 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT 0 | 1138 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT 0 |
1139 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE 1 | 1139 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE 1 |
1140 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC 2 | 1140 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC 2 |
1141 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX 5 | 1141 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN 5 |
1142 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX 6 | ||
1142 | 1143 | ||
1143 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CMD_ENABLE 1 | 1144 | #define NVGPU_IOCTL_CHANNEL_EVENT_ID_CMD_ENABLE 1 |
1144 | 1145 | ||