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-rw-r--r--drivers/gpu/nvgpu/common/fb/fb_gv11b.c32
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c6
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h54
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h10
4 files changed, 97 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
index b98d1c41..49e8f385 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11B FB 2 * GV11B FB
3 * 3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -62,6 +62,34 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g)
62 } 62 }
63} 63}
64 64
65static void gv11b_fb_set_atomic_mode(struct gk20a *g)
66{
67 u32 reg_val;
68
69 /*
70 * NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE
71 * NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2
72 */
73 reg_val = nvgpu_readl(g, fb_mmu_ctrl_r());
74 reg_val = set_field(reg_val, fb_mmu_ctrl_atomic_capability_mode_m(),
75 fb_mmu_ctrl_atomic_capability_mode_rmw_f());
76 reg_val = set_field(reg_val, fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(),
77 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f());
78 nvgpu_writel(g, fb_mmu_ctrl_r(), reg_val);
79
80 /* NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW */
81 reg_val = nvgpu_readl(g, fb_hshub_num_active_ltcs_r());
82 reg_val = set_field(reg_val, fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(),
83 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f());
84 nvgpu_writel(g, fb_hshub_num_active_ltcs_r(), reg_val);
85
86 nvgpu_log(g, gpu_dbg_info, "fb_mmu_ctrl_r 0x%x",
87 gk20a_readl(g, fb_mmu_ctrl_r()));
88
89 nvgpu_log(g, gpu_dbg_info, "fb_hshub_num_active_ltcs_r 0x%x",
90 gk20a_readl(g, fb_hshub_num_active_ltcs_r()));
91}
92
65void gv11b_fb_init_hw(struct gk20a *g) 93void gv11b_fb_init_hw(struct gk20a *g)
66{ 94{
67 gm20b_fb_init_hw(g); 95 gm20b_fb_init_hw(g);
@@ -75,6 +103,8 @@ void gv11b_fb_init_fs_state(struct gk20a *g)
75 103
76 gv11b_init_nvlink_soc_credits(g); 104 gv11b_init_nvlink_soc_credits(g);
77 105
106 gv11b_fb_set_atomic_mode(g);
107
78 nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %x", 108 nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %x",
79 gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); 109 gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));
80 110
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 9506db3a..1dfecfc1 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11b GPU GR 2 * GV11b GPU GR
3 * 3 *
4 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -4297,7 +4297,9 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g)
4297 gr_gpcs_pri_mmu_ctrl_cache_mode_m() | 4297 gr_gpcs_pri_mmu_ctrl_cache_mode_m() |
4298 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() | 4298 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() |
4299 gr_gpcs_pri_mmu_ctrl_mmu_vol_m() | 4299 gr_gpcs_pri_mmu_ctrl_mmu_vol_m() |
4300 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(); 4300 gr_gpcs_pri_mmu_ctrl_mmu_disable_m()|
4301 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m()|
4302 gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m();
4301 gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp); 4303 gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp);
4302 gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0); 4304 gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0);
4303 gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0); 4305 gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
index 86bdaf28..fe35bb71 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -60,6 +60,22 @@ static inline u32 fb_fbhub_num_active_ltcs_r(void)
60{ 60{
61 return 0x00100800U; 61 return 0x00100800U;
62} 62}
63static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void)
64{
65 return U32(0x1U) << 25U;
66}
67static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void)
68{
69 return 0x2000000U;
70}
71static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m(void)
72{
73 return U32(0x1U) << 26U;
74}
75static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f(void)
76{
77 return 0x0U;
78}
63static inline u32 fb_mmu_ctrl_r(void) 79static inline u32 fb_mmu_ctrl_r(void)
64{ 80{
65 return 0x00100c80U; 81 return 0x00100c80U;
@@ -76,6 +92,42 @@ static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
76{ 92{
77 return (r >> 16U) & 0xffU; 93 return (r >> 16U) & 0xffU;
78} 94}
95static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void)
96{
97 return U32(0x3U) << 24U;
98}
99static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void)
100{
101 return 0x0U;
102}
103static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void)
104{
105 return 0x2000000U;
106}
107static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void)
108{
109 return U32(0x1U) << 27U;
110}
111static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f(void)
112{
113 return 0x0U;
114}
115static inline u32 fb_hshub_num_active_ltcs_r(void)
116{
117 return 0x001fbc20U;
118}
119static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void)
120{
121 return U32(0x1U) << 25U;
122}
123static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void)
124{
125 return 0x0U;
126}
127static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void)
128{
129 return 0x2000000U;
130}
79static inline u32 fb_priv_mmu_phy_secure_r(void) 131static inline u32 fb_priv_mmu_phy_secure_r(void)
80{ 132{
81 return 0x00100ce4U; 133 return 0x00100ce4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 36a7ebf5..01dc99d5 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -4976,6 +4976,14 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
4976{ 4976{
4977 return 0x1U << 31U; 4977 return 0x1U << 31U;
4978} 4978}
4979static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void)
4980{
4981 return U32(0x3U) << 24U;
4982}
4983static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void)
4984{
4985 return U32(0x1U) << 27U;
4986}
4979static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) 4987static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
4980{ 4988{
4981 return 0x00418890U; 4989 return 0x00418890U;