diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 78 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 38 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 76 |
8 files changed, 203 insertions, 19 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 3bc10109..5e46344a 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -442,6 +442,7 @@ struct gpu_ops { | |||
442 | void (*dump_ctxsw_stats)(struct gk20a *g, struct vm_gk20a *vm, | 442 | void (*dump_ctxsw_stats)(struct gk20a *g, struct vm_gk20a *vm, |
443 | struct nvgpu_gr_ctx *gr_ctx); | 443 | struct nvgpu_gr_ctx *gr_ctx); |
444 | void (*fecs_host_int_enable)(struct gk20a *g); | 444 | void (*fecs_host_int_enable)(struct gk20a *g); |
445 | int (*handle_ssync_hww)(struct gk20a *g); | ||
445 | } gr; | 446 | } gr; |
446 | struct { | 447 | struct { |
447 | void (*init_hw)(struct gk20a *g); | 448 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index c7b00500..fb02bb81 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5895,7 +5895,10 @@ int gk20a_gr_isr(struct gk20a *g) | |||
5895 | 5895 | ||
5896 | if (exception & gr_exception_fe_m()) { | 5896 | if (exception & gr_exception_fe_m()) { |
5897 | u32 fe = gk20a_readl(g, gr_fe_hww_esr_r()); | 5897 | u32 fe = gk20a_readl(g, gr_fe_hww_esr_r()); |
5898 | nvgpu_err(g, "fe warning %08x", fe); | 5898 | u32 info = gk20a_readl(g, gr_fe_hww_esr_info_r()); |
5899 | |||
5900 | nvgpu_err(g, "fe exception: esr 0x%08x, info 0x%08x", | ||
5901 | fe, info); | ||
5899 | gk20a_writel(g, gr_fe_hww_esr_r(), | 5902 | gk20a_writel(g, gr_fe_hww_esr_r(), |
5900 | gr_fe_hww_esr_reset_active_f()); | 5903 | gr_fe_hww_esr_reset_active_f()); |
5901 | need_reset |= -EFAULT; | 5904 | need_reset |= -EFAULT; |
@@ -5903,12 +5906,67 @@ int gk20a_gr_isr(struct gk20a *g) | |||
5903 | 5906 | ||
5904 | if (exception & gr_exception_memfmt_m()) { | 5907 | if (exception & gr_exception_memfmt_m()) { |
5905 | u32 memfmt = gk20a_readl(g, gr_memfmt_hww_esr_r()); | 5908 | u32 memfmt = gk20a_readl(g, gr_memfmt_hww_esr_r()); |
5906 | nvgpu_err(g, "memfmt exception %08x", memfmt); | 5909 | |
5910 | nvgpu_err(g, "memfmt exception: esr %08x", memfmt); | ||
5907 | gk20a_writel(g, gr_memfmt_hww_esr_r(), | 5911 | gk20a_writel(g, gr_memfmt_hww_esr_r(), |
5908 | gr_memfmt_hww_esr_reset_active_f()); | 5912 | gr_memfmt_hww_esr_reset_active_f()); |
5909 | need_reset |= -EFAULT; | 5913 | need_reset |= -EFAULT; |
5910 | } | 5914 | } |
5911 | 5915 | ||
5916 | if (exception & gr_exception_pd_m()) { | ||
5917 | u32 pd = gk20a_readl(g, gr_pd_hww_esr_r()); | ||
5918 | |||
5919 | nvgpu_err(g, "pd exception: esr 0x%08x", pd); | ||
5920 | gk20a_writel(g, gr_pd_hww_esr_r(), | ||
5921 | gr_pd_hww_esr_reset_active_f()); | ||
5922 | need_reset |= -EFAULT; | ||
5923 | } | ||
5924 | |||
5925 | if (exception & gr_exception_scc_m()) { | ||
5926 | u32 scc = gk20a_readl(g, gr_scc_hww_esr_r()); | ||
5927 | |||
5928 | nvgpu_err(g, "scc exception: esr 0x%08x", scc); | ||
5929 | gk20a_writel(g, gr_scc_hww_esr_r(), | ||
5930 | gr_scc_hww_esr_reset_active_f()); | ||
5931 | need_reset |= -EFAULT; | ||
5932 | } | ||
5933 | |||
5934 | if (exception & gr_exception_ds_m()) { | ||
5935 | u32 ds = gk20a_readl(g, gr_ds_hww_esr_r()); | ||
5936 | |||
5937 | nvgpu_err(g, "ds exception: esr: 0x%08x", ds); | ||
5938 | gk20a_writel(g, gr_ds_hww_esr_r(), | ||
5939 | gr_ds_hww_esr_reset_task_f()); | ||
5940 | need_reset |= -EFAULT; | ||
5941 | } | ||
5942 | |||
5943 | if (exception & gr_exception_ssync_m()) { | ||
5944 | if (g->ops.gr.handle_ssync_hww) | ||
5945 | need_reset |= g->ops.gr.handle_ssync_hww(g); | ||
5946 | else | ||
5947 | nvgpu_err(g, "unhandled ssync exception"); | ||
5948 | } | ||
5949 | |||
5950 | if (exception & gr_exception_mme_m()) { | ||
5951 | u32 mme = gk20a_readl(g, gr_mme_hww_esr_r()); | ||
5952 | u32 info = gk20a_readl(g, gr_mme_hww_esr_info_r()); | ||
5953 | |||
5954 | nvgpu_err(g, "mme exception: esr 0x%08x info:0x%08x", | ||
5955 | mme, info); | ||
5956 | gk20a_writel(g, gr_mme_hww_esr_r(), | ||
5957 | gr_mme_hww_esr_reset_active_f()); | ||
5958 | need_reset |= -EFAULT; | ||
5959 | } | ||
5960 | |||
5961 | if (exception & gr_exception_sked_m()) { | ||
5962 | u32 sked = gk20a_readl(g, gr_sked_hww_esr_r()); | ||
5963 | |||
5964 | nvgpu_err(g, "sked exception: esr 0x%08x", sked); | ||
5965 | gk20a_writel(g, gr_sked_hww_esr_r(), | ||
5966 | gr_sked_hww_esr_reset_active_f()); | ||
5967 | need_reset |= -EFAULT; | ||
5968 | } | ||
5969 | |||
5912 | /* check if a gpc exception has occurred */ | 5970 | /* check if a gpc exception has occurred */ |
5913 | if (exception & gr_exception_gpc_m() && need_reset == 0) { | 5971 | if (exception & gr_exception_gpc_m() && need_reset == 0) { |
5914 | bool post_event = false; | 5972 | bool post_event = false; |
@@ -5931,22 +5989,6 @@ int gk20a_gr_isr(struct gk20a *g) | |||
5931 | } | 5989 | } |
5932 | } | 5990 | } |
5933 | 5991 | ||
5934 | if (exception & gr_exception_ds_m()) { | ||
5935 | u32 ds = gk20a_readl(g, gr_ds_hww_esr_r()); | ||
5936 | nvgpu_err(g, "ds exception %08x", ds); | ||
5937 | gk20a_writel(g, gr_ds_hww_esr_r(), | ||
5938 | gr_ds_hww_esr_reset_task_f()); | ||
5939 | need_reset |= -EFAULT; | ||
5940 | } | ||
5941 | |||
5942 | if (exception & gr_exception_sked_m()) { | ||
5943 | u32 sked = gk20a_readl(g, gr_sked_hww_esr_r()); | ||
5944 | |||
5945 | nvgpu_err(g, "sked exception %08x", sked); | ||
5946 | gk20a_writel(g, gr_sked_hww_esr_r(), | ||
5947 | gr_sked_hww_esr_reset_active_f()); | ||
5948 | } | ||
5949 | |||
5950 | gk20a_writel(g, gr_intr_r(), gr_intr_exception_reset_f()); | 5992 | gk20a_writel(g, gr_intr_r(), gr_intr_exception_reset_f()); |
5951 | gr_intr &= ~gr_intr_exception_pending_f(); | 5993 | gr_intr &= ~gr_intr_exception_pending_f(); |
5952 | 5994 | ||
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index a2b97520..0f966adb 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -426,6 +426,7 @@ static const struct gpu_ops gv100_ops = { | |||
426 | gr_gv11b_handle_tpc_sm_ecc_exception, | 426 | gr_gv11b_handle_tpc_sm_ecc_exception, |
427 | .decode_egpc_addr = gv11b_gr_decode_egpc_addr, | 427 | .decode_egpc_addr = gv11b_gr_decode_egpc_addr, |
428 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, | 428 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, |
429 | .handle_ssync_hww = gr_gv11b_handle_ssync_hww, | ||
429 | }, | 430 | }, |
430 | .fb = { | 431 | .fb = { |
431 | .reset = gv100_fb_reset, | 432 | .reset = gv100_fb_reset, |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 6b43fcc8..3e207811 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -313,12 +313,32 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
313 | void gr_gv11b_enable_hww_exceptions(struct gk20a *g) | 313 | void gr_gv11b_enable_hww_exceptions(struct gk20a *g) |
314 | { | 314 | { |
315 | /* enable exceptions */ | 315 | /* enable exceptions */ |
316 | |||
316 | gk20a_writel(g, gr_fe_hww_esr_r(), | 317 | gk20a_writel(g, gr_fe_hww_esr_r(), |
317 | gr_fe_hww_esr_en_enable_f() | | 318 | gr_fe_hww_esr_en_enable_f() | |
318 | gr_fe_hww_esr_reset_active_f()); | 319 | gr_fe_hww_esr_reset_active_f()); |
319 | gk20a_writel(g, gr_memfmt_hww_esr_r(), | 320 | gk20a_writel(g, gr_memfmt_hww_esr_r(), |
320 | gr_memfmt_hww_esr_en_enable_f() | | 321 | gr_memfmt_hww_esr_en_enable_f() | |
321 | gr_memfmt_hww_esr_reset_active_f()); | 322 | gr_memfmt_hww_esr_reset_active_f()); |
323 | gk20a_writel(g, gr_pd_hww_esr_r(), | ||
324 | gr_pd_hww_esr_en_enable_f() | | ||
325 | gr_pd_hww_esr_reset_active_f()); | ||
326 | gk20a_writel(g, gr_scc_hww_esr_r(), | ||
327 | gr_scc_hww_esr_en_enable_f() | | ||
328 | gr_scc_hww_esr_reset_active_f()); | ||
329 | gk20a_writel(g, gr_ds_hww_esr_r(), | ||
330 | gr_ds_hww_esr_en_enabled_f() | | ||
331 | gr_ds_hww_esr_reset_task_f()); | ||
332 | gk20a_writel(g, gr_ssync_hww_esr_r(), | ||
333 | gr_ssync_hww_esr_en_enable_f() | | ||
334 | gr_ssync_hww_esr_reset_active_f()); | ||
335 | gk20a_writel(g, gr_mme_hww_esr_r(), | ||
336 | gr_mme_hww_esr_en_enable_f() | | ||
337 | gr_mme_hww_esr_reset_active_f()); | ||
338 | |||
339 | /* For now leave POR values */ | ||
340 | nvgpu_log(g, gpu_dbg_info, "gr_sked_hww_esr_en_r 0x%08x", | ||
341 | gk20a_readl(g, gr_sked_hww_esr_en_r())); | ||
322 | } | 342 | } |
323 | 343 | ||
324 | void gr_gv11b_fecs_host_int_enable(struct gk20a *g) | 344 | void gr_gv11b_fecs_host_int_enable(struct gk20a *g) |
@@ -351,8 +371,16 @@ void gr_gv11b_enable_exceptions(struct gk20a *g) | |||
351 | 371 | ||
352 | reg_val = gr_exception_en_fe_enabled_f() | | 372 | reg_val = gr_exception_en_fe_enabled_f() | |
353 | gr_exception_en_memfmt_enabled_f() | | 373 | gr_exception_en_memfmt_enabled_f() | |
374 | gr_exception_en_pd_enabled_f() | | ||
375 | gr_exception_en_scc_enabled_f() | | ||
354 | gr_exception_en_ds_enabled_f() | | 376 | gr_exception_en_ds_enabled_f() | |
377 | gr_exception_en_ssync_enabled_f() | | ||
378 | gr_exception_en_mme_enabled_f() | | ||
379 | gr_exception_en_sked_enabled_f() | | ||
355 | gr_exception_en_gpc_enabled_f(); | 380 | gr_exception_en_gpc_enabled_f(); |
381 | |||
382 | nvgpu_log(g, gpu_dbg_info, "gr_exception_en 0x%08x", reg_val); | ||
383 | |||
356 | gk20a_writel(g, gr_exception_en_r(), reg_val); | 384 | gk20a_writel(g, gr_exception_en_r(), reg_val); |
357 | 385 | ||
358 | } | 386 | } |
@@ -4246,3 +4274,13 @@ u32 gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g) | |||
4246 | { | 4274 | { |
4247 | return gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(); | 4275 | return gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(); |
4248 | } | 4276 | } |
4277 | |||
4278 | int gr_gv11b_handle_ssync_hww(struct gk20a *g) | ||
4279 | { | ||
4280 | u32 ssync = gk20a_readl(g, gr_ssync_hww_esr_r()); | ||
4281 | |||
4282 | nvgpu_err(g, "ssync exception: esr 0x%08x", ssync); | ||
4283 | gk20a_writel(g, gr_ssync_hww_esr_r(), | ||
4284 | gr_ssync_hww_esr_reset_active_f()); | ||
4285 | return -EFAULT; | ||
4286 | } | ||
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 157c567a..2f8d2e17 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -227,5 +227,6 @@ int gr_gv11b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
227 | void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, | 227 | void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, |
228 | struct channel_gk20a *ch_ctx, | 228 | struct channel_gk20a *ch_ctx, |
229 | struct nvgpu_mem *mem); | 229 | struct nvgpu_mem *mem); |
230 | int gr_gv11b_handle_ssync_hww(struct gk20a *g); | ||
230 | 231 | ||
231 | #endif | 232 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index ec86d74c..91d80080 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -399,6 +399,7 @@ static const struct gpu_ops gv11b_ops = { | |||
399 | .ecc_init_scrub_reg = gr_gv11b_ecc_init_scrub_reg, | 399 | .ecc_init_scrub_reg = gr_gv11b_ecc_init_scrub_reg, |
400 | .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, | 400 | .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, |
401 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, | 401 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, |
402 | .handle_ssync_hww = gr_gv11b_handle_ssync_hww, | ||
402 | }, | 403 | }, |
403 | .fb = { | 404 | .fb = { |
404 | .reset = gv11b_fb_reset, | 405 | .reset = gv11b_fb_reset, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h index ef259bcf..3be17f41 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -196,6 +196,22 @@ static inline u32 gr_exception_sked_m(void) | |||
196 | { | 196 | { |
197 | return 0x1U << 8U; | 197 | return 0x1U << 8U; |
198 | } | 198 | } |
199 | static inline u32 gr_exception_pd_m(void) | ||
200 | { | ||
201 | return 0x1U << 2U; | ||
202 | } | ||
203 | static inline u32 gr_exception_scc_m(void) | ||
204 | { | ||
205 | return 0x1U << 3U; | ||
206 | } | ||
207 | static inline u32 gr_exception_ssync_m(void) | ||
208 | { | ||
209 | return 0x1U << 5U; | ||
210 | } | ||
211 | static inline u32 gr_exception_mme_m(void) | ||
212 | { | ||
213 | return 0x1U << 7U; | ||
214 | } | ||
199 | static inline u32 gr_exception1_r(void) | 215 | static inline u32 gr_exception1_r(void) |
200 | { | 216 | { |
201 | return 0x00400118U; | 217 | return 0x00400118U; |
@@ -544,6 +560,10 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void) | |||
544 | { | 560 | { |
545 | return 0x80000000U; | 561 | return 0x80000000U; |
546 | } | 562 | } |
563 | static inline u32 gr_fe_hww_esr_info_r(void) | ||
564 | { | ||
565 | return 0x004041b0U; | ||
566 | } | ||
547 | static inline u32 gr_fe_go_idle_timeout_r(void) | 567 | static inline u32 gr_fe_go_idle_timeout_r(void) |
548 | { | 568 | { |
549 | return 0x00404154U; | 569 | return 0x00404154U; |
@@ -592,6 +612,10 @@ static inline u32 gr_mme_hww_esr_en_enable_f(void) | |||
592 | { | 612 | { |
593 | return 0x80000000U; | 613 | return 0x80000000U; |
594 | } | 614 | } |
615 | static inline u32 gr_mme_hww_esr_info_r(void) | ||
616 | { | ||
617 | return 0x00404494U; | ||
618 | } | ||
595 | static inline u32 gr_memfmt_hww_esr_r(void) | 619 | static inline u32 gr_memfmt_hww_esr_r(void) |
596 | { | 620 | { |
597 | return 0x00404600U; | 621 | return 0x00404600U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index a4bcce42..d34dcf33 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -184,6 +184,22 @@ static inline u32 gr_exception_sked_m(void) | |||
184 | { | 184 | { |
185 | return 0x1U << 8U; | 185 | return 0x1U << 8U; |
186 | } | 186 | } |
187 | static inline u32 gr_exception_pd_m(void) | ||
188 | { | ||
189 | return 0x1U << 2U; | ||
190 | } | ||
191 | static inline u32 gr_exception_scc_m(void) | ||
192 | { | ||
193 | return 0x1U << 3U; | ||
194 | } | ||
195 | static inline u32 gr_exception_ssync_m(void) | ||
196 | { | ||
197 | return 0x1U << 5U; | ||
198 | } | ||
199 | static inline u32 gr_exception_mme_m(void) | ||
200 | { | ||
201 | return 0x1U << 7U; | ||
202 | } | ||
187 | static inline u32 gr_exception1_r(void) | 203 | static inline u32 gr_exception1_r(void) |
188 | { | 204 | { |
189 | return 0x00400118U; | 205 | return 0x00400118U; |
@@ -232,6 +248,46 @@ static inline u32 gr_exception_en_ds_enabled_f(void) | |||
232 | { | 248 | { |
233 | return 0x10U; | 249 | return 0x10U; |
234 | } | 250 | } |
251 | static inline u32 gr_exception_en_pd_m(void) | ||
252 | { | ||
253 | return 0x1U << 2U; | ||
254 | } | ||
255 | static inline u32 gr_exception_en_pd_enabled_f(void) | ||
256 | { | ||
257 | return 0x4U; | ||
258 | } | ||
259 | static inline u32 gr_exception_en_scc_m(void) | ||
260 | { | ||
261 | return 0x1U << 3U; | ||
262 | } | ||
263 | static inline u32 gr_exception_en_scc_enabled_f(void) | ||
264 | { | ||
265 | return 0x8U; | ||
266 | } | ||
267 | static inline u32 gr_exception_en_ssync_m(void) | ||
268 | { | ||
269 | return 0x1U << 5U; | ||
270 | } | ||
271 | static inline u32 gr_exception_en_ssync_enabled_f(void) | ||
272 | { | ||
273 | return 0x20U; | ||
274 | } | ||
275 | static inline u32 gr_exception_en_mme_m(void) | ||
276 | { | ||
277 | return 0x1U << 7U; | ||
278 | } | ||
279 | static inline u32 gr_exception_en_mme_enabled_f(void) | ||
280 | { | ||
281 | return 0x80U; | ||
282 | } | ||
283 | static inline u32 gr_exception_en_sked_m(void) | ||
284 | { | ||
285 | return 0x1U << 8U; | ||
286 | } | ||
287 | static inline u32 gr_exception_en_sked_enabled_f(void) | ||
288 | { | ||
289 | return 0x100U; | ||
290 | } | ||
235 | static inline u32 gr_exception1_en_r(void) | 291 | static inline u32 gr_exception1_en_r(void) |
236 | { | 292 | { |
237 | return 0x00400130U; | 293 | return 0x00400130U; |
@@ -1408,6 +1464,10 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void) | |||
1408 | { | 1464 | { |
1409 | return 0x80000000U; | 1465 | return 0x80000000U; |
1410 | } | 1466 | } |
1467 | static inline u32 gr_fe_hww_esr_info_r(void) | ||
1468 | { | ||
1469 | return 0x004041b0U; | ||
1470 | } | ||
1411 | static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) | 1471 | static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) |
1412 | { | 1472 | { |
1413 | return 0x00419eacU; | 1473 | return 0x00419eacU; |
@@ -1536,6 +1596,10 @@ static inline u32 gr_mme_hww_esr_en_enable_f(void) | |||
1536 | { | 1596 | { |
1537 | return 0x80000000U; | 1597 | return 0x80000000U; |
1538 | } | 1598 | } |
1599 | static inline u32 gr_mme_hww_esr_info_r(void) | ||
1600 | { | ||
1601 | return 0x00404494U; | ||
1602 | } | ||
1539 | static inline u32 gr_memfmt_hww_esr_r(void) | 1603 | static inline u32 gr_memfmt_hww_esr_r(void) |
1540 | { | 1604 | { |
1541 | return 0x00404600U; | 1605 | return 0x00404600U; |
@@ -2980,6 +3044,18 @@ static inline u32 gr_scc_hww_esr_en_enable_f(void) | |||
2980 | { | 3044 | { |
2981 | return 0x80000000U; | 3045 | return 0x80000000U; |
2982 | } | 3046 | } |
3047 | static inline u32 gr_ssync_hww_esr_r(void) | ||
3048 | { | ||
3049 | return 0x00405a14U; | ||
3050 | } | ||
3051 | static inline u32 gr_ssync_hww_esr_reset_active_f(void) | ||
3052 | { | ||
3053 | return 0x40000000U; | ||
3054 | } | ||
3055 | static inline u32 gr_ssync_hww_esr_en_enable_f(void) | ||
3056 | { | ||
3057 | return 0x80000000U; | ||
3058 | } | ||
2983 | static inline u32 gr_sked_hww_esr_r(void) | 3059 | static inline u32 gr_sked_hww_esr_r(void) |
2984 | { | 3060 | { |
2985 | return 0x00407020U; | 3061 | return 0x00407020U; |