diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 |
16 files changed, 66 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index edc1c5ff..c2a8d6ce 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -470,6 +470,7 @@ struct gpu_ops { | |||
470 | u32 addr, | 470 | u32 addr, |
471 | u32 *priv_addr_table, | 471 | u32 *priv_addr_table, |
472 | u32 *num_registers); | 472 | u32 *num_registers); |
473 | u32 (*get_pmm_per_chiplet_offset)(void); | ||
473 | } gr; | 474 | } gr; |
474 | struct { | 475 | struct { |
475 | void (*init_hw)(struct gk20a *g); | 476 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 04d00e55..e4344b9f 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -63,9 +63,7 @@ | |||
63 | #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h> | 63 | #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h> |
64 | 64 | ||
65 | #define BLK_SIZE (256) | 65 | #define BLK_SIZE (256) |
66 | #define NV_PMM_FBP_STRIDE 0x1000 | ||
67 | #define NV_PERF_PMM_FBP_ROUTER_STRIDE 0x0200 | 66 | #define NV_PERF_PMM_FBP_ROUTER_STRIDE 0x0200 |
68 | #define NV_PERF_PMMGPC_CHIPLET_OFFSET 0x1000 | ||
69 | #define NV_PERF_PMMGPCROUTER_STRIDE 0x0200 | 67 | #define NV_PERF_PMMGPCROUTER_STRIDE 0x0200 |
70 | #define NV_PCFG_BASE 0x00088000 | 68 | #define NV_PCFG_BASE 0x00088000 |
71 | #define NV_XBAR_MXBAR_PRI_GPC_GNIC_STRIDE 0x0020 | 69 | #define NV_XBAR_MXBAR_PRI_GPC_GNIC_STRIDE 0x0020 |
@@ -7563,7 +7561,7 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g, | |||
7563 | count, offset, max_cnt, base, ~0)) | 7561 | count, offset, max_cnt, base, ~0)) |
7564 | return -EINVAL; | 7562 | return -EINVAL; |
7565 | 7563 | ||
7566 | base = (NV_PERF_PMMGPC_CHIPLET_OFFSET * gpc_num); | 7564 | base = (g->ops.gr.get_pmm_per_chiplet_offset() * gpc_num); |
7567 | if (add_ctxsw_buffer_map_entries(map, | 7565 | if (add_ctxsw_buffer_map_entries(map, |
7568 | &g->gr.ctx_vars.ctxsw_regs.perf_gpc, | 7566 | &g->gr.ctx_vars.ctxsw_regs.perf_gpc, |
7569 | count, offset, max_cnt, base, ~0)) | 7567 | count, offset, max_cnt, base, ~0)) |
@@ -7703,7 +7701,9 @@ static int gr_gk20a_create_hwpm_ctxsw_buffer_offset_map(struct gk20a *g) | |||
7703 | &g->gr.ctx_vars.ctxsw_regs.fbp, | 7701 | &g->gr.ctx_vars.ctxsw_regs.fbp, |
7704 | &count, &offset, | 7702 | &count, &offset, |
7705 | hwpm_ctxsw_reg_count_max, 0, | 7703 | hwpm_ctxsw_reg_count_max, 0, |
7706 | g->gr.num_fbps, NV_PMM_FBP_STRIDE, ~0)) | 7704 | g->gr.num_fbps, |
7705 | g->ops.gr.get_pmm_per_chiplet_offset(), | ||
7706 | ~0)) | ||
7707 | goto cleanup; | 7707 | goto cleanup; |
7708 | 7708 | ||
7709 | /* Add entries from _LIST_nv_perf_fbprouter_ctx_regs */ | 7709 | /* Add entries from _LIST_nv_perf_fbprouter_ctx_regs */ |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 08ac20e4..262957c5 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B GPC MMU | 2 | * GM20B GPC MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -41,6 +41,7 @@ | |||
41 | #include <nvgpu/hw/gm20b/hw_ltc_gm20b.h> | 41 | #include <nvgpu/hw/gm20b/hw_ltc_gm20b.h> |
42 | #include <nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h> | 42 | #include <nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h> |
43 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | 43 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> |
44 | #include <nvgpu/hw/gm20b/hw_perf_gm20b.h> | ||
44 | 45 | ||
45 | void gr_gm20b_init_gpc_mmu(struct gk20a *g) | 46 | void gr_gm20b_init_gpc_mmu(struct gk20a *g) |
46 | { | 47 | { |
@@ -1541,3 +1542,8 @@ void gm20a_gr_disable_rd_coalesce(struct gk20a *g) | |||
1541 | 1542 | ||
1542 | gk20a_writel(g, gr_gpcs_tpcs_tex_m_dbg2_r(), dbg2_reg); | 1543 | gk20a_writel(g, gr_gpcs_tpcs_tex_m_dbg2_r(), dbg2_reg); |
1543 | } | 1544 | } |
1545 | |||
1546 | u32 gr_gm20b_get_pmm_per_chiplet_offset(void) | ||
1547 | { | ||
1548 | return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1); | ||
1549 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index 3f604028..aabf6d95 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B GPC MMU | 2 | * GM20B GPC MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -135,4 +135,5 @@ void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr, | |||
135 | u32 *priv_addr_table_index); | 135 | u32 *priv_addr_table_index); |
136 | void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 136 | void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
137 | u32 global_esr); | 137 | u32 global_esr); |
138 | u32 gr_gm20b_get_pmm_per_chiplet_offset(void); | ||
138 | #endif | 139 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index ac1c7123..bbe2b100 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -322,6 +322,8 @@ static const struct gpu_ops gm20b_ops = { | |||
322 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, | 322 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, |
323 | .decode_priv_addr = gr_gk20a_decode_priv_addr, | 323 | .decode_priv_addr = gr_gk20a_decode_priv_addr, |
324 | .create_priv_addr_table = gr_gk20a_create_priv_addr_table, | 324 | .create_priv_addr_table = gr_gk20a_create_priv_addr_table, |
325 | .get_pmm_per_chiplet_offset = | ||
326 | gr_gm20b_get_pmm_per_chiplet_offset, | ||
325 | }, | 327 | }, |
326 | .fb = { | 328 | .fb = { |
327 | .reset = fb_gk20a_reset, | 329 | .reset = fb_gk20a_reset, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index f2ce4050..91bc614c 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -385,6 +385,8 @@ static const struct gpu_ops gp106_ops = { | |||
385 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, | 385 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, |
386 | .decode_priv_addr = gr_gk20a_decode_priv_addr, | 386 | .decode_priv_addr = gr_gk20a_decode_priv_addr, |
387 | .create_priv_addr_table = gr_gk20a_create_priv_addr_table, | 387 | .create_priv_addr_table = gr_gk20a_create_priv_addr_table, |
388 | .get_pmm_per_chiplet_offset = | ||
389 | gr_gm20b_get_pmm_per_chiplet_offset, | ||
388 | }, | 390 | }, |
389 | .fb = { | 391 | .fb = { |
390 | .reset = gp106_fb_reset, | 392 | .reset = gp106_fb_reset, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a31418f7..5c10d79d 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -353,6 +353,8 @@ static const struct gpu_ops gp10b_ops = { | |||
353 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, | 353 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, |
354 | .decode_priv_addr = gr_gk20a_decode_priv_addr, | 354 | .decode_priv_addr = gr_gk20a_decode_priv_addr, |
355 | .create_priv_addr_table = gr_gk20a_create_priv_addr_table, | 355 | .create_priv_addr_table = gr_gk20a_create_priv_addr_table, |
356 | .get_pmm_per_chiplet_offset = | ||
357 | gr_gm20b_get_pmm_per_chiplet_offset, | ||
356 | }, | 358 | }, |
357 | .fb = { | 359 | .fb = { |
358 | .reset = fb_gk20a_reset, | 360 | .reset = fb_gk20a_reset, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index c7c648a7..fe235f89 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -432,6 +432,8 @@ static const struct gpu_ops gv100_ops = { | |||
432 | .add_ctxsw_reg_perf_pma = gr_gv100_add_ctxsw_reg_perf_pma, | 432 | .add_ctxsw_reg_perf_pma = gr_gv100_add_ctxsw_reg_perf_pma, |
433 | .decode_priv_addr = gr_gv11b_decode_priv_addr, | 433 | .decode_priv_addr = gr_gv11b_decode_priv_addr, |
434 | .create_priv_addr_table = gr_gv11b_create_priv_addr_table, | 434 | .create_priv_addr_table = gr_gv11b_create_priv_addr_table, |
435 | .get_pmm_per_chiplet_offset = | ||
436 | gr_gv11b_get_pmm_per_chiplet_offset, | ||
435 | }, | 437 | }, |
436 | .fb = { | 438 | .fb = { |
437 | .reset = gv100_fb_reset, | 439 | .reset = gv100_fb_reset, |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 67603739..f8461f9d 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -4513,10 +4513,16 @@ int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, | |||
4513 | return 0; | 4513 | return 0; |
4514 | } | 4514 | } |
4515 | 4515 | ||
4516 | static u32 gr_gv11b_pri_pmmgpc_addr(u32 gpc_num, u32 domain_idx, u32 offset) | 4516 | u32 gr_gv11b_get_pmm_per_chiplet_offset(void) |
4517 | { | ||
4518 | return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1); | ||
4519 | } | ||
4520 | |||
4521 | static u32 gr_gv11b_pri_pmmgpc_addr(struct gk20a *g, u32 gpc_num, | ||
4522 | u32 domain_idx, u32 offset) | ||
4517 | { | 4523 | { |
4518 | return perf_pmmgpc_base_v() + | 4524 | return perf_pmmgpc_base_v() + |
4519 | (gpc_num * (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1)) + | 4525 | (gpc_num * g->ops.gr.get_pmm_per_chiplet_offset()) + |
4520 | (domain_idx * perf_pmmgpc_perdomain_offset_v()) + | 4526 | (domain_idx * perf_pmmgpc_perdomain_offset_v()) + |
4521 | offset; | 4527 | offset; |
4522 | } | 4528 | } |
@@ -4531,8 +4537,7 @@ static void gr_gv11b_split_pmm_fbp_broadcast_address(struct gk20a *g, | |||
4531 | 4537 | ||
4532 | for (fbp_num = 0; fbp_num < g->gr.num_fbps; fbp_num++) { | 4538 | for (fbp_num = 0; fbp_num < g->gr.num_fbps; fbp_num++) { |
4533 | base = perf_pmmfbp_base_v() + | 4539 | base = perf_pmmfbp_base_v() + |
4534 | (fbp_num * | 4540 | (fbp_num * g->ops.gr.get_pmm_per_chiplet_offset()); |
4535 | (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1)); | ||
4536 | 4541 | ||
4537 | for (domain_idx = domain_start; | 4542 | for (domain_idx = domain_start; |
4538 | domain_idx < (domain_start + num_domains); | 4543 | domain_idx < (domain_start + num_domains); |
@@ -4653,7 +4658,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, | |||
4653 | domain_idx < (pmm_domain_start + num_domains); | 4658 | domain_idx < (pmm_domain_start + num_domains); |
4654 | domain_idx++) { | 4659 | domain_idx++) { |
4655 | priv_addr_table[t++] = | 4660 | priv_addr_table[t++] = |
4656 | gr_gv11b_pri_pmmgpc_addr(gpc_num, | 4661 | gr_gv11b_pri_pmmgpc_addr(g, gpc_num, |
4657 | domain_idx, offset); | 4662 | domain_idx, offset); |
4658 | } | 4663 | } |
4659 | } | 4664 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 3c581326..1a3a851e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -234,6 +234,7 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
234 | int gr_gv11b_handle_ssync_hww(struct gk20a *g); | 234 | int gr_gv11b_handle_ssync_hww(struct gk20a *g); |
235 | u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm); | 235 | u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm); |
236 | 236 | ||
237 | u32 gr_gv11b_get_pmm_per_chiplet_offset(void); | ||
237 | int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, | 238 | int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, |
238 | int *addr_type, | 239 | int *addr_type, |
239 | u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, | 240 | u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e39df1db..d0a564db 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -405,6 +405,8 @@ static const struct gpu_ops gv11b_ops = { | |||
405 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, | 405 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, |
406 | .decode_priv_addr = gr_gv11b_decode_priv_addr, | 406 | .decode_priv_addr = gr_gv11b_decode_priv_addr, |
407 | .create_priv_addr_table = gr_gv11b_create_priv_addr_table, | 407 | .create_priv_addr_table = gr_gv11b_create_priv_addr_table, |
408 | .get_pmm_per_chiplet_offset = | ||
409 | gr_gv11b_get_pmm_per_chiplet_offset, | ||
408 | }, | 410 | }, |
409 | .fb = { | 411 | .fb = { |
410 | .reset = gv11b_fb_reset, | 412 | .reset = gv11b_fb_reset, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h index ae34cabd..a94ba307 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -56,6 +56,14 @@ | |||
56 | #ifndef _hw_perf_gm20b_h_ | 56 | #ifndef _hw_perf_gm20b_h_ |
57 | #define _hw_perf_gm20b_h_ | 57 | #define _hw_perf_gm20b_h_ |
58 | 58 | ||
59 | static inline u32 perf_pmmsys_base_v(void) | ||
60 | { | ||
61 | return 0x001b0000U; | ||
62 | } | ||
63 | static inline u32 perf_pmmsys_extent_v(void) | ||
64 | { | ||
65 | return 0x001b0fffU; | ||
66 | } | ||
59 | static inline u32 perf_pmasys_control_r(void) | 67 | static inline u32 perf_pmasys_control_r(void) |
60 | { | 68 | { |
61 | return 0x001b4000U; | 69 | return 0x001b4000U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h index b0182789..334cd200 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -56,6 +56,14 @@ | |||
56 | #ifndef _hw_perf_gp106_h_ | 56 | #ifndef _hw_perf_gp106_h_ |
57 | #define _hw_perf_gp106_h_ | 57 | #define _hw_perf_gp106_h_ |
58 | 58 | ||
59 | static inline u32 perf_pmmsys_base_v(void) | ||
60 | { | ||
61 | return 0x001b0000U; | ||
62 | } | ||
63 | static inline u32 perf_pmmsys_extent_v(void) | ||
64 | { | ||
65 | return 0x001b0fffU; | ||
66 | } | ||
59 | static inline u32 perf_pmasys_control_r(void) | 67 | static inline u32 perf_pmasys_control_r(void) |
60 | { | 68 | { |
61 | return 0x001b4000U; | 69 | return 0x001b4000U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h index aa0fafe7..43424e13 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -56,6 +56,14 @@ | |||
56 | #ifndef _hw_perf_gp10b_h_ | 56 | #ifndef _hw_perf_gp10b_h_ |
57 | #define _hw_perf_gp10b_h_ | 57 | #define _hw_perf_gp10b_h_ |
58 | 58 | ||
59 | static inline u32 perf_pmmsys_base_v(void) | ||
60 | { | ||
61 | return 0x001b0000U; | ||
62 | } | ||
63 | static inline u32 perf_pmmsys_extent_v(void) | ||
64 | { | ||
65 | return 0x001b0fffU; | ||
66 | } | ||
59 | static inline u32 perf_pmasys_control_r(void) | 67 | static inline u32 perf_pmasys_control_r(void) |
60 | { | 68 | { |
61 | return 0x001b4000U; | 69 | return 0x001b4000U; |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index c56e900e..53ba1e14 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -227,6 +227,8 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
227 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, | 227 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, |
228 | .decode_priv_addr = gr_gk20a_decode_priv_addr, | 228 | .decode_priv_addr = gr_gk20a_decode_priv_addr, |
229 | .create_priv_addr_table = gr_gk20a_create_priv_addr_table, | 229 | .create_priv_addr_table = gr_gk20a_create_priv_addr_table, |
230 | .get_pmm_per_chiplet_offset = | ||
231 | gr_gm20b_get_pmm_per_chiplet_offset, | ||
230 | }, | 232 | }, |
231 | .fb = { | 233 | .fb = { |
232 | .reset = fb_gk20a_reset, | 234 | .reset = fb_gk20a_reset, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index a4496044..0b9049dd 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -263,6 +263,8 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
263 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, | 263 | .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, |
264 | .decode_priv_addr = gr_gv11b_decode_priv_addr, | 264 | .decode_priv_addr = gr_gv11b_decode_priv_addr, |
265 | .create_priv_addr_table = gr_gv11b_create_priv_addr_table, | 265 | .create_priv_addr_table = gr_gv11b_create_priv_addr_table, |
266 | .get_pmm_per_chiplet_offset = | ||
267 | gr_gv11b_get_pmm_per_chiplet_offset, | ||
266 | }, | 268 | }, |
267 | .fb = { | 269 | .fb = { |
268 | .reset = gv11b_fb_reset, | 270 | .reset = gv11b_fb_reset, |