diff options
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 51 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | 20 |
3 files changed, 61 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index 1c1a3c82..ec5c5b7d 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -37,7 +37,7 @@ | |||
37 | 37 | ||
38 | /* PMU F/W version */ | 38 | /* PMU F/W version */ |
39 | #define APP_VERSION_GV11B 23355380 | 39 | #define APP_VERSION_GV11B 23355380 |
40 | #define APP_VERSION_GV10X 22836594 | 40 | #define APP_VERSION_GV10X 23440730 |
41 | #define APP_VERSION_GP10X 21308030 | 41 | #define APP_VERSION_GP10X 21308030 |
42 | #define APP_VERSION_GP10B 20429989 | 42 | #define APP_VERSION_GP10B 20429989 |
43 | #define APP_VERSION_GM20B 20490253 | 43 | #define APP_VERSION_GM20B 20490253 |
@@ -389,6 +389,11 @@ static void pmu_allocation_set_dmem_offset_v1(struct nvgpu_pmu *pmu, | |||
389 | pmu_a_ptr->alloc.dmem.offset = offset; | 389 | pmu_a_ptr->alloc.dmem.offset = offset; |
390 | } | 390 | } |
391 | 391 | ||
392 | static void *get_pmu_msg_pmu_init_msg_ptr_v5(struct pmu_init_msg *init) | ||
393 | { | ||
394 | return (void *)(&(init->pmu_init_v5)); | ||
395 | } | ||
396 | |||
392 | static void *get_pmu_msg_pmu_init_msg_ptr_v4(struct pmu_init_msg *init) | 397 | static void *get_pmu_msg_pmu_init_msg_ptr_v4(struct pmu_init_msg *init) |
393 | { | 398 | { |
394 | return (void *)(&(init->pmu_init_v4)); | 399 | return (void *)(&(init->pmu_init_v4)); |
@@ -399,6 +404,14 @@ static void *get_pmu_msg_pmu_init_msg_ptr_v3(struct pmu_init_msg *init) | |||
399 | return (void *)(&(init->pmu_init_v3)); | 404 | return (void *)(&(init->pmu_init_v3)); |
400 | } | 405 | } |
401 | 406 | ||
407 | static u16 get_pmu_init_msg_pmu_sw_mg_off_v5(union pmu_init_msg_pmu *init_msg) | ||
408 | { | ||
409 | struct pmu_init_msg_pmu_v5 *init = | ||
410 | (struct pmu_init_msg_pmu_v5 *)(&init_msg->v5); | ||
411 | |||
412 | return init->sw_managed_area_offset; | ||
413 | } | ||
414 | |||
402 | static u16 get_pmu_init_msg_pmu_sw_mg_off_v4(union pmu_init_msg_pmu *init_msg) | 415 | static u16 get_pmu_init_msg_pmu_sw_mg_off_v4(union pmu_init_msg_pmu *init_msg) |
403 | { | 416 | { |
404 | struct pmu_init_msg_pmu_v4 *init = | 417 | struct pmu_init_msg_pmu_v4 *init = |
@@ -415,6 +428,14 @@ static u16 get_pmu_init_msg_pmu_sw_mg_off_v3(union pmu_init_msg_pmu *init_msg) | |||
415 | return init->sw_managed_area_offset; | 428 | return init->sw_managed_area_offset; |
416 | } | 429 | } |
417 | 430 | ||
431 | static u16 get_pmu_init_msg_pmu_sw_mg_size_v5(union pmu_init_msg_pmu *init_msg) | ||
432 | { | ||
433 | struct pmu_init_msg_pmu_v5 *init = | ||
434 | (struct pmu_init_msg_pmu_v5 *)(&init_msg->v5); | ||
435 | |||
436 | return init->sw_managed_area_size; | ||
437 | } | ||
438 | |||
418 | static u16 get_pmu_init_msg_pmu_sw_mg_size_v4(union pmu_init_msg_pmu *init_msg) | 439 | static u16 get_pmu_init_msg_pmu_sw_mg_size_v4(union pmu_init_msg_pmu *init_msg) |
419 | { | 440 | { |
420 | struct pmu_init_msg_pmu_v4 *init = | 441 | struct pmu_init_msg_pmu_v4 *init = |
@@ -856,7 +877,7 @@ static void get_pmu_init_msg_pmu_queue_params_v4(struct pmu_queue *queue, | |||
856 | static void get_pmu_init_msg_pmu_queue_params_v5(struct pmu_queue *queue, | 877 | static void get_pmu_init_msg_pmu_queue_params_v5(struct pmu_queue *queue, |
857 | u32 id, void *pmu_init_msg) | 878 | u32 id, void *pmu_init_msg) |
858 | { | 879 | { |
859 | struct pmu_init_msg_pmu_v4 *init = pmu_init_msg; | 880 | struct pmu_init_msg_pmu_v5 *init = pmu_init_msg; |
860 | u32 current_ptr = 0; | 881 | u32 current_ptr = 0; |
861 | u8 i; | 882 | u8 i; |
862 | u8 tmp_id = id; | 883 | u8 tmp_id = id; |
@@ -1249,18 +1270,26 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1249 | pmu_allocation_get_fb_addr_v3; | 1270 | pmu_allocation_get_fb_addr_v3; |
1250 | g->ops.pmu_ver.pmu_allocation_get_fb_size = | 1271 | g->ops.pmu_ver.pmu_allocation_get_fb_size = |
1251 | pmu_allocation_get_fb_size_v3; | 1272 | pmu_allocation_get_fb_size_v3; |
1252 | if (pmu->desc->app_version == APP_VERSION_GV10X) | 1273 | if (pmu->desc->app_version == APP_VERSION_GV10X) { |
1253 | g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = | 1274 | g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = |
1254 | get_pmu_init_msg_pmu_queue_params_v5; | 1275 | get_pmu_init_msg_pmu_queue_params_v5; |
1255 | else | 1276 | g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr = |
1277 | get_pmu_msg_pmu_init_msg_ptr_v5; | ||
1278 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off = | ||
1279 | get_pmu_init_msg_pmu_sw_mg_off_v5; | ||
1280 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size = | ||
1281 | get_pmu_init_msg_pmu_sw_mg_size_v5; | ||
1282 | } else { | ||
1256 | g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = | 1283 | g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = |
1257 | get_pmu_init_msg_pmu_queue_params_v4; | 1284 | get_pmu_init_msg_pmu_queue_params_v4; |
1258 | g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr = | 1285 | g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr = |
1259 | get_pmu_msg_pmu_init_msg_ptr_v4; | 1286 | get_pmu_msg_pmu_init_msg_ptr_v4; |
1260 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off = | 1287 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off = |
1261 | get_pmu_init_msg_pmu_sw_mg_off_v4; | 1288 | get_pmu_init_msg_pmu_sw_mg_off_v4; |
1262 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size = | 1289 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size = |
1263 | get_pmu_init_msg_pmu_sw_mg_size_v4; | 1290 | get_pmu_init_msg_pmu_sw_mg_size_v4; |
1291 | } | ||
1292 | |||
1264 | g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size = | 1293 | g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size = |
1265 | get_pmu_perfmon_cmd_start_size_v3; | 1294 | get_pmu_perfmon_cmd_start_size_v3; |
1266 | g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar = | 1295 | g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar = |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h index 71ecc24a..d146cac7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h +++ b/drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -102,7 +102,7 @@ struct pmu_hdr { | |||
102 | #define nv_pmu_hdr pmu_hdr | 102 | #define nv_pmu_hdr pmu_hdr |
103 | typedef u8 flcn_status; | 103 | typedef u8 flcn_status; |
104 | 104 | ||
105 | #define PMU_DMEM_ALLOC_ALIGNMENT (4) | 105 | #define PMU_DMEM_ALLOC_ALIGNMENT (32) |
106 | #define PMU_DMEM_ALIGNMENT (4) | 106 | #define PMU_DMEM_ALIGNMENT (4) |
107 | 107 | ||
108 | #define PMU_CMD_FLAGS_PMU_MASK (0xF0) | 108 | #define PMU_CMD_FLAGS_PMU_MASK (0xF0) |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h index 8e38db31..5f718dc6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -141,10 +141,27 @@ struct pmu_init_msg_pmu_v4 { | |||
141 | u8 dummy[18]; | 141 | u8 dummy[18]; |
142 | }; | 142 | }; |
143 | 143 | ||
144 | struct pmu_init_msg_pmu_v5 { | ||
145 | u8 msg_type; | ||
146 | u8 flcn_status; | ||
147 | u8 queue_index[PMU_QUEUE_COUNT_FOR_V4]; | ||
148 | u16 queue_size[PMU_QUEUE_COUNT_FOR_V4]; | ||
149 | u16 queue_offset; | ||
150 | |||
151 | u16 sw_managed_area_offset; | ||
152 | u16 sw_managed_area_size; | ||
153 | |||
154 | u16 os_debug_entry_point; | ||
155 | |||
156 | u8 dummy[18]; | ||
157 | u8 pad; | ||
158 | }; | ||
159 | |||
144 | union pmu_init_msg_pmu { | 160 | union pmu_init_msg_pmu { |
145 | struct pmu_init_msg_pmu_v1 v1; | 161 | struct pmu_init_msg_pmu_v1 v1; |
146 | struct pmu_init_msg_pmu_v3 v3; | 162 | struct pmu_init_msg_pmu_v3 v3; |
147 | struct pmu_init_msg_pmu_v4 v4; | 163 | struct pmu_init_msg_pmu_v4 v4; |
164 | struct pmu_init_msg_pmu_v5 v5; | ||
148 | }; | 165 | }; |
149 | 166 | ||
150 | struct pmu_init_msg { | 167 | struct pmu_init_msg { |
@@ -153,6 +170,7 @@ struct pmu_init_msg { | |||
153 | struct pmu_init_msg_pmu_v1 pmu_init_v1; | 170 | struct pmu_init_msg_pmu_v1 pmu_init_v1; |
154 | struct pmu_init_msg_pmu_v3 pmu_init_v3; | 171 | struct pmu_init_msg_pmu_v3 pmu_init_v3; |
155 | struct pmu_init_msg_pmu_v4 pmu_init_v4; | 172 | struct pmu_init_msg_pmu_v4 pmu_init_v4; |
173 | struct pmu_init_msg_pmu_v5 pmu_init_v5; | ||
156 | }; | 174 | }; |
157 | }; | 175 | }; |
158 | 176 | ||