diff options
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/cde.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_channel.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h | 37 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.h | 4 |
8 files changed, 28 insertions, 75 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/cde.c b/drivers/gpu/nvgpu/common/linux/cde.c index 30edc1d5..65c50726 100644 --- a/drivers/gpu/nvgpu/common/linux/cde.c +++ b/drivers/gpu/nvgpu/common/linux/cde.c | |||
@@ -527,16 +527,12 @@ static int gk20a_init_cde_required_class(struct gk20a_cde_ctx *cde_ctx, | |||
527 | { | 527 | { |
528 | struct nvgpu_os_linux *l = cde_ctx->l; | 528 | struct nvgpu_os_linux *l = cde_ctx->l; |
529 | struct gk20a *g = &l->g; | 529 | struct gk20a *g = &l->g; |
530 | struct nvgpu_alloc_obj_ctx_args alloc_obj_ctx; | ||
531 | int err; | 530 | int err; |
532 | 531 | ||
533 | alloc_obj_ctx.class_num = required_class; | ||
534 | alloc_obj_ctx.flags = 0; | ||
535 | |||
536 | /* CDE enabled */ | 532 | /* CDE enabled */ |
537 | cde_ctx->ch->cde = true; | 533 | cde_ctx->ch->cde = true; |
538 | 534 | ||
539 | err = gk20a_alloc_obj_ctx(cde_ctx->ch, &alloc_obj_ctx); | 535 | err = gk20a_alloc_obj_ctx(cde_ctx->ch, required_class, 0); |
540 | if (err) { | 536 | if (err) { |
541 | nvgpu_warn(g, "cde: failed to allocate ctx. err=%d", | 537 | nvgpu_warn(g, "cde: failed to allocate ctx. err=%d", |
542 | err); | 538 | err); |
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c index ee4755c8..7814aea5 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c | |||
@@ -923,6 +923,10 @@ long gk20a_channel_ioctl(struct file *filp, | |||
923 | case NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD: | 923 | case NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD: |
924 | break; | 924 | break; |
925 | case NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX: | 925 | case NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX: |
926 | { | ||
927 | struct nvgpu_alloc_obj_ctx_args *args = | ||
928 | (struct nvgpu_alloc_obj_ctx_args *)buf; | ||
929 | |||
926 | err = gk20a_busy(ch->g); | 930 | err = gk20a_busy(ch->g); |
927 | if (err) { | 931 | if (err) { |
928 | dev_err(dev, | 932 | dev_err(dev, |
@@ -930,10 +934,10 @@ long gk20a_channel_ioctl(struct file *filp, | |||
930 | __func__, cmd); | 934 | __func__, cmd); |
931 | break; | 935 | break; |
932 | } | 936 | } |
933 | err = ch->g->ops.gr.alloc_obj_ctx(ch, | 937 | err = ch->g->ops.gr.alloc_obj_ctx(ch, args->class_num, args->flags); |
934 | (struct nvgpu_alloc_obj_ctx_args *)buf); | ||
935 | gk20a_idle(ch->g); | 938 | gk20a_idle(ch->g); |
936 | break; | 939 | break; |
940 | } | ||
937 | case NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX: | 941 | case NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX: |
938 | { | 942 | { |
939 | struct nvgpu_alloc_gpfifo_ex_args *alloc_gpfifo_ex_args = | 943 | struct nvgpu_alloc_gpfifo_ex_args *alloc_gpfifo_ex_args = |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index a34f06b2..65c3b56f 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -225,7 +225,7 @@ struct gpu_ops { | |||
225 | void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); | 225 | void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); |
226 | void (*free_channel_ctx)(struct channel_gk20a *c, bool is_tsg); | 226 | void (*free_channel_ctx)(struct channel_gk20a *c, bool is_tsg); |
227 | int (*alloc_obj_ctx)(struct channel_gk20a *c, | 227 | int (*alloc_obj_ctx)(struct channel_gk20a *c, |
228 | struct nvgpu_alloc_obj_ctx_args *args); | 228 | u32 class_num, u32 flags); |
229 | int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr, | 229 | int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr, |
230 | struct channel_gk20a *c, u64 zcull_va, | 230 | struct channel_gk20a *c, u64 zcull_va, |
231 | u32 mode); | 231 | u32 mode); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index f78d862c..ef7136fe 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -2890,8 +2890,7 @@ void gk20a_free_channel_ctx(struct channel_gk20a *c, bool is_tsg) | |||
2890 | c->first_init = false; | 2890 | c->first_init = false; |
2891 | } | 2891 | } |
2892 | 2892 | ||
2893 | int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | 2893 | int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) |
2894 | struct nvgpu_alloc_obj_ctx_args *args) | ||
2895 | { | 2894 | { |
2896 | struct gk20a *g = c->g; | 2895 | struct gk20a *g = c->g; |
2897 | struct fifo_gk20a *f = &g->fifo; | 2896 | struct fifo_gk20a *f = &g->fifo; |
@@ -2909,13 +2908,13 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | |||
2909 | return -EINVAL; | 2908 | return -EINVAL; |
2910 | } | 2909 | } |
2911 | 2910 | ||
2912 | if (!g->ops.gr.is_valid_class(g, args->class_num)) { | 2911 | if (!g->ops.gr.is_valid_class(g, class_num)) { |
2913 | nvgpu_err(g, | 2912 | nvgpu_err(g, |
2914 | "invalid obj class 0x%x", args->class_num); | 2913 | "invalid obj class 0x%x", class_num); |
2915 | err = -EINVAL; | 2914 | err = -EINVAL; |
2916 | goto out; | 2915 | goto out; |
2917 | } | 2916 | } |
2918 | c->obj_class = args->class_num; | 2917 | c->obj_class = class_num; |
2919 | 2918 | ||
2920 | if (gk20a_is_channel_marked_as_tsg(c)) | 2919 | if (gk20a_is_channel_marked_as_tsg(c)) |
2921 | tsg = &f->tsg[c->tsgid]; | 2920 | tsg = &f->tsg[c->tsgid]; |
@@ -2924,8 +2923,8 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | |||
2924 | if (!tsg) { | 2923 | if (!tsg) { |
2925 | if (!ch_ctx->gr_ctx) { | 2924 | if (!ch_ctx->gr_ctx) { |
2926 | err = gr_gk20a_alloc_channel_gr_ctx(g, c, | 2925 | err = gr_gk20a_alloc_channel_gr_ctx(g, c, |
2927 | args->class_num, | 2926 | class_num, |
2928 | args->flags); | 2927 | flags); |
2929 | if (err) { | 2928 | if (err) { |
2930 | nvgpu_err(g, | 2929 | nvgpu_err(g, |
2931 | "fail to allocate gr ctx buffer"); | 2930 | "fail to allocate gr ctx buffer"); |
@@ -2945,8 +2944,8 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | |||
2945 | tsg->vm = c->vm; | 2944 | tsg->vm = c->vm; |
2946 | nvgpu_vm_get(tsg->vm); | 2945 | nvgpu_vm_get(tsg->vm); |
2947 | err = gr_gk20a_alloc_tsg_gr_ctx(g, tsg, | 2946 | err = gr_gk20a_alloc_tsg_gr_ctx(g, tsg, |
2948 | args->class_num, | 2947 | class_num, |
2949 | args->flags); | 2948 | flags); |
2950 | if (err) { | 2949 | if (err) { |
2951 | nvgpu_err(g, | 2950 | nvgpu_err(g, |
2952 | "fail to allocate TSG gr ctx buffer"); | 2951 | "fail to allocate TSG gr ctx buffer"); |
@@ -2993,7 +2992,7 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | |||
2993 | } | 2992 | } |
2994 | 2993 | ||
2995 | /* tweak any perf parameters per-context here */ | 2994 | /* tweak any perf parameters per-context here */ |
2996 | if (args->class_num == KEPLER_COMPUTE_A) { | 2995 | if (class_num == KEPLER_COMPUTE_A) { |
2997 | u32 tex_lock_disable_mask; | 2996 | u32 tex_lock_disable_mask; |
2998 | u32 texlock; | 2997 | u32 texlock; |
2999 | u32 lockboost_mask; | 2998 | u32 lockboost_mask; |
@@ -3047,7 +3046,7 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | |||
3047 | "failed to set texlock for compute class"); | 3046 | "failed to set texlock for compute class"); |
3048 | } | 3047 | } |
3049 | 3048 | ||
3050 | args->flags |= NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO; | 3049 | flags |= NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO; |
3051 | 3050 | ||
3052 | if (g->support_pmu && g->can_elpg) | 3051 | if (g->support_pmu && g->can_elpg) |
3053 | nvgpu_pmu_enable_elpg(g); | 3052 | nvgpu_pmu_enable_elpg(g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index db1a9514..8a044728 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -522,13 +522,7 @@ int gk20a_init_gr_channel(struct channel_gk20a *ch_gk20a); | |||
522 | 522 | ||
523 | int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr); | 523 | int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr); |
524 | 524 | ||
525 | struct nvgpu_alloc_obj_ctx_args; | 525 | int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags); |
526 | struct nvgpu_free_obj_ctx_args; | ||
527 | |||
528 | int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | ||
529 | struct nvgpu_alloc_obj_ctx_args *args); | ||
530 | int gk20a_free_obj_ctx(struct channel_gk20a *c, | ||
531 | struct nvgpu_free_obj_ctx_args *args); | ||
532 | void gk20a_free_channel_ctx(struct channel_gk20a *c, bool is_tsg); | 526 | void gk20a_free_channel_ctx(struct channel_gk20a *c, bool is_tsg); |
533 | 527 | ||
534 | int gk20a_gr_isr(struct gk20a *g); | 528 | int gk20a_gr_isr(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h deleted file mode 100644 index 9a48c0df..00000000 --- a/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h +++ /dev/null | |||
@@ -1,37 +0,0 @@ | |||
1 | /* | ||
2 | * GP10B GPU graphics ops | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _GR_OPS_GP10B_H_ | ||
26 | #define _GR_OPS_GP10B_H_ | ||
27 | |||
28 | #include "gr_ops.h" | ||
29 | |||
30 | #define __gr_gp10b_op(X) gr_gp10b_ ## X | ||
31 | #define __set_gr_gp10b_op(X) . X = gr_gp10b_ ## X | ||
32 | |||
33 | bool __gr_gp10b_op(is_valid_class)(struct gk20a *, u32); | ||
34 | int __gr_gp10b_op(alloc_obj_ctx)(struct channel_gk20a *, struct nvgpu_alloc_obj_ctx_args *); | ||
35 | |||
36 | |||
37 | #endif | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index d400f08e..fca02831 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -485,8 +485,7 @@ static int vgpu_gr_tsg_bind_gr_ctx(struct tsg_gk20a *tsg) | |||
485 | return err; | 485 | return err; |
486 | } | 486 | } |
487 | 487 | ||
488 | int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, | 488 | int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) |
489 | struct nvgpu_alloc_obj_ctx_args *args) | ||
490 | { | 489 | { |
491 | struct gk20a *g = c->g; | 490 | struct gk20a *g = c->g; |
492 | struct fifo_gk20a *f = &g->fifo; | 491 | struct fifo_gk20a *f = &g->fifo; |
@@ -503,12 +502,12 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, | |||
503 | return -EINVAL; | 502 | return -EINVAL; |
504 | } | 503 | } |
505 | 504 | ||
506 | if (!g->ops.gr.is_valid_class(g, args->class_num)) { | 505 | if (!g->ops.gr.is_valid_class(g, class_num)) { |
507 | nvgpu_err(g, "invalid obj class 0x%x", args->class_num); | 506 | nvgpu_err(g, "invalid obj class 0x%x", class_num); |
508 | err = -EINVAL; | 507 | err = -EINVAL; |
509 | goto out; | 508 | goto out; |
510 | } | 509 | } |
511 | c->obj_class = args->class_num; | 510 | c->obj_class = class_num; |
512 | 511 | ||
513 | if (gk20a_is_channel_marked_as_tsg(c)) | 512 | if (gk20a_is_channel_marked_as_tsg(c)) |
514 | tsg = &f->tsg[c->tsgid]; | 513 | tsg = &f->tsg[c->tsgid]; |
@@ -518,8 +517,8 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, | |||
518 | if (!ch_ctx->gr_ctx) { | 517 | if (!ch_ctx->gr_ctx) { |
519 | err = g->ops.gr.alloc_gr_ctx(g, &c->ch_ctx.gr_ctx, | 518 | err = g->ops.gr.alloc_gr_ctx(g, &c->ch_ctx.gr_ctx, |
520 | c->vm, | 519 | c->vm, |
521 | args->class_num, | 520 | class_num, |
522 | args->flags); | 521 | flags); |
523 | if (!err) | 522 | if (!err) |
524 | err = vgpu_gr_ch_bind_gr_ctx(c); | 523 | err = vgpu_gr_ch_bind_gr_ctx(c); |
525 | if (err) { | 524 | if (err) { |
@@ -541,8 +540,8 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, | |||
541 | nvgpu_vm_get(tsg->vm); | 540 | nvgpu_vm_get(tsg->vm); |
542 | err = g->ops.gr.alloc_gr_ctx(g, &tsg->tsg_gr_ctx, | 541 | err = g->ops.gr.alloc_gr_ctx(g, &tsg->tsg_gr_ctx, |
543 | c->vm, | 542 | c->vm, |
544 | args->class_num, | 543 | class_num, |
545 | args->flags); | 544 | flags); |
546 | if (!err) | 545 | if (!err) |
547 | err = vgpu_gr_tsg_bind_gr_ctx(tsg); | 546 | err = vgpu_gr_tsg_bind_gr_ctx(tsg); |
548 | if (err) { | 547 | if (err) { |
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h index 5a5e0928..b43e334a 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h | |||
@@ -27,7 +27,6 @@ | |||
27 | 27 | ||
28 | struct gk20a; | 28 | struct gk20a; |
29 | struct channel_gk20a; | 29 | struct channel_gk20a; |
30 | struct nvgpu_alloc_obj_ctx_args; | ||
31 | struct gr_gk20a; | 30 | struct gr_gk20a; |
32 | struct gr_zcull_info; | 31 | struct gr_zcull_info; |
33 | struct zbc_entry; | 32 | struct zbc_entry; |
@@ -36,8 +35,7 @@ struct dbg_session_gk20a; | |||
36 | 35 | ||
37 | void vgpu_gr_detect_sm_arch(struct gk20a *g); | 36 | void vgpu_gr_detect_sm_arch(struct gk20a *g); |
38 | void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg); | 37 | void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg); |
39 | int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, | 38 | int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags); |
40 | struct nvgpu_alloc_obj_ctx_args *args); | ||
41 | int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr, | 39 | int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr, |
42 | struct channel_gk20a *c, u64 zcull_va, | 40 | struct channel_gk20a *c, u64 zcull_va, |
43 | u32 mode); | 41 | u32 mode); |