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-rw-r--r--drivers/gpu/nvgpu/vgpu/mm_vgpu.c18
-rw-r--r--include/linux/tegra_vgpu.h8
2 files changed, 25 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
index bfaacff5..8af01158 100644
--- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
@@ -531,8 +531,26 @@ static void vgpu_mm_tlb_invalidate(struct vm_gk20a *vm)
531 WARN_ON(err || msg.ret); 531 WARN_ON(err || msg.ret);
532} 532}
533 533
534static void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable)
535{
536 struct gk20a_platform *platform = gk20a_get_platform(g->dev);
537 struct tegra_vgpu_cmd_msg msg;
538 struct tegra_vgpu_mmu_debug_mode *p = &msg.params.mmu_debug_mode;
539 int err;
540
541 gk20a_dbg_fn("");
542
543 msg.cmd = TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE;
544 msg.handle = platform->virt_handle;
545 p->enable = (u32)enable;
546 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
547 WARN_ON(err || msg.ret);
548}
549
534void vgpu_init_mm_ops(struct gpu_ops *gops) 550void vgpu_init_mm_ops(struct gpu_ops *gops)
535{ 551{
552 gops->mm.is_debug_mode_enabled = NULL;
553 gops->mm.set_debug_mode = vgpu_mm_mmu_set_debug_mode;
536 gops->mm.gmmu_map = vgpu_locked_gmmu_map; 554 gops->mm.gmmu_map = vgpu_locked_gmmu_map;
537 gops->mm.gmmu_unmap = vgpu_locked_gmmu_unmap; 555 gops->mm.gmmu_unmap = vgpu_locked_gmmu_unmap;
538 gops->mm.vm_remove = vgpu_vm_remove_support; 556 gops->mm.vm_remove = vgpu_vm_remove_support;
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 7587d355..b7bcc905 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -70,7 +70,8 @@ enum {
70 TEGRA_VGPU_CMD_ZBC_SET_TABLE, 70 TEGRA_VGPU_CMD_ZBC_SET_TABLE,
71 TEGRA_VGPU_CMD_ZBC_QUERY_TABLE, 71 TEGRA_VGPU_CMD_ZBC_QUERY_TABLE,
72 TEGRA_VGPU_CMD_AS_MAP_EX, 72 TEGRA_VGPU_CMD_AS_MAP_EX,
73 TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS 73 TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS,
74 TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE
74}; 75};
75 76
76struct tegra_vgpu_connect_params { 77struct tegra_vgpu_connect_params {
@@ -259,6 +260,10 @@ struct tegra_vgpu_gr_bind_ctxsw_buffers_params {
259 u32 mode; 260 u32 mode;
260}; 261};
261 262
263struct tegra_vgpu_mmu_debug_mode {
264 u32 enable;
265};
266
262struct tegra_vgpu_cmd_msg { 267struct tegra_vgpu_cmd_msg {
263 u32 cmd; 268 u32 cmd;
264 int ret; 269 int ret;
@@ -283,6 +288,7 @@ struct tegra_vgpu_cmd_msg {
283 struct tegra_vgpu_zbc_set_table_params zbc_set_table; 288 struct tegra_vgpu_zbc_set_table_params zbc_set_table;
284 struct tegra_vgpu_zbc_query_table_params zbc_query_table; 289 struct tegra_vgpu_zbc_query_table_params zbc_query_table;
285 struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers; 290 struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers;
291 struct tegra_vgpu_mmu_debug_mode mmu_debug_mode;
286 char padding[192]; 292 char padding[192];
287 } params; 293 } params;
288}; 294};