73 files changed, 5543 insertions, 2 deletions

diff --git a/Makefile.umbrella.tmk b/Makefile.umbrella.tmk
new file mode 100644
index 00000000..451beca7
--- /dev/null
+++ b/Makefile.umbrella.tmk
@@ -0,0 +1,26 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+# tmake for SW Mobile
+#
+# Repository umbrella makefile fragment for "nvgpu"
+#
+###############################################################################
+
+#
+# Components common to all builds
+#
+NV_REPOSITORY_COMPONENTS := drivers/gpu/nvgpu
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:
diff --git a/drivers/gpu/nvgpu/Makefile.interface.tmk b/drivers/gpu/nvgpu/Makefile.interface.tmk
new file mode 100644
index 00000000..f836de19
--- /dev/null
+++ b/drivers/gpu/nvgpu/Makefile.interface.tmk
@@ -0,0 +1,27 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018, NVIDIA CORPORATION.  All Rights Reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+# tmake for SW Mobile component makefile
+#
+# libnvgpu-drv interface makefile fragment
+#
+###############################################################################
+
+ifdef NV_INTERFACE_FLAG_SHARED_LIBRARY_SECTION
+NV_INTERFACE_NAME             := nvgpu-drv
+NV_INTERFACE_EXPORTS          := libnvgpu-drv
+NV_INTERFACE_PUBLIC_INCLUDES  := . include
+endif
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
new file mode 100644
index 00000000..676ca05b
--- /dev/null
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -0,0 +1,209 @@
+# -*- mode: makefile -*-
+#
+# Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+srcs := common/mm/nvgpu_allocator.c \
+        common/mm/bitmap_allocator.c \
+        common/mm/buddy_allocator.c \
+        common/mm/page_allocator.c \
+        common/mm/lockless_allocator.c \
+        common/mm/gmmu.c \
+        common/mm/pd_cache.c \
+        common/mm/vm.c \
+        common/mm/vm_area.c \
+        common/mm/nvgpu_mem.c \
+        common/mm/comptags.c \
+        common/mm/mm.c \
+        common/bus.c \
+        common/enabled.c \
+        common/pramin.c \
+        common/semaphore.c \
+        common/as.c \
+        common/rbtree.c \
+        common/ltc.c \
+        common/vbios/bios.c \
+        common/falcon/falcon.c \
+        common/pmu/pmu.c \
+        common/pmu/pmu_ipc.c \
+        common/pmu/pmu_fw.c \
+        common/pmu/pmu_pg.c \
+        common/pmu/pmu_perfmon.c \
+        common/pmu/pmu_debug.c \
+        common/posix/nvgpu.c \
+        common/posix/bitmap.c \
+        common/posix/bug.c \
+        common/posix/log.c \
+        common/posix/kmem.c \
+        common/posix/io.c \
+        common/posix/posix-nvgpu_mem.c \
+        common/posix/dma.c \
+        common/posix/posix-vm.c \
+        common/posix/timers.c \
+        common/posix/posix-comptags.c \
+        common/posix/firmware.c \
+        common/posix/soc.c \
+        common/posix/rwsem.c \
+        common/posix/cond.c \
+        common/posix/thread.c \
+        common/posix/error_notifier.c \
+        common/posix/fuse.c \
+        common/posix/clk_arb.c \
+        common/posix/channel.c \
+        common/posix/tsg.c \
+        common/posix/nvlink.c \
+        common/posix/lock.c \
+        common/posix/stubs.c \
+        boardobj/boardobj.c \
+        boardobj/boardobjgrp.c \
+        boardobj/boardobjgrpmask.c \
+        boardobj/boardobjgrp_e255.c \
+        boardobj/boardobjgrp_e32.c \
+        pstate/pstate.c \
+        volt/volt_dev.c \
+        volt/volt_pmu.c \
+        volt/volt_policy.c \
+        volt/volt_rail.c \
+        clk/clk.c \
+        clk/clk_domain.c \
+        clk/clk_fll.c \
+        clk/clk_freq_controller.c \
+        clk/clk_prog.c \
+        clk/clk_vf_point.c \
+        clk/clk_vin.c \
+        therm/thrm.c \
+        therm/thrmchannel.c \
+        therm/thrmdev.c \
+        therm/thrmpmu.c \
+        perf/perf.c \
+        perf/vfe_equ.c \
+        perf/vfe_var.c \
+        pmgr/pmgr.c \
+        pmgr/pmgrpmu.c \
+        pmgr/pwrdev.c \
+        pmgr/pwrmonitor.c \
+        pmgr/pwrpolicy.c \
+        lpwr/lpwr.c \
+        lpwr/rppg.c \
+        gk20a/gk20a.c \
+        gk20a/bus_gk20a.c \
+        gk20a/pramin_gk20a.c \
+        gk20a/ce2_gk20a.c \
+        gk20a/fifo_gk20a.c \
+        gk20a/channel_gk20a.c \
+        gk20a/channel_sync_gk20a.c \
+        gk20a/dbg_gpu_gk20a.c \
+        gk20a/regops_gk20a.c \
+        gk20a/gr_gk20a.c \
+        gk20a/mm_gk20a.c \
+        gk20a/pmu_gk20a.c \
+        gk20a/flcn_gk20a.c \
+        gk20a/priv_ring_gk20a.c \
+        gk20a/fence_gk20a.c \
+        gk20a/therm_gk20a.c \
+        gk20a/gr_ctx_gk20a_sim.c \
+        gk20a/gr_ctx_gk20a.c \
+        gk20a/gk20a_gating_reglist.c \
+        gk20a/fb_gk20a.c \
+        gk20a/hal.c \
+        gk20a/tsg_gk20a.c \
+        gk20a/mc_gk20a.c \
+        gm20b/hal_gm20b.c \
+        gm20b/bus_gm20b.c \
+        gm20b/ltc_gm20b.c \
+        gm20b/gr_gm20b.c \
+        gm20b/clk_gm20b.c \
+        gm20b/fb_gm20b.c \
+        gm20b/fifo_gm20b.c \
+        gm20b/gr_ctx_gm20b.c \
+        gm20b/gm20b_gating_reglist.c \
+        gm20b/acr_gm20b.c \
+        gm20b/pmu_gm20b.c \
+        gm20b/mm_gm20b.c \
+        gm20b/regops_gm20b.c \
+        gm20b/therm_gm20b.c \
+        gm20b/fuse_gm20b.c \
+        gp10b/gr_gp10b.c  \
+        gp10b/gr_ctx_gp10b.c  \
+        gp10b/ce_gp10b.c \
+        gp10b/mc_gp10b.c  \
+        gp10b/fifo_gp10b.c  \
+        gp10b/ltc_gp10b.c \
+        gp10b/mm_gp10b.c \
+        gp10b/fb_gp10b.c \
+        gp10b/pmu_gp10b.c \
+        gp10b/hal_gp10b.c \
+        gp10b/rpfb_gp10b.c \
+        gp10b/gp10b_gating_reglist.c \
+        gp10b/regops_gp10b.c \
+        gp10b/therm_gp10b.c \
+        gp10b/fecs_trace_gp10b.c \
+        gp10b/priv_ring_gp10b.c \
+        gp10b/gp10b.c \
+        gp10b/fuse_gp10b.c \
+        gv11b/gv11b.c  \
+        gv11b/dbg_gpu_gv11b.c  \
+        gv11b/mc_gv11b.c  \
+        gv11b/ltc_gv11b.c  \
+        gv11b/hal_gv11b.c \
+        gv11b/gv11b_gating_reglist.c \
+        gv11b/gr_gv11b.c \
+        gv11b/fb_gv11b.c \
+        gv11b/fifo_gv11b.c \
+        gv11b/mm_gv11b.c \
+        gv11b/ce_gv11b.c \
+        gv11b/gr_ctx_gv11b.c \
+        gv11b/pmu_gv11b.c \
+        gv11b/acr_gv11b.c \
+        gv11b/subctx_gv11b.c \
+        gv11b/regops_gv11b.c \
+        gv11b/therm_gv11b.c \
+        gp106/hal_gp106.c \
+        gp106/mm_gp106.c \
+        gp106/flcn_gp106.c \
+        gp106/pmu_gp106.c \
+        gp106/mclk_gp106.c \
+        gp106/gr_gp106.c \
+        gp106/gr_ctx_gp106.c \
+        gp106/acr_gp106.c \
+        gp106/sec2_gp106.c \
+        gp106/fifo_gp106.c \
+        gp106/fb_gp106.c \
+        gp106/regops_gp106.c \
+        gp106/bios_gp106.c \
+        gp106/fuse_gp106.c \
+        gp106/clk_gp106.c \
+        gp106/clk_arb_gp106.c \
+        gp106/gp106_gating_reglist.c \
+        gp106/xve_gp106.c \
+        gp106/therm_gp106.c \
+        gv100/mm_gv100.c \
+        gv100/gr_ctx_gv100.c \
+        gv100/fb_gv100.c \
+        gv100/bios_gv100.c \
+        gv100/fifo_gv100.c \
+        gv100/gr_gv100.c \
+        gv100/regops_gv100.c \
+        gv100/flcn_gv100.c \
+        gv100/mc_gv100.c \
+        gv100/nvlink_gv100.c \
+        gv100/hal_gv100.c \
+        gv100/pmu_gv100.c \
+        gv100/gv100_gating_reglist.c
diff --git a/drivers/gpu/nvgpu/Makefile.tmk b/drivers/gpu/nvgpu/Makefile.tmk
new file mode 100644
index 00000000..25775d39
--- /dev/null
+++ b/drivers/gpu/nvgpu/Makefile.tmk
@@ -0,0 +1,34 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2018 NVIDIA CORPORATION.  All Rights Reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+ifdef NV_COMPONENT_FLAG_SHARED_LIBRARY_SECTION
+include $(NV_BUILD_START_COMPONENT)
+
+include $(NV_COMPONENT_DIR)/Makefile.sources
+
+NV_COMPONENT_NAME               := nvgpu-drv
+NV_COMPONENT_OWN_INTERFACE_DIR  := .
+NV_COMPONENT_SOURCES            := $(srcs)
+NV_COMPONENT_INCLUDES           := . include ../../../include
+NV_COMPONENT_SYSTEM_SHARED_LIBRARIES += pthread
+NV_COMPONENT_CFLAGS             += -D__NVGPU_POSIX__
+
+include $(NV_BUILD_SHARED_LIBRARY)
+endif
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:
diff --git a/drivers/gpu/nvgpu/common/posix/bitmap.c b/drivers/gpu/nvgpu/common/posix/bitmap.c
new file mode 100644
index 00000000..51361777
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/bitmap.c
@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <nvgpu/posix/bitops.h>
+#include <nvgpu/posix/atomic.h>
+
+#define BIT_MASK(nr)    (1UL << ((nr) % BITS_PER_LONG))
+#define BIT_WORD(nr)    ((nr) / BITS_PER_LONG)
+
+unsigned long __nvgpu_posix_fls(unsigned long word)
+{
+        int num = BITS_PER_LONG - 1;
+
+#if BITS_PER_LONG == 64
+        if (!(word & (~0ul << 32))) {
+                num -= 32;
+                word <<= 32;
+        }
+#endif
+        if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
+                num -= 16;
+                word <<= 16;
+        }
+        if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
+                num -= 8;
+                word <<= 8;
+        }
+        if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
+                num -= 4;
+                word <<= 4;
+        }
+        if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
+                num -= 2;
+                word <<= 2;
+        }
+        if (!(word & (~0ul << (BITS_PER_LONG-1))))
+                num -= 1;
+        return num;
+}
+
+unsigned long __nvgpu_posix_ffs(unsigned long word)
+{
+        int num = 0;
+
+#if BITS_PER_LONG == 64
+        if ((word & 0xffffffff) == 0) {
+                num += 32;
+                word >>= 32;
+        }
+#endif
+        if ((word & 0xffff) == 0) {
+                num += 16;
+                word >>= 16;
+        }
+        if ((word & 0xff) == 0) {
+                num += 8;
+                word >>= 8;
+        }
+        if ((word & 0xf) == 0) {
+                num += 4;
+                word >>= 4;
+        }
+        if ((word & 0x3) == 0) {
+                num += 2;
+                word >>= 2;
+        }
+        if ((word & 0x1) == 0)
+                num += 1;
+
+        return num;
+}
+
+static unsigned long __find_next_bit(const unsigned long *addr,
+                                     unsigned long n,
+                                     unsigned long start,
+                                     bool invert)
+{
+        unsigned long idx;
+        unsigned long w;
+        unsigned long start_mask;
+
+        /*
+         * We make a mask we can XOR into the word so that we can invert the
+         * word without requiring a branch. I.e instead of doing:
+         *
+         *   w = invert ? ~addr[idx] : addr[idx]
+         *
+         * We can do:
+         *
+         *   w = addr[idx] ^= invert_mask
+         *
+         * This saves us a branch every iteration through the loop. Now we can
+         * always just look for 1s.
+         */
+        unsigned long invert_mask = invert ? ~0UL : 0UL;
+
+        if (start >= n)
+                return n;
+
+        start_mask = ~0UL << (start & (BITS_PER_LONG - 1));
+
+        idx = start / BITS_PER_LONG;
+        w = (addr[idx] ^ invert_mask) & start_mask;
+
+        start = round_up(start, BITS_PER_LONG);
+
+        /*
+         * Find the first non-zero word taking into account start and
+         * invert.
+         */
+        while (!w) {
+                idx++;
+                start += BITS_PER_LONG;
+
+                w = addr[idx] ^ invert_mask;
+        }
+
+        return min(n, ffs(w) + idx * BITS_PER_LONG);
+}
+
+unsigned long find_first_bit(const unsigned long *addr, unsigned long size)
+{
+        return __find_next_bit(addr, size, 0, false);
+}
+
+unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long size)
+{
+        return __find_next_bit(addr, size, 0, true);
+}
+
+unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
+                            unsigned long offset)
+{
+        return __find_next_bit(addr, size, offset, false);
+}
+
+static unsigned long find_next_zero_bit(const unsigned long *addr,
+                                        unsigned long size,
+                                        unsigned long offset)
+{
+        return __find_next_bit(addr, size, offset, true);
+}
+
+void bitmap_set(unsigned long *map, unsigned int start, int len)
+{
+        unsigned int end = start + len;
+
+        /*
+         * Super slow naive implementation. But speed isn't what matters here.
+         */
+        while (start < end)
+                set_bit(start++, map);
+}
+
+void bitmap_clear(unsigned long *map, unsigned int start, int len)
+{
+        unsigned int end = start + len;
+
+        while (start < end)
+                clear_bit(start++, map);
+}
+
+/*
+ * This is essentially a find-first-fit allocator: this searches a bitmap for
+ * the first space that is large enough to satisfy the requested size of bits.
+ * That means that this is not a vary smart allocator. But it is fast relative
+ * to an allocator that goes looking for an optimal location.
+ */
+unsigned long bitmap_find_next_zero_area_off(unsigned long *map,
+                                             unsigned long size,
+                                             unsigned long start,
+                                             unsigned int nr,
+                                             unsigned long align_mask,
+                                             unsigned long align_offset)
+{
+        unsigned long offs;
+
+        while (start + nr <= size) {
+                start = find_next_zero_bit(map, size, start);
+
+                start = ALIGN_MASK(start + align_offset, align_mask) -
+                        align_offset;
+
+                /*
+                 * Not enough space left to satisfy the requested area.
+                 */
+                if ((start + nr) > size)
+                        return size;
+
+                offs = find_next_bit(map, size, start);
+
+                if ((offs - start) >= nr)
+                        return start;
+
+                start = offs + 1;
+        }
+
+        return size;
+}
+
+unsigned long bitmap_find_next_zero_area(unsigned long *map,
+                                         unsigned long size,
+                                         unsigned long start,
+                                         unsigned int nr,
+                                         unsigned long align_mask)
+{
+        return bitmap_find_next_zero_area_off(map, size, start, nr,
+                                              align_mask, 0);
+}
+
+bool test_bit(int nr, const volatile unsigned long *addr)
+{
+        return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
+}
+
+bool test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long mask = BIT_MASK(nr);
+        volatile unsigned long *p = addr + BIT_WORD(nr);
+
+        return !!(__sync_fetch_and_or(p, mask) & mask);
+}
+
+bool test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long mask = BIT_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+        return !!(__sync_fetch_and_and(p, ~mask) & mask);
+}
+
+void set_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long mask = BIT_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+        __atomic_or(p, mask);
+}
+
+void clear_bit(int nr, volatile unsigned long *addr)
+{
+        unsigned long mask = BIT_MASK(nr);
+        unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+        __atomic_and(p, ~mask);
+}
diff --git a/drivers/gpu/nvgpu/common/posix/bug.c b/drivers/gpu/nvgpu/common/posix/bug.c
new file mode 100644
index 00000000..64f4a6f6
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/bug.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+
+#include <nvgpu/posix/bug.h>
+
+__attribute__ ((noreturn))
+static void __hang(void)
+{
+        nvgpu_err(NULL, "Hanging!");
+
+        while (1)
+                ;
+}
+
+static void __dump_stack(unsigned int skip_frames)
+{
+        return;
+}
+
+void dump_stack(void)
+{
+        __dump_stack(0);
+}
+
+/*
+ * Ahhh! A bug!
+ */
+void __bug(const char *fmt, ...)
+{
+        nvgpu_err(NULL, "BUG detected!");
+
+        __hang();
+}
+
+bool __warn(bool cond, const char *fmt, ...)
+{
+        if (!cond)
+                goto done;
+
+        nvgpu_warn(NULL, "WARNING detected!");
+
+        dump_stack();
+
+done:
+        return cond;
+}
diff --git a/drivers/gpu/nvgpu/common/posix/channel.c b/drivers/gpu/nvgpu/common/posix/channel.c
new file mode 100644
index 00000000..05697159
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/channel.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "gk20a/channel_gk20a.h"
+
+u32 nvgpu_get_gpfifo_entry_size(void)
+{
+        /*
+         * There is no struct nvgpu_gpfifo for us to use yet. But when it's
+         * defined in userspace this is how big it will be.
+         */
+        return 8;
+}
diff --git a/drivers/gpu/nvgpu/common/posix/clk_arb.c b/drivers/gpu/nvgpu/common/posix/clk_arb.c
new file mode 100644
index 00000000..f41383cd
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/clk_arb.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/clk_arb.h>
+
+/**
+ * Stub imlementation of the clk_arb code. Yikes. Much of this probably could be
+ * commonized if one were to think through the implementation but that is
+ * probably weeks of work at a minimum.
+ *
+ * So for POSIX it will be stubbed.
+ */
+
+int nvgpu_clk_arb_init_arbiter(struct gk20a *g)
+{
+        return -ENOSYS;
+}
+
+int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
+                                        u16 *min_mhz, u16 *max_mhz)
+{
+        return -ENOSYS;
+}
+
+int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
+                                         u32 api_domain, u16 *actual_mhz)
+{
+        return -ENOSYS;
+}
+
+int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g,
+                                            u32 api_domain, u16 *effective_mhz)
+{
+        return -ENOSYS;
+}
+
+
+int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
+                                           u32 api_domain,
+                                           u32 *max_points, u16 *fpoints)
+{
+        return -ENOSYS;
+}
+
+u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g)
+{
+        return 0;
+}
+
+bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain)
+{
+        return false;
+}
+
+void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g)
+{
+}
+
+int nvgpu_clk_arb_install_session_fd(struct gk20a *g,
+                                     struct nvgpu_clk_session *session)
+{
+        return -ENOSYS;
+}
+
+
+int nvgpu_clk_arb_init_session(struct gk20a *g,
+                               struct nvgpu_clk_session **_session)
+{
+        return -ENOSYS;
+}
+
+void nvgpu_clk_arb_release_session(struct gk20a *g,
+                                   struct nvgpu_clk_session *session)
+{
+}
+
+int nvgpu_clk_arb_commit_request_fd(struct gk20a *g,
+                                    struct nvgpu_clk_session *session,
+                                    int request_fd)
+{
+        return -ENOSYS;
+}
+
+int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
+                                         int fd, u32 api_domain, u16 target_mhz)
+{
+        return -ENOSYS;
+}
+
+int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
+                                         u32 api_domain, u16 *target_mhz)
+{
+        return -ENOSYS;
+}
+
+int nvgpu_clk_arb_install_event_fd(struct gk20a *g,
+                                   struct nvgpu_clk_session *session,
+                                   int *event_fd, u32 alarm_mask)
+{
+        return -ENOSYS;
+}
+
+int nvgpu_clk_arb_install_request_fd(struct gk20a *g,
+                                     struct nvgpu_clk_session *session,
+                                     int *event_fd)
+{
+        return -ENOSYS;
+}
+
+void nvgpu_clk_arb_schedule_vf_table_update(struct gk20a *g)
+{
+}
+
+int nvgpu_clk_arb_get_current_pstate(struct gk20a *g)
+{
+        return -ENOSYS;
+}
+
+void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock)
+{
+}
+
+void nvgpu_clk_arb_send_thermal_alarm(struct gk20a *g)
+{
+}
+
+void nvgpu_clk_arb_schedule_alarm(struct gk20a *g, u32 alarm)
+{
+}
diff --git a/drivers/gpu/nvgpu/common/posix/cond.c b/drivers/gpu/nvgpu/common/posix/cond.c
new file mode 100644
index 00000000..ca8a2c4a
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/cond.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/cond.h>
+
+#include <nvgpu/posix/cond.h>
+
+int nvgpu_cond_init(struct nvgpu_cond *cond)
+{
+        return -ENOSYS;
+}
+
+int nvgpu_cond_signal(struct nvgpu_cond *cond)
+{
+        return -ENOSYS;
+}
+
+int nvgpu_cond_signal_interruptible(struct nvgpu_cond *cond)
+{
+        return -ENOSYS;
+}
+
+int nvgpu_cond_broadcast(struct nvgpu_cond *cond)
+{
+        return -ENOSYS;
+}
+
+int nvgpu_cond_broadcast_interruptible(struct nvgpu_cond *cond)
+{
+        return -ENOSYS;
+}
+
+void nvgpu_cond_destroy(struct nvgpu_cond *cond)
+{
+
+}
diff --git a/drivers/gpu/nvgpu/common/posix/dma.c b/drivers/gpu/nvgpu/common/posix/dma.c
new file mode 100644
index 00000000..23f59501
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/dma.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <stdlib.h>
+
+#include <nvgpu/mm.h>
+#include <nvgpu/vm.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/dma.h>
+#include <nvgpu/gmmu.h>
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/enabled.h>
+
+/*
+ * In userspace vidmem vs sysmem is just a difference in what is placed in the
+ * aperture field.
+ */
+static int __nvgpu_do_dma_alloc(struct gk20a *g, unsigned long flags,
+                                size_t size, struct nvgpu_mem *mem,
+                                enum nvgpu_aperture ap)
+{
+        void *memory = malloc(mem->aligned_size);
+
+        if (memory == NULL)
+                return -ENOMEM;
+
+        mem->cpu_va       = memory;
+        mem->aperture     = ap;
+        mem->size         = size;
+        mem->aligned_size = PAGE_ALIGN(size);
+        mem->gpu_va       = 0ULL;
+        mem->skip_wmb     = true;
+        mem->vidmem_alloc = NULL;
+        mem->allocator    = NULL;
+
+        return 0;
+}
+
+bool nvgpu_iommuable(struct gk20a *g)
+{
+        return false;
+}
+
+int nvgpu_dma_alloc(struct gk20a *g, size_t size, struct nvgpu_mem *mem)
+{
+        return nvgpu_dma_alloc_flags(g, 0, size, mem);
+}
+
+int nvgpu_dma_alloc_flags(struct gk20a *g, unsigned long flags, size_t size,
+                          struct nvgpu_mem *mem)
+{
+        if (!nvgpu_is_enabled(g, NVGPU_MM_UNIFIED_MEMORY)) {
+                /*
+                 * First try vidmem. Obviously in userspace there's no such
+                 * thing as vidmem per se but we will mark the aperture as
+                 * vidmem.
+                 */
+                int err = nvgpu_dma_alloc_flags_vid(g, 0, size, mem);
+
+                if (!err)
+                        return 0;
+                /*
+                 * Fall back to sysmem (which may then also fail) in case
+                 * vidmem is exhausted.
+                 */
+        }
+
+        return nvgpu_dma_alloc_flags_sys(g, flags, size, mem);
+
+}
+
+int nvgpu_dma_alloc_sys(struct gk20a *g, size_t size, struct nvgpu_mem *mem)
+{
+        return nvgpu_dma_alloc_flags_sys(g, 0, size, mem);
+}
+
+int nvgpu_dma_alloc_flags_sys(struct gk20a *g, unsigned long flags,
+                              size_t size, struct nvgpu_mem *mem)
+{
+        return __nvgpu_do_dma_alloc(g, flags, size, mem, APERTURE_SYSMEM);
+}
+
+int nvgpu_dma_alloc_vid(struct gk20a *g, size_t size, struct nvgpu_mem *mem)
+{
+        return nvgpu_dma_alloc_flags_vid(g, 0, size, mem);
+}
+
+int nvgpu_dma_alloc_flags_vid(struct gk20a *g, unsigned long flags,
+                              size_t size, struct nvgpu_mem *mem)
+{
+        return __nvgpu_do_dma_alloc(g, flags, size, mem, APERTURE_VIDMEM);
+}
+
+int nvgpu_dma_alloc_flags_vid_at(struct gk20a *g, unsigned long flags,
+                                 size_t size, struct nvgpu_mem *mem, u64 at)
+{
+        BUG();
+
+        return 0;
+}
+
+void nvgpu_dma_free(struct gk20a *g, struct nvgpu_mem *mem)
+{
+        if (!(mem->mem_flags & NVGPU_MEM_FLAG_SHADOW_COPY))
+                free(mem->cpu_va);
+
+        memset(mem, 0, sizeof(*mem));
+}
+
+int nvgpu_dma_alloc_map(struct vm_gk20a *vm, size_t size,
+                struct nvgpu_mem *mem)
+{
+        return nvgpu_dma_alloc_map_flags(vm, 0, size, mem);
+}
+
+int nvgpu_dma_alloc_map_flags(struct vm_gk20a *vm, unsigned long flags,
+                size_t size, struct nvgpu_mem *mem)
+{
+        if (!nvgpu_is_enabled(gk20a_from_vm(vm), NVGPU_MM_UNIFIED_MEMORY)) {
+                int err = nvgpu_dma_alloc_map_flags_vid(vm,
+                                flags | NVGPU_DMA_NO_KERNEL_MAPPING,
+                                size, mem);
+
+                if (!err)
+                        return 0;
+                /*
+                 * Fall back to sysmem (which may then also fail) in case
+                 * vidmem is exhausted.
+                 */
+        }
+
+        return nvgpu_dma_alloc_map_flags_sys(vm, flags, size, mem);
+}
+
+int nvgpu_dma_alloc_map_sys(struct vm_gk20a *vm, size_t size,
+                struct nvgpu_mem *mem)
+{
+        return nvgpu_dma_alloc_map_flags_sys(vm, 0, size, mem);
+}
+
+int nvgpu_dma_alloc_map_flags_sys(struct vm_gk20a *vm, unsigned long flags,
+                size_t size, struct nvgpu_mem *mem)
+{
+        int err = nvgpu_dma_alloc_flags_sys(vm->mm->g, flags, size, mem);
+
+        if (err)
+                return err;
+
+        mem->gpu_va = nvgpu_gmmu_map(vm, mem, size, 0,
+                                     gk20a_mem_flag_none, false,
+                                     mem->aperture);
+        if (!mem->gpu_va) {
+                err = -ENOMEM;
+                goto fail_free;
+        }
+
+        return 0;
+
+fail_free:
+        nvgpu_dma_free(vm->mm->g, mem);
+        return err;
+}
+
+int nvgpu_dma_alloc_map_vid(struct vm_gk20a *vm, size_t size,
+                struct nvgpu_mem *mem)
+{
+        return nvgpu_dma_alloc_map_flags_vid(vm,
+                        NVGPU_DMA_NO_KERNEL_MAPPING, size, mem);
+}
+
+int nvgpu_dma_alloc_map_flags_vid(struct vm_gk20a *vm, unsigned long flags,
+                size_t size, struct nvgpu_mem *mem)
+{
+        int err = nvgpu_dma_alloc_flags_vid(vm->mm->g, flags, size, mem);
+
+        if (err)
+                return err;
+
+        mem->gpu_va = nvgpu_gmmu_map(vm, mem, size, 0,
+                                     gk20a_mem_flag_none, false,
+                                     mem->aperture);
+        if (!mem->gpu_va) {
+                err = -ENOMEM;
+                goto fail_free;
+        }
+
+        return 0;
+
+fail_free:
+        nvgpu_dma_free(vm->mm->g, mem);
+        return err;
+}
+
+void nvgpu_dma_unmap_free(struct vm_gk20a *vm, struct nvgpu_mem *mem)
+{
+        if (mem->gpu_va)
+                nvgpu_gmmu_unmap(vm, mem, mem->gpu_va);
+        mem->gpu_va = 0;
+
+        nvgpu_dma_free(vm->mm->g, mem);
+}
diff --git a/drivers/gpu/nvgpu/common/posix/error_notifier.c b/drivers/gpu/nvgpu/common/posix/error_notifier.c
new file mode 100644
index 00000000..50b4f258
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/error_notifier.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/error_notifier.h>
+
+void nvgpu_set_error_notifier_locked(struct channel_gk20a *ch, u32 error)
+{
+}
+
+void nvgpu_set_error_notifier(struct channel_gk20a *ch, u32 error)
+{
+}
+
+void nvgpu_set_error_notifier_if_empty(struct channel_gk20a *ch, u32 error)
+{
+}
+
+bool nvgpu_is_error_notifier_set(struct channel_gk20a *ch, u32 error_notifier)
+{
+        return false;
+}
diff --git a/drivers/gpu/nvgpu/common/posix/firmware.c b/drivers/gpu/nvgpu/common/posix/firmware.c
new file mode 100644
index 00000000..aedfef9f
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/firmware.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/firmware.h>
+
+struct nvgpu_firmware *nvgpu_request_firmware(struct gk20a *g,
+                                              const char *fw_name,
+                                              int flags)
+{
+        return NULL;
+}
+
+void nvgpu_release_firmware(struct gk20a *g, struct nvgpu_firmware *fw)
+{
+        /* Noop. */
+}
diff --git a/drivers/gpu/nvgpu/common/posix/fuse.c b/drivers/gpu/nvgpu/common/posix/fuse.c
new file mode 100644
index 00000000..09ec36dc
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/fuse.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/fuse.h>
+
+int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g)
+{
+        return 0;
+}
+
+void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val)
+{
+}
+
+void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val)
+{
+}
+
+void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val)
+{
+}
+
+void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val)
+{
+}
+
+int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
+{
+        return -ENODEV;
+}
+
+int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
+{
+        return -ENODEV;
+}
diff --git a/drivers/gpu/nvgpu/common/posix/io.c b/drivers/gpu/nvgpu/common/posix/io.c
new file mode 100644
index 00000000..ce018940
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/io.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/io_usermode.h>
+#include <nvgpu/bug.h>
+
+/*
+ * For now none of these make sense to execute in userspace. Eventually we
+ * may want to use these to verify certain register read/write sequences
+ * but for now, just hang.
+ */
+
+void nvgpu_writel(struct gk20a *g, u32 r, u32 v)
+{
+        BUG();
+}
+
+u32 nvgpu_readl(struct gk20a *g, u32 r)
+{
+        BUG();
+
+        return 0;
+}
+
+u32 __nvgpu_readl(struct gk20a *g, u32 r)
+{
+        BUG();
+
+        return 0;
+}
+
+void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v)
+{
+        BUG();
+}
+
+void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v)
+{
+        BUG();
+}
+
+u32 nvgpu_bar1_readl(struct gk20a *g, u32 b)
+{
+        BUG();
+
+        return 0;
+}
+
+bool nvgpu_io_exists(struct gk20a *g)
+{
+        return false;
+}
+
+bool nvgpu_io_valid_reg(struct gk20a *g, u32 r)
+{
+        return false;
+}
+
+void nvgpu_usermode_writel(struct gk20a *g, u32 r, u32 v)
+{
+        BUG();
+}
diff --git a/drivers/gpu/nvgpu/common/posix/kmem.c b/drivers/gpu/nvgpu/common/posix/kmem.c
new file mode 100644
index 00000000..3c0b9b66
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/kmem.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <stdlib.h>
+
+#include <nvgpu/bug.h>
+#include <nvgpu/kmem.h>
+#include <nvgpu/types.h>
+
+#include <nvgpu/posix/kmem.h>
+
+struct nvgpu_kmem_cache {
+        size_t alloc_size;
+};
+
+/*
+ * kmem cache emulation: basically just do a regular malloc(). This is slower
+ * but should not affect a user of kmem cache in the slightest bit.
+ */
+struct nvgpu_kmem_cache *nvgpu_kmem_cache_create(struct gk20a *g, size_t size)
+{
+        struct nvgpu_kmem_cache *cache =
+                malloc(sizeof(struct nvgpu_kmem_cache));
+
+        if (cache != NULL)
+                return NULL;
+
+        cache->alloc_size = size;
+
+        return cache;
+}
+
+void nvgpu_kmem_cache_destroy(struct nvgpu_kmem_cache *cache)
+{
+        free(cache);
+}
+
+void *nvgpu_kmem_cache_alloc(struct nvgpu_kmem_cache *cache)
+{
+        return malloc(cache->alloc_size);
+}
+
+void nvgpu_kmem_cache_free(struct nvgpu_kmem_cache *cache, void *ptr)
+{
+        free(ptr);
+}
+
+void *__nvgpu_kmalloc(struct gk20a *g, size_t size, unsigned long ip)
+{
+        return malloc(size);
+}
+
+void *__nvgpu_kzalloc(struct gk20a *g, size_t size, unsigned long ip)
+{
+        return calloc(1, size);
+}
+
+void *__nvgpu_kcalloc(struct gk20a *g, size_t n, size_t size, unsigned long ip)
+{
+        /*
+         * calloc() implicitly zeros mem. So calloc a single member size bytes
+         * long.
+         */
+        return calloc(n, size);
+}
+
+void __nvgpu_kfree(struct gk20a *g, void *addr)
+{
+        free(addr);
+}
+
+/*
+ * The concept of vmalloc() does not exist in userspace.
+ */
+void *__nvgpu_vmalloc(struct gk20a *g, unsigned long size, unsigned long ip)
+{
+        return __nvgpu_kmalloc(g, size, ip);
+}
+
+void *__nvgpu_vzalloc(struct gk20a *g, unsigned long size, unsigned long ip)
+{
+        return __nvgpu_kzalloc(g, size, ip);
+}
+
+void __nvgpu_vfree(struct gk20a *g, void *addr)
+{
+        __nvgpu_kfree(g, addr);
+}
+
+void *__nvgpu_big_alloc(struct gk20a *g, size_t size, bool clear)
+{
+        /*
+         * Since in userspace vmalloc() == kmalloc() == malloc() we can just
+         * reuse k[zm]alloc() for this.
+         */
+        return clear ?
+                __nvgpu_kzalloc(g, size, _THIS_IP_) :
+                __nvgpu_kmalloc(g, size, _THIS_IP_);
+}
+
+void nvgpu_big_free(struct gk20a *g, void *p)
+{
+        __nvgpu_kfree(g, p);
+}
+
+int nvgpu_kmem_init(struct gk20a *g)
+{
+        /* Nothing to init at the moment. */
+        return 0;
+}
+
+void nvgpu_kmem_fini(struct gk20a *g, int flags)
+{
+
+}
diff --git a/drivers/gpu/nvgpu/common/posix/lock.c b/drivers/gpu/nvgpu/common/posix/lock.c
new file mode 100644
index 00000000..bca0f04c
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/lock.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/lock.h>
+#include <nvgpu/posix/lock.h>
+
+int nvgpu_mutex_init(struct nvgpu_mutex *mutex)
+{
+        return pthread_mutex_init(&mutex->lock.mutex, NULL);
+}
+
+void nvgpu_mutex_acquire(struct nvgpu_mutex *mutex)
+{
+        __nvgpu_posix_lock_acquire(&mutex->lock);
+}
+
+void nvgpu_mutex_release(struct nvgpu_mutex *mutex)
+{
+        __nvgpu_posix_lock_release(&mutex->lock);
+}
+
+int nvgpu_mutex_tryacquire(struct nvgpu_mutex *mutex)
+{
+        return __nvgpu_posix_lock_try_acquire(&mutex->lock);
+}
+
+void nvgpu_mutex_destroy(struct nvgpu_mutex *mutex)
+{
+        pthread_mutex_destroy(&mutex->lock.mutex);
+}
+
+void nvgpu_spinlock_init(struct nvgpu_spinlock *spinlock)
+{
+        pthread_mutex_init(&spinlock->lock.mutex, NULL);
+}
+
+void nvgpu_spinlock_acquire(struct nvgpu_spinlock *spinlock)
+{
+        __nvgpu_posix_lock_acquire(&spinlock->lock);
+}
+
+void nvgpu_spinlock_release(struct nvgpu_spinlock *spinlock)
+{
+        __nvgpu_posix_lock_release(&spinlock->lock);
+}
+
+void nvgpu_raw_spinlock_init(struct nvgpu_raw_spinlock *spinlock)
+{
+        pthread_mutex_init(&spinlock->lock.mutex, NULL);
+}
+
+void nvgpu_raw_spinlock_acquire(struct nvgpu_raw_spinlock *spinlock)
+{
+        __nvgpu_posix_lock_acquire(&spinlock->lock);
+}
+
+void nvgpu_raw_spinlock_release(struct nvgpu_raw_spinlock *spinlock)
+{
+        __nvgpu_posix_lock_release(&spinlock->lock);
+}
diff --git a/drivers/gpu/nvgpu/common/posix/log.c b/drivers/gpu/nvgpu/common/posix/log.c
new file mode 100644
index 00000000..6bfb673c
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/log.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/types.h>
+
+#include "gk20a/gk20a.h"
+
+/*
+ * Define a length for log buffers. This is the buffer that the 'fmt, ...' part
+ * of __nvgpu_do_log_print() prints into.
+ */
+#define LOG_BUFFER_LENGTH       160
+
+/*
+ * Keep this roughly the same as the kernel log format.
+ */
+#define LOG_FMT                 "nvgpu: %s %33s:%-4d [%-4s]  %s\n"
+
+u64 nvgpu_dbg_mask = NVGPU_DEFAULT_DBG_MASK;
+
+static const char *log_types[] = {
+        "ERR",
+        "WRN",
+        "DBG",
+        "INFO",
+};
+
+static inline const char *nvgpu_log_name(struct gk20a *g)
+{
+        return "gpu.USS";
+}
+
+static void __nvgpu_really_print_log(const char *gpu_name,
+                                     const char *func_name, int line,
+                                     enum nvgpu_log_type type, const char *log)
+{
+        const char *name = gpu_name ? gpu_name : "";
+        const char *log_type = log_types[type];
+
+        printf(LOG_FMT, name, func_name, line, log_type, log);
+}
+
+__attribute__((format (printf, 5, 6)))
+void __nvgpu_log_msg(struct gk20a *g, const char *func_name, int line,
+                     enum nvgpu_log_type type, const char *fmt, ...)
+{
+        char log[LOG_BUFFER_LENGTH];
+        va_list args;
+
+        va_start(args, fmt);
+        vsnprintf(log, LOG_BUFFER_LENGTH, fmt, args);
+        va_end(args);
+
+        __nvgpu_really_print_log(nvgpu_log_name(g),
+                                 func_name, line, type, log);
+}
+
+__attribute__((format (printf, 5, 6)))
+void __nvgpu_log_dbg(struct gk20a *g, u64 log_mask,
+                     const char *func_name, int line,
+                     const char *fmt, ...)
+{
+        char log[LOG_BUFFER_LENGTH];
+        va_list args;
+
+        if ((log_mask & g->log_mask) == 0)
+                return;
+
+        va_start(args, fmt);
+        vsnprintf(log, LOG_BUFFER_LENGTH, fmt, args);
+        va_end(args);
+
+        __nvgpu_really_print_log(nvgpu_log_name(g),
+                                 func_name, line, NVGPU_DEBUG, log);
+}
diff --git a/drivers/gpu/nvgpu/common/posix/nvgpu.c b/drivers/gpu/nvgpu/common/posix/nvgpu.c
new file mode 100644
index 00000000..6f2a5fe9
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/nvgpu.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <unistd.h>
+#include <stdlib.h>
+#include <pthread.h>
+
+#include <nvgpu/bug.h>
+#include <nvgpu/types.h>
+#include <nvgpu/atomic.h>
+#include <nvgpu/nvgpu_common.h>
+#include <nvgpu/os_sched.h>
+
+#include <nvgpu/posix/probe.h>
+
+#include "os_posix.h"
+
+#include "gk20a/gk20a.h"
+
+void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
+{
+        /*
+         * No interrupts in userspace so nothing to wait for.
+         */
+}
+
+int nvgpu_current_pid(struct gk20a *g)
+{
+        /*
+         * In the kernel this gets us the PID of the calling process for IOCTLs.
+         * But since we are in userspace this doesn't quite mean the same thing.
+         * This simply returns the PID of the currently running process.
+         */
+        return (int)getpid();
+}
+
+int nvgpu_current_tid(struct gk20a *g)
+{
+        /*
+         * In POSIX thread ID is not the same as a process ID. In Linux threads
+         * and processes are represented by the same thing, but userspace can't
+         * really rely on that.
+         *
+         * We can, however, get a pthread_t for a given thread. But this
+         * pthread_t need not have any relation to the underlying system's
+         * representation of "threads".
+         */
+        return (int)pthread_self();
+}
+
+/*
+ * Somewhat meaningless in userspace...
+ */
+void nvgpu_kernel_restart(void *cmd)
+{
+        BUG();
+}
+
+/*
+ * We have no runtime PM stuff in userspace so these are really just noops.
+ */
+void gk20a_busy_noresume(struct gk20a *g)
+{
+}
+
+void gk20a_idle_nosuspend(struct gk20a *g)
+{
+}
+
+int gk20a_busy(struct gk20a *g)
+{
+        nvgpu_atomic_inc(&g->usage_count);
+
+        return 0;
+}
+
+void gk20a_idle(struct gk20a *g)
+{
+        nvgpu_atomic_dec(&g->usage_count);
+}
+
+/*
+ * This function aims to initialize enough stuff to make unit testing worth
+ * while. There are several interfaces and APIs that rely on the struct gk20a's
+ * state in order to function: logging, for example, but there are many other
+ * things, too.
+ *
+ * Initialize as much of that as possible here. This is meant to be equivalent
+ * to the kernel space driver's probe function.
+ */
+struct gk20a *nvgpu_posix_probe(void)
+{
+        struct gk20a *g;
+        struct nvgpu_os_posix *p;
+        int err;
+
+        p = malloc(sizeof(*p));
+        if (p == NULL)
+                return NULL;
+
+        g = &p->g;
+
+        err = nvgpu_kmem_init(g);
+        if (err != 0)
+                goto fail;
+
+        return g;
+
+fail:
+        free(p);
+
+        return NULL;
+}
+
+void nvgpu_posix_cleanup(struct gk20a *g)
+{
+        nvgpu_kmem_fini(g, 0);
+}
diff --git a/drivers/gpu/nvgpu/common/posix/nvlink.c b/drivers/gpu/nvgpu/common/posix/nvlink.c
new file mode 100644
index 00000000..c830d6ed
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/nvlink.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/nvlink.h>
+
+int nvgpu_nvlink_train(struct gk20a *g, u32 link_id, bool from_off)
+{
+        return -ENOSYS;
+}
+
+int nvgpu_nvlink_enumerate(struct gk20a *g)
+{
+        return -ENOSYS;
+}
diff --git a/drivers/gpu/nvgpu/common/posix/os_posix.h b/drivers/gpu/nvgpu/common/posix/os_posix.h
new file mode 100644
index 00000000..955186ef
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/os_posix.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_OS_POSIX_H__
+#define __NVGPU_OS_POSIX_H__
+
+#include "gk20a/gk20a.h"
+
+struct nvgpu_os_posix {
+        struct gk20a g;
+};
+
+#endif
diff --git a/drivers/gpu/nvgpu/common/posix/posix-comptags.c b/drivers/gpu/nvgpu/common/posix/posix-comptags.c
new file mode 100644
index 00000000..a00246dd
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/posix-comptags.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/bug.h>
+#include <nvgpu/comptags.h>
+
+#include <nvgpu/posix/vm.h>
+
+void gk20a_get_comptags(struct nvgpu_os_buffer *buf,
+                        struct gk20a_comptags *comptags)
+{
+}
+
+int gk20a_alloc_or_get_comptags(struct gk20a *g,
+                                struct nvgpu_os_buffer *buf,
+                                struct gk20a_comptag_allocator *allocator,
+                                struct gk20a_comptags *comptags)
+{
+        return -ENODEV;
+}
+
+bool gk20a_comptags_start_clear(struct nvgpu_os_buffer *buf)
+{
+        return false;
+}
+
+void gk20a_comptags_finish_clear(struct nvgpu_os_buffer *buf,
+                                 bool clear_successful)
+{
+}
diff --git a/drivers/gpu/nvgpu/common/posix/posix-nvgpu_mem.c b/drivers/gpu/nvgpu/common/posix/posix-nvgpu_mem.c
new file mode 100644
index 00000000..f8feb6a2
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/posix-nvgpu_mem.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/bug.h>
+#include <nvgpu/dma.h>
+#include <nvgpu/gmmu.h>
+#include <nvgpu/kmem.h>
+#include <nvgpu/nvgpu_mem.h>
+
+/*
+ * DMA memory buffers - obviously we don't really have DMA in userspace but we
+ * can emulate a lot of the DMA mem functionality for unit testing purposes.
+ */
+
+int nvgpu_mem_begin(struct gk20a *g, struct nvgpu_mem *mem)
+{
+        return 0;
+}
+
+void nvgpu_mem_end(struct gk20a *g, struct nvgpu_mem *mem)
+{
+        return;
+}
+
+u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u32 w)
+{
+        u32 *mem_ptr = (u32 *)mem->cpu_va;
+
+        return mem_ptr[w];
+}
+
+u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset)
+{
+        if (offset & 0x3)
+                BUG();
+
+        return nvgpu_mem_rd32(g, mem, offset >> 2);
+}
+
+void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
+                    void *dest, u32 size)
+{
+        if (offset & 0x3 || size & 0x3)
+                BUG();
+
+        memcpy(dest, ((char *)mem->cpu_va) + offset, size);
+}
+
+void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u32 w, u32 data)
+{
+        u32 *mem_ptr = (u32 *)mem->cpu_va;
+
+        mem_ptr[w] = data;
+}
+
+void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, u32 data)
+{
+        if (offset & 0x3)
+                BUG();
+
+        nvgpu_mem_wr32(g, mem, offset >> 2, data);
+}
+
+void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
+                    void *src, u32 size)
+{
+        if (offset & 0x3 || size & 0x3)
+                BUG();
+
+        memcpy(((char *)mem->cpu_va) + offset, src, size);
+}
+
+void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
+                  u32 c, u32 size)
+{
+        memset(((char *)mem->cpu_va) + offset, c, size);
+}
+
+/*
+ * These functions are somewhat meaningless.
+ */
+u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem)
+{
+        return (u64)(uintptr_t)mem->cpu_va;
+}
+
+u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem)
+{
+        return (u64)(uintptr_t)mem->cpu_va;
+}
+
+static struct nvgpu_sgl *nvgpu_mem_sgl_next(struct nvgpu_sgl *sgl)
+{
+        return NULL;
+}
+
+static u64 nvgpu_mem_sgl_phys(struct gk20a *g, struct nvgpu_sgl *sgl)
+{
+        struct nvgpu_mem *mem = (struct nvgpu_mem *)sgl;
+
+        return (u64)(uintptr_t)mem->cpu_va;
+}
+
+static u64 nvgpu_mem_sgl_dma(struct nvgpu_sgl *sgl)
+{
+        struct nvgpu_mem *mem = (struct nvgpu_mem *)sgl;
+
+        return (u64)(uintptr_t)mem->cpu_va;
+}
+
+static u64 nvgpu_mem_sgl_length(struct nvgpu_sgl *sgl)
+{
+        struct nvgpu_mem *mem = (struct nvgpu_mem *)sgl;
+
+        return (u64)mem->aligned_size;
+}
+
+static u64 nvgpu_mem_sgl_gpu_addr(struct gk20a *g, struct nvgpu_sgl *sgl,
+                                  struct nvgpu_gmmu_attrs *attrs)
+{
+        struct nvgpu_mem *mem = (struct nvgpu_mem *)sgl;
+
+        return mem->gpu_va;
+}
+
+static bool nvgpu_mem_sgt_iommuable(struct gk20a *g, struct nvgpu_sgt *sgt)
+{
+        return nvgpu_iommuable(g);
+}
+
+static void nvgpu_mem_sgt_free(struct gk20a *g, struct nvgpu_sgt *sgt)
+{
+        nvgpu_kfree(g, sgt);
+}
+
+static struct nvgpu_sgt_ops nvgpu_sgt_posix_ops = {
+        .sgl_next       = nvgpu_mem_sgl_next,
+        .sgl_phys       = nvgpu_mem_sgl_phys,
+        .sgl_dma        = nvgpu_mem_sgl_dma,
+        .sgl_length     = nvgpu_mem_sgl_length,
+        .sgl_gpu_addr   = nvgpu_mem_sgl_gpu_addr,
+        .sgt_iommuable  = nvgpu_mem_sgt_iommuable,
+        .sgt_free       = nvgpu_mem_sgt_free,
+};
+
+struct nvgpu_sgt *nvgpu_sgt_create_from_mem(struct gk20a *g,
+                                            struct nvgpu_mem *mem)
+{
+        struct nvgpu_sgt *sgt = nvgpu_kzalloc(g, sizeof(*sgt));
+
+        if (sgt == NULL)
+                return NULL;
+
+        /*
+         * The userspace implementation is simple: a single 'entry' (which we
+         * only need the mem struct to describe). Maybe this could be expanded
+         * to be more interesting some day.
+         */
+        sgt->sgl = (struct nvgpu_sgl *)mem;
+        sgt->ops = &nvgpu_sgt_posix_ops;
+
+        return sgt;
+}
+
+int nvgpu_mem_create_from_mem(struct gk20a *g,
+                              struct nvgpu_mem *dest, struct nvgpu_mem *src,
+                              int start_page, int nr_pages)
+{
+        u64 start = start_page * PAGE_SIZE;
+        u64 size = nr_pages * PAGE_SIZE;
+
+        if (src->aperture != APERTURE_SYSMEM)
+                return -EINVAL;
+
+        /* Some silly things a caller might do... */
+        if (size > src->size)
+                return -EINVAL;
+        if ((start + size) > src->size)
+                return -EINVAL;
+
+        memset(dest, 0, sizeof(*dest));
+
+        dest->cpu_va    = ((char *)src->cpu_va) + start;
+        dest->mem_flags = src->mem_flags | NVGPU_MEM_FLAG_SHADOW_COPY;
+        dest->aperture  = src->aperture;
+        dest->skip_wmb  = src->skip_wmb;
+        dest->size      = size;
+
+        return 0;
+}
diff --git a/drivers/gpu/nvgpu/common/posix/posix-vm.c b/drivers/gpu/nvgpu/common/posix/posix-vm.c
new file mode 100644
index 00000000..588b956d
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/posix-vm.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <stdlib.h>
+
+#include <nvgpu/vm.h>
+#include <nvgpu/bug.h>
+
+#include <nvgpu/posix/vm.h>
+
+u64 nvgpu_os_buf_get_size(struct nvgpu_os_buffer *os_buf)
+{
+        return os_buf->size;
+}
+
+struct nvgpu_mapped_buf *nvgpu_vm_find_mapping(struct vm_gk20a *vm,
+                                               struct nvgpu_os_buffer *os_buf,
+                                               u64 map_addr,
+                                               u32 flags,
+                                               int kind)
+{
+        BUG();
+
+        /*
+         * No map caching for now.
+         */
+        return NULL;
+}
+
+void nvgpu_vm_unmap_system(struct nvgpu_mapped_buf *mapped_buffer)
+{
+        free(mapped_buffer->os_priv.buf);
+}
diff --git a/drivers/gpu/nvgpu/common/posix/rwsem.c b/drivers/gpu/nvgpu/common/posix/rwsem.c
new file mode 100644
index 00000000..7a696b75
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/rwsem.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/bug.h>
+#include <nvgpu/rwsem.h>
+#include <nvgpu/timers.h>
+
+#include <nvgpu/posix/rwsem.h>
+
+void nvgpu_rwsem_init(struct nvgpu_rwsem *rwsem)
+{
+        memset(rwsem, 0, sizeof(*rwsem));
+
+        nvgpu_spinlock_init(&rwsem->lock);
+}
+
+/*
+ * Acquire.
+ */
+void nvgpu_rwsem_down_read(struct nvgpu_rwsem *rwsem)
+{
+        while (true) {
+                nvgpu_spinlock_acquire(&rwsem->lock);
+
+                /*
+                 * If there's a writer try again.
+                 */
+                if (rwsem->writers < 0) {
+                        nvgpu_spinlock_release(&rwsem->lock);
+                        nvgpu_msleep(10);
+                        continue;
+                }
+
+                /*
+                 * Otherwise decrement the read counter and return.
+                 */
+                rwsem->readers -= 1;
+                nvgpu_spinlock_release(&rwsem->lock);
+                return;
+        }
+}
+
+/*
+ * Release.
+ */
+void nvgpu_rwsem_up_read(struct nvgpu_rwsem *rwsem)
+{
+        nvgpu_spinlock_acquire(&rwsem->lock);
+        rwsem->readers += 1;
+
+        /*
+         * Can't be any writers if there was a reader. Also can't be
+         * a positive number of readers. The increments are always
+         * downward so if we have a positive number then there is a
+         * balancing bug.
+         */
+        BUG_ON(rwsem->writers < 0);
+        BUG_ON(rwsem->readers > 0);
+
+        nvgpu_spinlock_release(&rwsem->lock);
+}
+
+void nvgpu_rwsem_down_write(struct nvgpu_rwsem *rwsem)
+{
+        while (true) {
+                nvgpu_spinlock_acquire(&rwsem->lock);
+
+                /*
+                 * If there's a reader or a writer try again. Note: in this very
+                 * simple implementation it's possible for readers to
+                 * indefinitely starve writers.
+                 */
+                if (rwsem->writers < 0 || rwsem->readers < 0) {
+                        nvgpu_spinlock_release(&rwsem->lock);
+                        nvgpu_msleep(10);
+                        continue;
+                }
+
+                rwsem->writers -= 1;
+                nvgpu_spinlock_release(&rwsem->lock);
+                return;
+        }
+}
+
+void nvgpu_rwsem_up_write(struct nvgpu_rwsem *rwsem)
+{
+        nvgpu_spinlock_acquire(&rwsem->lock);
+        rwsem->writers += 1;
+
+        /*
+         * Writers can't be positive: that would be an unbalanced free. Readers
+         * must be zero - otherwise this writer should never have had access!
+         */
+        BUG_ON(rwsem->writers > 0);
+        BUG_ON(rwsem->readers != 0);
+
+        nvgpu_spinlock_release(&rwsem->lock);
+}
diff --git a/drivers/gpu/nvgpu/common/posix/soc.c b/drivers/gpu/nvgpu/common/posix/soc.c
new file mode 100644
index 00000000..0e5c7141
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/soc.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/soc.h>
+
+bool nvgpu_platform_is_silicon(struct gk20a *g)
+{
+        return false;
+}
+
+bool nvgpu_platform_is_simulation(struct gk20a *g)
+{
+        return false;
+}
+
+bool nvgpu_platform_is_fpga(struct gk20a *g)
+{
+        return false;
+}
+
+bool nvgpu_is_hypervisor_mode(struct gk20a *g)
+{
+        return false;
+}
+
+bool nvgpu_is_bpmp_running(struct gk20a *g)
+{
+        return false;
+}
diff --git a/drivers/gpu/nvgpu/common/posix/stubs.c b/drivers/gpu/nvgpu/common/posix/stubs.c
new file mode 100644
index 00000000..d6270692
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/stubs.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * Here lie OS stubs that do not have an implementation yet nor has any plans
+ * for an implementation.
+ */
+
+#include "gk20a/dbg_gpu_gk20a.h"
+
+void nvgpu_dbg_session_post_event(struct dbg_session_gk20a *dbg_s)
+{
+}
diff --git a/drivers/gpu/nvgpu/common/posix/thread.c b/drivers/gpu/nvgpu/common/posix/thread.c
new file mode 100644
index 00000000..d9476523
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/thread.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/bug.h>
+#include <nvgpu/thread.h>
+
+#include <nvgpu/posix/thread.h>
+
+/**
+ * Use pthreads to mostly emulate the Linux kernel APIs. There are some things
+ * that are quite different - especially the stop/should_stop notions. In user
+ * space threads can send signals to one another but of course within the kernel
+ * that is not as simple.
+ *
+ * This could use some nice debugging some day as well.
+ */
+
+/*
+ * nvgpu thread functions return int. POSIX threads return void *. This little
+ * wrapper takes the int returning nvgpu thread and instead passes that int back
+ * through the void * pointer.
+ */
+static void *__nvgpu_posix_thread_wrapper(void *data)
+{
+        struct nvgpu_posix_thread_data *nvgpu = data;
+
+        return ERR_PTR(nvgpu->fn(nvgpu->data));
+}
+
+int nvgpu_thread_create(struct nvgpu_thread *thread,
+                        void *data,
+                        int (*threadfn)(void *data), const char *name)
+{
+        int ret;
+
+        BUG_ON(thread->running);
+
+        memset(thread, 0, sizeof(*thread));
+
+        /*
+         * By subtracting 1 the above memset ensures that we have a zero
+         * terminated string.
+         */
+        strncpy(thread->tname, name, NVGPU_THREAD_POSIX_MAX_NAMELEN - 1);
+
+        thread->nvgpu.data = data;
+        thread->nvgpu.fn = threadfn;
+
+        ret = pthread_create(&thread->thread, NULL,
+                             __nvgpu_posix_thread_wrapper,
+                             &thread->nvgpu);
+        if (ret != 0)
+                return ret;
+
+#ifdef _GNU_SOURCE
+        pthread_setname_np(thread->thread, thread->tname);
+#endif
+
+        thread->running = true;
+
+        return 0;
+}
+
+void nvgpu_thread_stop(struct nvgpu_thread *thread)
+{
+        thread->should_stop = true;
+}
+
+bool nvgpu_thread_should_stop(struct nvgpu_thread *thread)
+{
+        return thread->should_stop;
+}
+
+bool nvgpu_thread_is_running(struct nvgpu_thread *thread)
+{
+        return thread->running;
+}
diff --git a/drivers/gpu/nvgpu/common/posix/timers.c b/drivers/gpu/nvgpu/common/posix/timers.c
new file mode 100644
index 00000000..c84b0de5
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/timers.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <sys/time.h>
+
+#include <nvgpu/bug.h>
+#include <nvgpu/log.h>
+#include <nvgpu/timers.h>
+
+static s64 now(void)
+{
+        return nvgpu_current_time_ms();
+}
+
+/*
+ * Returns true if a > b;
+ */
+static bool time_after(s64 a, s64 b)
+{
+        return a - b > 0;
+}
+
+int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout,
+                       u32 duration, unsigned long flags)
+{
+        if (flags & ~NVGPU_TIMER_FLAG_MASK)
+                return -EINVAL;
+
+        memset(timeout, 0, sizeof(*timeout));
+
+        timeout->g = g;
+        timeout->flags = flags;
+
+        if (flags & NVGPU_TIMER_RETRY_TIMER)
+                timeout->retries.max = duration;
+        else
+                timeout->time = nvgpu_current_time_ms() + (s64)duration;
+
+        return 0;
+}
+
+static int __nvgpu_timeout_expired_msg_cpu(struct nvgpu_timeout *timeout,
+                                         void *caller,
+                                         const char *fmt, va_list args)
+{
+        struct gk20a *g = timeout->g;
+
+        if (time_after(now(), timeout->time)) {
+                if (!(timeout->flags & NVGPU_TIMER_SILENT_TIMEOUT)) {
+                        char buf[128];
+
+                        vsnprintf(buf, sizeof(buf), fmt, args);
+
+                        nvgpu_err(g, "Timeout detected @ %p %s", caller, buf);
+                }
+
+                return -ETIMEDOUT;
+        }
+
+        return 0;
+}
+
+static int __nvgpu_timeout_expired_msg_retry(struct nvgpu_timeout *timeout,
+                                           void *caller,
+                                           const char *fmt, va_list args)
+{
+        struct gk20a *g = timeout->g;
+
+        if (timeout->retries.attempted >= timeout->retries.max) {
+                if (!(timeout->flags & NVGPU_TIMER_SILENT_TIMEOUT)) {
+                        char buf[128];
+
+                        vsnprintf(buf, sizeof(buf), fmt, args);
+
+                        nvgpu_err(g, "No more retries @ %p %s", caller, buf);
+                }
+
+                return -ETIMEDOUT;
+        }
+
+        timeout->retries.attempted++;
+
+        return 0;
+}
+
+int __nvgpu_timeout_expired_msg(struct nvgpu_timeout *timeout,
+                              void *caller, const char *fmt, ...)
+{
+        int ret;
+        va_list args;
+
+        va_start(args, fmt);
+        if (timeout->flags & NVGPU_TIMER_RETRY_TIMER)
+                ret = __nvgpu_timeout_expired_msg_retry(timeout, caller, fmt,
+                                                      args);
+        else
+                ret = __nvgpu_timeout_expired_msg_cpu(timeout, caller, fmt,
+                                                    args);
+        va_end(args);
+
+        return ret;
+}
+
+int nvgpu_timeout_peek_expired(struct nvgpu_timeout *timeout)
+{
+        if (timeout->flags & NVGPU_TIMER_RETRY_TIMER)
+                return timeout->retries.attempted >= timeout->retries.max;
+        else
+                return time_after(now(), timeout->time);
+}
+
+void nvgpu_udelay(unsigned int usecs)
+{
+        BUG();
+}
+
+void nvgpu_usleep_range(unsigned int min_us, unsigned int max_us)
+{
+        BUG();
+}
+
+void nvgpu_msleep(unsigned int msecs)
+{
+        BUG();
+}
+
+static inline s64 __nvgpu_current_time_us(void)
+{
+        struct timeval now;
+        s64 time_now;
+        int ret;
+
+        ret = gettimeofday(&now, NULL);
+        if (ret != 0)
+                BUG();
+
+        time_now = ((s64)now.tv_sec * (s64)1000000) + (s64)now.tv_usec;
+
+        return time_now;
+}
+
+s64 nvgpu_current_time_ms(void)
+{
+        return __nvgpu_current_time_us() / (s64)1000;
+}
+
+u64 nvgpu_hr_timestamp(void)
+{
+        return __nvgpu_current_time_us();
+}
diff --git a/drivers/gpu/nvgpu/common/posix/tsg.c b/drivers/gpu/nvgpu/common/posix/tsg.c
new file mode 100644
index 00000000..8736123d
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/tsg.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "gk20a/tsg_gk20a.h"
+
+void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg,
+                                       int __event_id)
+{
+}
diff --git a/drivers/gpu/nvgpu/include/nvgpu/atomic.h b/drivers/gpu/nvgpu/include/nvgpu/atomic.h
index 0f319f71..12d1c86e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/atomic.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/atomic.h
@@ -24,6 +24,8 @@
 
 #ifdef __KERNEL__
 #include <nvgpu/linux/atomic.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/atomic.h>
 #else
 #include <nvgpu_rmos/include/atomic.h>
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/barrier.h b/drivers/gpu/nvgpu/include/nvgpu/barrier.h
index 03a14a99..49b10b86 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/barrier.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/barrier.h
@@ -30,6 +30,8 @@
 
 #ifdef __KERNEL__
 #include <nvgpu/linux/barrier.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/barrier.h>
 #else
 #include <nvgpu_rmos/include/barrier.h>
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bitops.h b/drivers/gpu/nvgpu/include/nvgpu/bitops.h
index d3bac60e..26b6e19d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bitops.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bitops.h
@@ -25,6 +25,8 @@
 #ifdef __KERNEL__
 #include <linux/bitops.h>
 #include <linux/bitmap.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/bitops.h>
 #else
 #include <nvgpu_rmos/include/bitops.h>
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bsearch.h b/drivers/gpu/nvgpu/include/nvgpu/bsearch.h
index b02cc85c..872701e6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bsearch.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bsearch.h
@@ -24,6 +24,8 @@
 
 #ifdef __KERNEL__
 #include <linux/bsearch.h>
+#elif defined(__NVGPU_POSIX__)
+#include <stdlib.h>
 #endif
 
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bug.h b/drivers/gpu/nvgpu/include/nvgpu/bug.h
index ea62c6d8..671439a1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bug.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bug.h
@@ -24,6 +24,8 @@
 
 #ifdef __KERNEL__
 #include <linux/bug.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/bug.h>
 #else
 #include <nvgpu_rmos/include/bug.h>
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/circ_buf.h b/drivers/gpu/nvgpu/include/nvgpu/circ_buf.h
index c6620663..4dd9e0d8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/circ_buf.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/circ_buf.h
@@ -24,6 +24,8 @@
 
 #ifdef __KERNEL__
 #include <linux/circ_buf.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/circ_buf.h>
 #endif
 
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/cond.h b/drivers/gpu/nvgpu/include/nvgpu/cond.h
index b6f2598e..340fb460 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/cond.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/cond.h
@@ -25,6 +25,8 @@
 
 #ifdef __KERNEL__
 #include <nvgpu/linux/cond.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/cond.h>
 #else
 #include <nvgpu_rmos/include/cond.h>
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/kmem.h b/drivers/gpu/nvgpu/include/nvgpu/kmem.h
index fef837cf..91574ce0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/kmem.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/kmem.h
@@ -40,6 +40,8 @@ struct gk20a;
  */
 #ifdef __KERNEL__
 #include <nvgpu/linux/kmem.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/kmem.h>
 #else
 #include <nvgpu_rmos/include/kmem.h>
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/lock.h b/drivers/gpu/nvgpu/include/nvgpu/lock.h
index bccded57..7e4b2ac3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/lock.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/lock.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,8 @@
 
 #ifdef __KERNEL__
 #include <nvgpu/linux/lock.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/lock.h>
 #else
 #include <nvgpu_rmos/include/lock.h>
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/log.h b/drivers/gpu/nvgpu/include/nvgpu/log.h
index 897dcfc6..87ab17ee 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/log.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/log.h
@@ -106,7 +106,7 @@ int nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask);
  * Print a message if the log_mask matches the enabled debugging.
  */
 #define nvgpu_log(g, log_mask, fmt, arg...)                             \
-        __nvgpu_log_dbg(g, log_mask, __func__, __LINE__, fmt, ##arg)
+        __nvgpu_log_dbg(g, (u32)log_mask, __func__, __LINE__, fmt, ##arg)
 
 /**
  * nvgpu_err - Print an error
diff --git a/drivers/gpu/nvgpu/include/nvgpu/log2.h b/drivers/gpu/nvgpu/include/nvgpu/log2.h
index 827162f8..57b77217 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/log2.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/log2.h
@@ -24,6 +24,8 @@
 
 #ifdef __KERNEL__
 #include <linux/log2.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/log2.h>
 #endif
 
 #endif /* __NVGPU_LOG2_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
index c5e3e752..93fce81e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
@@ -29,6 +29,8 @@
 
 #ifdef __KERNEL__
 #include <nvgpu/linux/nvgpu_mem.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/nvgpu_mem.h>
 #else
 #include <nvgpu_rmos/include/nvgpu_mem.h>
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/atomic.h b/drivers/gpu/nvgpu/include/nvgpu/posix/atomic.h
new file mode 100644
index 00000000..c9d92128
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/atomic.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_ATOMIC_H__
+#define __NVGPU_POSIX_ATOMIC_H__
+
+#include <nvgpu/types.h>
+
+/*
+ * Note: this code uses the GCC builtins to implement atomics.
+ */
+
+#define __atomic_cmpxchg(p, v, c)       __sync_val_compare_and_swap(p, v, c)
+#define __atomic_and(p, v)              __sync_fetch_and_and(p, v)
+#define __atomic_or(p, v)               __sync_fetch_and_or(p, v)
+
+#define cmpxchg                         __atomic_cmpxchg
+
+/*
+ * Place holders until real atomics can be implemented... Yay for GCC builtins!
+ * We can use those eventually to define all the Linux atomic ops.
+ *
+ * TODO: make these _actually_ atomic!
+ */
+typedef struct __nvgpu_posix_atomic {
+        int v;
+} nvgpu_atomic_t;
+
+typedef struct __nvgpu_posix_atomic64 {
+        long v;
+} nvgpu_atomic64_t;
+
+#define __nvgpu_atomic_init(i)          { i }
+#define __nvgpu_atomic64_init(i)        { i }
+
+static inline void __nvgpu_atomic_set(nvgpu_atomic_t *v, int i)
+{
+        v->v = i;
+}
+
+static inline int __nvgpu_atomic_read(nvgpu_atomic_t *v)
+{
+        return v->v;
+}
+
+static inline void __nvgpu_atomic_inc(nvgpu_atomic_t *v)
+{
+        v->v++;
+}
+
+static inline int __nvgpu_atomic_inc_return(nvgpu_atomic_t *v)
+{
+        v->v++;
+        return v->v;
+}
+
+static inline void __nvgpu_atomic_dec(nvgpu_atomic_t *v)
+{
+        v->v--;
+}
+
+static inline int __nvgpu_atomic_dec_return(nvgpu_atomic_t *v)
+{
+        v->v--;
+        return v->v;
+}
+
+static inline int __nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new)
+{
+        if (v->v == old)
+                v->v = new;
+
+        return v->v;
+}
+
+static inline int __nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new)
+{
+        v->v = new;
+        return new;
+}
+
+static inline bool __nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v)
+{
+        v->v++;
+        return v->v ? true : false;
+}
+
+static inline bool __nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v)
+{
+        v->v--;
+        return v->v ? true : false;
+}
+
+static inline bool __nvgpu_atomic_sub_and_test(int i, nvgpu_atomic_t *v)
+{
+        v->v -= i;
+        return v->v ? true : false;
+}
+
+static inline int __nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v)
+{
+        v->v += i;
+        return v->v;
+}
+
+static inline int __nvgpu_atomic_add_unless(nvgpu_atomic_t *v, int a, int u)
+{
+        if (v->v != u)
+                v->v += a;
+
+        return v->v;
+}
+
+static inline void __nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i)
+{
+        v->v = i;
+}
+
+static inline long __nvgpu_atomic64_read(nvgpu_atomic64_t *v)
+{
+        return v->v;
+}
+
+static inline void __nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v)
+{
+        v->v += x;
+}
+
+static inline void __nvgpu_atomic64_inc(nvgpu_atomic64_t *v)
+{
+        v->v++;
+}
+
+static inline long __nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v)
+{
+        v->v++;
+        return v->v;
+}
+
+static inline void __nvgpu_atomic64_dec(nvgpu_atomic64_t *v)
+{
+        v->v--;
+}
+
+static inline long __nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v)
+{
+        v->v--;
+        return v->v;
+}
+
+static inline long __nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v,
+                                        long old, long new)
+{
+
+        if (v->v == old)
+                v->v = new;
+
+        return v->v;
+}
+
+static inline void __nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v)
+{
+        v->v -= x;
+}
+
+static inline long __nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v)
+{
+        v->v -= x;
+        return v->v;
+}
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/barrier.h b/drivers/gpu/nvgpu/include/nvgpu/posix/barrier.h
new file mode 100644
index 00000000..edc7b129
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/barrier.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_BARRIER_H__
+#define __NVGPU_POSIX_BARRIER_H__
+
+#define ACCESS_ONCE(x)  (*(volatile __typeof__(x) *)&x)
+
+/*
+ * TODO: implement all these!
+ */
+#define __nvgpu_mb()
+#define __nvgpu_rmb()
+#define __nvgpu_wmb()
+
+#define __nvgpu_smp_mb()
+#define __nvgpu_smp_rmb()
+#define __nvgpu_smp_wmb()
+
+#define __nvgpu_read_barrier_depends()
+#define __nvgpu_smp_read_barrier_depends()
+
+#define __NV_ACCESS_ONCE(x)     ACCESS_ONCE(x)
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h b/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h
new file mode 100644
index 00000000..bfc6fef1
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_BITOPS_H__
+#define __NVGPU_POSIX_BITOPS_H__
+
+#include <nvgpu/types.h>
+
+/*
+ * Assume an 8 bit byte, of course.
+ */
+#define BITS_PER_BYTE   8UL
+#define BITS_PER_LONG   (__SIZEOF_LONG__ * BITS_PER_BYTE)
+#define BITS_TO_LONGS(bits)                     \
+        (bits + (BITS_PER_LONG - 1) / BITS_PER_LONG)
+
+#define BIT(i)          (1UL << (i))
+
+#define GENMASK(h, l) \
+        (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
+
+#define DECLARE_BITMAP(bmap, bits)              \
+        unsigned long bmap[BITS_TO_LONGS(bits)]
+
+#define for_each_set_bit(bit, addr, size) \
+        for ((bit) = find_first_bit((addr), (size));            \
+             (bit) < (size);                                    \
+             (bit) = find_next_bit((addr), (size), (bit) + 1))
+
+#define ffs(word)       __ffs(word)
+#define ffz(word)       __ffs(~(word))
+#define fls(word)       __fls(word)
+
+/*
+ * Clashes with symbols in libc it seems.
+ */
+#define __ffs(word)     __nvgpu_posix_ffs(word)
+#define __fls(word)     __nvgpu_posix_fls(word)
+
+unsigned long __nvgpu_posix_ffs(unsigned long word);
+unsigned long __nvgpu_posix_fls(unsigned long word);
+
+unsigned long find_first_bit(const unsigned long *addr, unsigned long size);
+unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
+                            unsigned long offset);
+unsigned long find_first_zero_bit(const unsigned long *addr,
+                                  unsigned long size);
+
+bool test_bit(int nr, const volatile unsigned long *addr);
+bool test_and_set_bit(int nr, volatile unsigned long *addr);
+bool test_and_clear_bit(int nr, volatile unsigned long *addr);
+
+/*
+ * These two are atomic.
+ */
+void set_bit(int nr, volatile unsigned long *addr);
+void clear_bit(int nr, volatile unsigned long *addr);
+
+void bitmap_set(unsigned long *map, unsigned int start, int len);
+void bitmap_clear(unsigned long *map, unsigned int start, int len);
+unsigned long bitmap_find_next_zero_area_off(unsigned long *map,
+                                             unsigned long size,
+                                             unsigned long start,
+                                             unsigned int nr,
+                                             unsigned long align_mask,
+                                             unsigned long align_offset);
+unsigned long bitmap_find_next_zero_area(unsigned long *map,
+                                         unsigned long size,
+                                         unsigned long start,
+                                         unsigned int nr,
+                                         unsigned long align_mask);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/bug.h b/drivers/gpu/nvgpu/include/nvgpu/posix/bug.h
new file mode 100644
index 00000000..04389a90
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/bug.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_BUG_H__
+#define __NVGPU_POSIX_BUG_H__
+
+#include <nvgpu/types.h>
+
+/*
+ * TODO: make these actually useful!
+ */
+
+#define BUG()                                   __bug("")
+#define BUG_ON(cond)                            \
+        do {                                    \
+                if (cond)                       \
+                        BUG();                  \
+        } while (0)
+
+#define WARN(cond, msg, arg...)                 __warn(cond, msg, ##arg)
+#define WARN_ON(cond)                           __warn(cond, "")
+
+#define WARN_ONCE(cond, msg, arg...)            \
+        ({static int __warned__ = 0;            \
+          if (!__warned__) {                    \
+                  WARN(cond, msg, ##arg);       \
+                  __warned__ = 1;               \
+          }                                     \
+          cond; })
+
+
+void dump_stack(void);
+
+void __bug(const char *fmt, ...) __attribute__ ((noreturn));
+bool __warn(bool cond, const char *fmt, ...);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/circ_buf.h b/drivers/gpu/nvgpu/include/nvgpu/posix/circ_buf.h
new file mode 100644
index 00000000..8d9b5ea0
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/circ_buf.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_CIRC_BUF_H__
+#define __NVGPU_POSIX_CIRC_BUF_H__
+
+#include <nvgpu/bug.h>
+
+/* TODO: implement. */
+
+#define CIRC_CNT(head, tail, size)              \
+        ({(void)head;                           \
+          (void)tail;                           \
+          (void)size;                           \
+          BUG();                                \
+          1; })
+
+#define CIRC_SPACE(head, tail, size)            \
+        ({(void)head;                           \
+          (void)tail;                           \
+          (void)size;                           \
+          BUG();                                \
+          1; })
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/cond.h b/drivers/gpu/nvgpu/include/nvgpu/posix/cond.h
new file mode 100644
index 00000000..3528388b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/cond.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_COND_H__
+#define __NVGPU_POSIX_COND_H__
+
+#include <nvgpu/bug.h>
+
+struct nvgpu_cond {
+        /* Place holder until this can be properly implemented. */
+};
+
+/**
+ * NVGPU_COND_WAIT - Wait for a condition to be true
+ *
+ * @c - The condition variable to sleep on
+ * @condition - The condition that needs to be true
+ * @timeout_ms - Timeout in milliseconds, or 0 for infinite wait
+ *
+ * Wait for a condition to become true. Returns -ETIMEOUT if
+ * the wait timed out with condition false.
+ */
+#define NVGPU_COND_WAIT(c, condition, timeout_ms)       \
+        ({BUG(); 1; })
+
+/**
+ * NVGPU_COND_WAIT_INTERRUPTIBLE - Wait for a condition to be true
+ *
+ * @c - The condition variable to sleep on
+ * @condition - The condition that needs to be true
+ * @timeout_ms - Timeout in milliseconds, or 0 for infinite wait
+ *
+ * Wait for a condition to become true. Returns -ETIMEOUT if
+ * the wait timed out with condition false or -ERESTARTSYS on
+ * signal.
+ */
+#define NVGPU_COND_WAIT_INTERRUPTIBLE(c, condition, timeout_ms) \
+        ({BUG(); 1; })
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/kmem.h b/drivers/gpu/nvgpu/include/nvgpu/posix/kmem.h
new file mode 100644
index 00000000..483ac3b3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/kmem.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_KMEM_H__
+#define __NVGPU_POSIX_KMEM_H__
+
+#include <nvgpu/types.h>
+
+void *__nvgpu_kmalloc(struct gk20a *g, size_t size, unsigned long ip);
+void *__nvgpu_kzalloc(struct gk20a *g, size_t size, unsigned long ip);
+void *__nvgpu_kcalloc(struct gk20a *g, size_t n, size_t size, unsigned long ip);
+void *__nvgpu_vmalloc(struct gk20a *g, unsigned long size, unsigned long ip);
+void *__nvgpu_vzalloc(struct gk20a *g, unsigned long size, unsigned long ip);
+void __nvgpu_kfree(struct gk20a *g, void *addr);
+void __nvgpu_vfree(struct gk20a *g, void *addr);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/lock.h b/drivers/gpu/nvgpu/include/nvgpu/posix/lock.h
new file mode 100644
index 00000000..82eddd02
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/lock.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_LOCK_H__
+#define __NVGPU_POSIX_LOCK_H__
+
+#include <stdlib.h>
+
+#include <pthread.h>
+
+/*
+ * All locks for posix nvgpu are just pthread locks. There's not a lot of reason
+ * to have real spinlocks in userspace since we aren't using real HW or running
+ * perf critical code where a sleep could be devestating.
+ *
+ * This could be revisited later, though.
+ */
+struct __nvgpu_posix_lock {
+        pthread_mutex_t mutex;
+};
+
+static inline void __nvgpu_posix_lock_acquire(struct __nvgpu_posix_lock *lock)
+{
+        pthread_mutex_lock(&lock->mutex);
+}
+
+static inline int __nvgpu_posix_lock_try_acquire(
+        struct __nvgpu_posix_lock *lock)
+{
+        return pthread_mutex_trylock(&lock->mutex);
+}
+
+static inline void __nvgpu_posix_lock_release(struct __nvgpu_posix_lock *lock)
+{
+        pthread_mutex_unlock(&lock->mutex);
+}
+
+struct nvgpu_mutex {
+        struct __nvgpu_posix_lock lock;
+};
+
+struct nvgpu_spinlock {
+        struct __nvgpu_posix_lock lock;
+};
+
+struct nvgpu_raw_spinlock {
+        struct __nvgpu_posix_lock lock;
+};
+
+#endif /* NVGPU_LOCK_LINUX_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/log2.h b/drivers/gpu/nvgpu/include/nvgpu/posix/log2.h
new file mode 100644
index 00000000..ca95c10a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/log2.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_LOG2_H__
+#define __NVGPU_POSIX_LOG2_H__
+
+#define ilog2(x)                        (fls(x) - 1)
+
+#define roundup_pow_of_two(x)           (1UL << fls((x) - 1))
+#define rounddown_pow_of_two(x)         (1UL << (fls(x) - 1))
+
+#define is_power_of_2(x)                                        \
+        ({                                                      \
+                typeof(x) __x__ = (x);                          \
+                (__x__ != 0 && ((__x__ & (__x__ - 1)) == 0));   \
+        })
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/posix/nvgpu_mem.h
new file mode 100644
index 00000000..30cdf60f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/nvgpu_mem.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_NVGPU_MEM_H__
+#define __NVGPU_POSIX_NVGPU_MEM_H__
+
+struct nvgpu_mem_priv {
+        /*
+         * Eventually this will require an implementation using nvmap.
+         */
+};
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/probe.h b/drivers/gpu/nvgpu/include/nvgpu/posix/probe.h
new file mode 100644
index 00000000..a9763aa9
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/probe.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_PROBE_H__
+#define __NVGPU_POSIX_PROBE_H__
+
+struct gk20a;
+
+struct gk20a *nvgpu_posix_probe(void);
+void nvgpu_posix_cleanup(struct gk20a *g);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/rwsem.h b/drivers/gpu/nvgpu/include/nvgpu/posix/rwsem.h
new file mode 100644
index 00000000..65aa931b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/rwsem.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_RWSEM_H__
+#define __NVGPU_POSIX_RWSEM_H__
+
+#include <nvgpu/lock.h>
+
+struct nvgpu_rwsem {
+        struct nvgpu_spinlock lock;
+
+        int readers;
+        int writers;
+};
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/sizes.h b/drivers/gpu/nvgpu/include/nvgpu/posix/sizes.h
new file mode 100644
index 00000000..3fda7574
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/sizes.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_SIZES_H__
+#define __NVGPU_POSIX_SIZES_H__
+
+#define SZ_1K           (1UL << 10)
+#define SZ_4K           (SZ_1K << 2)
+#define SZ_64K          (SZ_1K << 6)
+#define SZ_128K         (SZ_1K << 7)
+
+#define SZ_1M           (1UL << 20)
+#define SZ_16M          (SZ_1M << 4)
+#define SZ_256M         (SZ_1M << 8)
+
+#define SZ_1G           (1UL << 30)
+#define SZ_4G           (SZ_1G << 2)
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/sort.h b/drivers/gpu/nvgpu/include/nvgpu/posix/sort.h
new file mode 100644
index 00000000..6a6920eb
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/sort.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_SORT_H__
+#define __NVGPU_POSIX_SORT_H__
+
+#include <nvgpu/bug.h>
+
+static void sort(void *base, size_t num, size_t size,
+                 int (*cmp)(const void *, const void *),
+                 void (*swap)(void *, void *, int))
+{
+        __bug("sort() not implemented yet!");
+}
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/thread.h b/drivers/gpu/nvgpu/include/nvgpu/posix/thread.h
new file mode 100644
index 00000000..a312cc13
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/thread.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_THREAD_H__
+#define __NVGPU_POSIX_THREAD_H__
+
+#include <pthread.h>
+
+#include <nvgpu/types.h>
+
+/*
+ * Handles passing an nvgpu thread function into a posix thread.
+ */
+struct nvgpu_posix_thread_data {
+        int (*fn)(void *data);
+        void *data;
+};
+
+/*
+ * For some reason POSIX only allows 16 bytes of name length.
+ */
+#define NVGPU_THREAD_POSIX_MAX_NAMELEN          16
+
+struct nvgpu_thread {
+        bool running;
+        bool should_stop;
+        pthread_t thread;
+        struct nvgpu_posix_thread_data nvgpu;
+        char tname[16];
+};
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/types.h b/drivers/gpu/nvgpu/include/nvgpu/posix/types.h
new file mode 100644
index 00000000..3dfcec6c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/types.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_TYPES_H__
+#define __NVGPU_POSIX_TYPES_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include <errno.h>
+#include <limits.h>
+#include <string.h>
+#include <strings.h>
+#include <stdio.h>
+#include <stdarg.h>
+
+/*
+ * For endianness functions.
+ */
+#include <netinet/in.h>
+
+typedef unsigned char           __u8;
+typedef unsigned short          __u16;
+typedef unsigned int            __u32;
+typedef unsigned long long      __u64;
+
+typedef __u8                    u8;
+typedef __u16                   u16;
+typedef __u32                   u32;
+typedef __u64                   u64;
+
+typedef char                    s8;
+typedef short                   s16;
+typedef int                     s32;
+typedef long long               s64;
+
+#define min_t(type, a, b)               \
+        ({                              \
+                type __a = (a);         \
+                type __b = (b);         \
+                __a < __b ? __a : __b;  \
+        })
+
+#define min(a, b)                       \
+        ({                              \
+                (a) < (b) ? a : b;      \
+        })
+#define min3(a, b, c)                   min(min(a, b), c)
+
+#define max(a, b)                       \
+        ({                              \
+                (a) > (b) ? a : b;      \
+        })
+
+#define PAGE_SIZE       4096
+
+#define ARRAY_SIZE(array)                       \
+        (sizeof(array) / sizeof((array)[0]))
+
+#define MAX_SCHEDULE_TIMEOUT    LONG_MAX
+
+#define DIV_ROUND_UP(n, d)      (((n) + (d) - 1) / (d))
+
+/*
+ * Only used in clk_gm20b.c which we will never unit test. Don't use!
+ */
+#define DIV_ROUND_CLOSEST(x, divisor)   ({BUG(); 0; })
+
+/*
+ * Joys of userspace: usually division just works since the compiler can link
+ * against external division functions implicitly.
+ */
+#define do_div(a, b)            ((a) /= (b))
+#define div64_u64(a, b)         ((a) / (b))
+
+#define __round_mask(x, y)      ((__typeof__(x))((y) - 1))
+#define round_up(x, y)          ((((x) - 1) | __round_mask(x, y)) + 1)
+#define roundup(x, y)           round_up(x, y)
+#define round_down(x, y)        ((x) & ~__round_mask(x, y))
+
+#define ALIGN_MASK(x, mask)     (((x) + (mask)) & ~(mask))
+#define ALIGN(x, a)             ALIGN_MASK(x, (typeof(x))(a) - 1)
+#define PAGE_ALIGN(x)           ALIGN(x, PAGE_SIZE)
+
+/*
+ * Caps return at the size of the buffer not what would have been written if buf
+ * were arbitrarily sized.
+ */
+static inline int scnprintf(char *buf, size_t size, const char *format, ...)
+{
+        size_t ret;
+        va_list args;
+
+        va_start(args, format);
+        ret = vsnprintf(buf, size, format, args);
+        va_end(args);
+
+        return ret <= size ? ret : size;
+}
+
+static inline u32 be32_to_cpu(u32 x)
+{
+        /*
+         * Conveniently big-endian happens to be network byte order as well so
+         * we can use ntohl() for this.
+         */
+        return ntohl(x);
+}
+
+/*
+ * Hamming weights.
+ */
+static inline unsigned long __hweight8(uint8_t x)
+{
+        return (unsigned long)(!!(x & (1 << 0)) +
+                               !!(x & (1 << 1)) +
+                               !!(x & (1 << 2)) +
+                               !!(x & (1 << 3)) +
+                               !!(x & (1 << 4)) +
+                               !!(x & (1 << 5)) +
+                               !!(x & (1 << 6)) +
+                               !!(x & (1 << 7)));
+}
+
+static inline unsigned long __hweight16(uint16_t x)
+{
+        return __hweight8((uint8_t)x) +
+                __hweight8((uint8_t)((x & 0xff00) >> 8));
+}
+
+static inline unsigned long __hweight32(uint32_t x)
+{
+        return __hweight16((uint16_t)x) +
+                __hweight16((uint16_t)((x & 0xffff0000) >> 16));
+}
+
+static inline unsigned long __hweight64(uint64_t x)
+{
+        return __hweight32((uint32_t)x) +
+                __hweight32((uint32_t)((x & 0xffffffff00000000) >> 32));
+}
+
+#define hweight32               __hweight32
+#define hweight_long            __hweight64
+
+/*
+ * Better suited under a compiler.h type header file, but for now these can live
+ * here.
+ */
+#define __must_check
+#define __maybe_unused          __attribute__((unused))
+#define __iomem
+#define unlikely
+#define likely
+
+#define __stringify(x)          #x
+
+/*
+ * Prevent compiler optimizations from mangling writes. But likely most uses of
+ * this in nvgpu are incorrect (i.e unnecessary).
+ */
+#define WRITE_ONCE(p, v)                                \
+        ({                                              \
+                volatile typeof(p) *__p__ = &(p);       \
+                *__p__ = v;                             \
+        })
+
+#define container_of(ptr, type, member) ({                      \
+        const typeof( ((type *)0)->member ) *__mptr = (ptr);    \
+        (type *)( (char *)__mptr - offsetof(type,member) );})
+
+#define __packed __attribute__((packed))
+
+#define IS_ENABLED(config) 0
+
+#define MAX_ERRNO       4095
+
+#define IS_ERR_VALUE(x) ((x) >= (unsigned long)-MAX_ERRNO)
+
+static inline void *ERR_PTR(long error)
+{
+        return (void *) error;
+}
+
+static inline long PTR_ERR(void *error)
+{
+        return (long)(uintptr_t)error;
+}
+
+static inline bool IS_ERR(const void *ptr)
+{
+        return IS_ERR_VALUE((unsigned long)ptr);
+}
+
+static inline bool IS_ERR_OR_NULL(const void *ptr)
+{
+        return (ptr == NULL) || IS_ERR_VALUE((unsigned long)ptr);
+}
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/vm.h b/drivers/gpu/nvgpu/include/nvgpu/posix/vm.h
new file mode 100644
index 00000000..ae997d3c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/vm.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_POSIX_VM_H__
+#define __NVGPU_POSIX_VM_H__
+
+#include <nvgpu/types.h>
+
+struct nvgpu_os_buffer {
+        /*
+         * We just use malloc() buffers in userspace.
+         */
+        void *buf;
+        size_t size;
+};
+
+struct nvgpu_mapped_buf_priv {
+        void *buf;
+        size_t size;
+};
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/rwsem.h b/drivers/gpu/nvgpu/include/nvgpu/rwsem.h
index 0366ceff..4facf138 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/rwsem.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/rwsem.h
@@ -24,6 +24,8 @@
 
 #ifdef __KERNEL__
 #include <nvgpu/linux/rwsem.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/rwsem.h>
 #else
 #include <nvgpu_rmos/include/rwsem.h>
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/sizes.h b/drivers/gpu/nvgpu/include/nvgpu/sizes.h
index bb6f9c3d..588e772d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/sizes.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/sizes.h
@@ -24,6 +24,8 @@
 
 #ifdef __KERNEL__
 #include <linux/sizes.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/sizes.h>
 #else
 #include <nvgpu_rmos/include/sizes.h>
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/sort.h b/drivers/gpu/nvgpu/include/nvgpu/sort.h
index 0bef3593..20d86680 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/sort.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/sort.h
@@ -24,6 +24,8 @@
 
 #ifdef __KERNEL__
 #include <linux/sort.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/sort.h>
 #else
 #include <nvgpu_rmos/include/sort.h>
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/thread.h b/drivers/gpu/nvgpu/include/nvgpu/thread.h
index 79df9cda..316ca146 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/thread.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/thread.h
@@ -25,10 +25,14 @@
 
 #ifdef __KERNEL__
 #include <nvgpu/linux/thread.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/thread.h>
 #else
 #include <nvgpu_rmos/include/thread.h>
 #endif
 
+#include <nvgpu/types.h>
+
 /**
  * nvgpu_thread_create - Create and run a new thread.
  *
diff --git a/drivers/gpu/nvgpu/include/nvgpu/types.h b/drivers/gpu/nvgpu/include/nvgpu/types.h
index 8425c25d..1e243e53 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/types.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/types.h
@@ -24,6 +24,8 @@
 
 #ifdef __KERNEL__
 #include <linux/types.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/types.h>
 #else
 #include <nvgpu_rmos/include/types.h>
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm.h b/drivers/gpu/nvgpu/include/nvgpu/vm.h
index a5a358ea..30a2d71d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vm.h
@@ -43,6 +43,8 @@ struct nvgpu_os_buffer;
 
 #ifdef __KERNEL__
 #include <nvgpu/linux/vm.h>
+#elif defined(__NVGPU_POSIX__)
+#include <nvgpu/posix/vm.h>
 #else
 /* QNX include goes here. */
 #include <nvgpu_rmos/include/vm.h>
diff --git a/drivers/gpu/nvgpu/libnvgpu-drv.export b/drivers/gpu/nvgpu/libnvgpu-drv.export
new file mode 100644
index 00000000..14900acc
--- /dev/null
+++ b/drivers/gpu/nvgpu/libnvgpu-drv.export
@@ -0,0 +1,1581 @@
+acr_ucode_patch_sig
+bitmap_clear
+bitmap_find_next_zero_area
+bitmap_find_next_zero_area_off
+bitmap_set
+bl_bootstrap_sec2
+boardobj_construct_super
+boardobj_destruct_super
+boardobjgrpconstruct_e255
+boardobjgrpconstruct_e32
+boardobjgrp_construct_super
+boardobjgrp_destruct_impl
+boardobjgrp_destruct_super
+boardobjgrpe32hdrset
+boardobjgrpmask_and
+boardobjgrpmask_bitclr
+boardobjgrpmask_bitget
+boardobjgrpmask_bitidxhighest
+boardobjgrpmask_bitidxlowest
+boardobjgrpmask_bitinv
+boardobjgrpmask_bitset
+boardobjgrpmask_bitsetcount
+boardobjgrpmask_clr
+boardobjgrpmask_copy
+boardobjgrpmask_export
+boardobjgrpmask_import
+boardobjgrpmask_init
+boardobjgrpmask_inv
+boardobjgrpmask_issubset
+boardobjgrpmask_iszero
+boardobjgrpmask_or
+boardobjgrpmask_set
+boardobjgrpmask_sizeeq
+boardobjgrpmask_xor
+boardobjgrp_pmucmd_construct_impl
+boardobjgrp_pmucmd_construct_impl_v1
+boardobjgrp_pmucmd_destroy_impl
+boardobjgrp_pmucmd_pmuinithandle_impl
+boardobjgrp_pmudatainit_legacy
+boardobjgrp_pmudatainit_super
+boardobjgrp_pmugetstatus_impl
+boardobjgrp_pmugetstatus_impl_v1
+boardobjgrp_pmuhdrdatainit_e255
+boardobjgrp_pmuhdrdatainit_e32
+boardobjgrp_pmuhdrdatainit_super
+boardobjgrp_pmuinithandle_impl
+boardobjgrp_pmuset_impl
+boardobjgrp_pmuset_impl_v1
+boardobj_implements_super
+boardobj_pmudatainit_super
+__bug
+channel_gk20a_alloc_job
+channel_gk20a_commit_va
+channel_gk20a_free_job
+channel_gk20a_is_prealloc_enabled
+channel_gk20a_joblist_is_empty
+channel_gk20a_joblist_lock
+channel_gk20a_joblist_unlock
+channel_gk20a_update_runlist
+channel_gm20b_bind
+channel_gp10b_commit_userd
+channel_gp10b_setup_ramfc
+channel_gv11b_setup_ramfc
+channel_gv11b_unbind
+clear_bit
+clear_halt_interrupt_status
+clk_domain_clk_prog_link
+clk_domain_get_f_or_v
+clk_domain_get_f_points
+clk_domain_pmu_setup
+clk_domain_print_vf_table
+clk_domain_sw_setup
+clk_fll_pmu_setup
+clk_fll_sw_setup
+clk_freq_controller_pmu_setup
+clk_freq_controller_sw_setup
+clk_get_fll_clks
+clk_pmu_freq_controller_load
+clk_pmu_vin_load
+clk_prog_pmu_setup
+clk_prog_sw_setup
+clk_set_fll_clks
+clk_vf_point_cache
+clk_vf_point_pmu_setup
+clk_vf_point_sw_setup
+clk_vin_pmu_setup
+clk_vin_sw_setup
+construct_clk_vf_point
+dbg_set_powergate
+dump_stack
+exec_regops_gk20a
+fb_gk20a_reset
+fb_gm20b_init_fs_state
+fecs_ucode_details
+find_first_bit
+find_first_zero_bit
+find_next_bit
+_fini
+free_acr_resources
+free_priv_cmdbuf
+get_ecc_override_val
+__get_pte_size
+__get_pte_size_fixed_map
+gk20a_alloc_fence
+gk20a_alloc_fence_pool
+gk20a_alloc_inst_block
+gk20a_alloc_obj_ctx
+gk20a_alloc_or_get_comptags
+gk20a_as_alloc_share
+gk20a_as_release_share
+gk20a_bus_bar1_bind
+gk20a_bus_init_hw
+gk20a_bus_isr
+gk20a_busy
+gk20a_busy_noresume
+gk20a_can_busy
+gk20a_ce2_isr
+gk20a_ce2_nonstall_isr
+gk20a_ce_create_context
+gk20a_ce_delete_context
+gk20a_ce_delete_context_priv
+gk20a_ce_destroy
+gk20a_ce_prepare_submit
+gk20a_ce_suspend
+gk20a_channel_abort
+gk20a_channel_abort_clean_up
+gk20a_channel_add_job
+gk20a_channel_alloc_gpfifo
+gk20a_channel_alloc_priv_cmdbuf
+gk20a_channel_clean_up_jobs
+gk20a_channel_close
+gk20a_channel_deterministic_idle
+gk20a_channel_deterministic_unidle
+gk20a_channel_free_usermode_buffers
+_gk20a_channel_get
+gk20a_channel_get_timescale_from_timeslice
+__gk20a_channel_kill
+_gk20a_channel_put
+gk20a_channel_resume
+gk20a_channel_semaphore_wakeup
+gk20a_channel_suspend
+gk20a_channel_sync_create
+gk20a_channel_sync_destroy
+gk20a_channel_sync_needs_sync_framework
+gk20a_channel_timeout_restart_all_channels
+gk20a_channel_update
+gk20a_channel_update_and_check_timeout
+gk20a_comptag_allocator_destroy
+gk20a_comptag_allocator_init
+gk20a_comptaglines_alloc
+gk20a_comptaglines_free
+gk20a_comptags_finish_clear
+gk20a_comptags_start_clear
+gk20a_dbg_gpu_broadcast_stop_trigger
+gk20a_dbg_gpu_clear_broadcast_stop_trigger
+gk20a_dbg_gpu_post_events
+gk20a_debug_dump_all_channel_status_ramfc
+gk20a_decode_ccsr_chan_status
+gk20a_decode_pbdma_chan_eng_ctx_status
+gk20a_deinit_pstate_support
+gk20a_detect_chip
+gk20a_disable_channel
+gk20a_disable_channel_tsg
+gk20a_disable_tsg
+gk20a_dump_channel_status_ramfc
+gk20a_dump_eng_status
+gk20a_dump_pbdma_status
+gk20a_elcg_init_idle_filters
+gk20a_enable_channel_tsg
+gk20a_enable_gr_hw
+gk20a_enable_priv_ring
+gk20a_enable_tsg
+gk20a_falcon_dump_stats
+gk20a_falcon_hal_sw_init
+gk20a_falcon_ops
+gk20a_fb_init_hw
+gk20a_fb_tlb_invalidate
+gk20a_fecs_dump_falcon_stats
+gk20a_fence_from_semaphore
+gk20a_fence_from_syncpt
+gk20a_fence_get
+gk20a_fence_install_fd
+gk20a_fence_is_expired
+gk20a_fence_put
+gk20a_fence_wait
+gk20a_fifo_abort_tsg
+gk20a_fifo_act_eng_interrupt_mask
+gk20a_fifo_alloc_inst
+gk20a_fifo_channel_from_chid
+gk20a_fifo_channel_status_is_ctx_reload
+gk20a_fifo_channel_status_is_next
+gk20a_fifo_channel_unbind
+gk20a_fifo_check_ch_ctxsw_timeout
+gk20a_fifo_check_tsg_ctxsw_timeout
+gk20a_fifo_default_timeslice_us
+gk20a_fifo_deferred_reset
+gk20a_fifo_delete_runlist
+gk20a_fifo_disable_all_engine_activity
+gk20a_fifo_disable_channel
+gk20a_fifo_disable_engine_activity
+gk20a_fifo_disable_tsg_sched
+gk20a_fifo_enable_all_engine_activity
+gk20a_fifo_enable_channel
+gk20a_fifo_enable_engine_activity
+gk20a_fifo_enable_tsg_sched
+gk20a_fifo_engine_enum_from_type
+gk20a_fifo_engine_interrupt_mask
+gk20a_fifo_error_ch
+gk20a_fifo_error_tsg
+gk20a_fifo_force_reset_ch
+gk20a_fifo_free_inst
+gk20a_fifo_get_all_ce_engine_reset_mask
+gk20a_fifo_get_engine_ids
+gk20a_fifo_get_engine_info
+gk20a_fifo_get_failing_engine_data
+gk20a_fifo_get_fast_ce_runlist_id
+gk20a_fifo_get_gr_engine_id
+gk20a_fifo_get_gr_runlist_id
+gk20a_fifo_get_mmu_fault_info
+gk20a_fifo_get_pbdma_signature
+gk20a_fifo_handle_pbdma_intr
+gk20a_fifo_handle_pbdma_intr_0
+gk20a_fifo_handle_pbdma_intr_1
+gk20a_fifo_handle_runlist_event
+gk20a_fifo_handle_sched_error
+gk20a_fifo_init_engine_info
+gk20a_fifo_interleave_level_name
+gk20a_fifo_intr_0_error_mask
+gk20a_fifo_is_engine_busy
+gk20a_fifo_is_preempt_pending
+gk20a_fifo_isr
+gk20a_fifo_issue_preempt
+gk20a_fifo_is_valid_engine_id
+gk20a_fifo_is_valid_runlist_id
+gk20a_fifo_mmu_fault_pending
+gk20a_fifo_nonstall_isr
+gk20a_fifo_pbdma_acquire_val
+gk20a_fifo_preempt
+gk20a_fifo_preempt_channel
+gk20a_fifo_preempt_tsg
+gk20a_fifo_recover
+gk20a_fifo_recover_ch
+gk20a_fifo_recover_tsg
+gk20a_fifo_reschedule_runlist
+gk20a_fifo_reset_engine
+gk20a_fifo_reset_pbdma_method
+gk20a_fifo_runlist_wait_pending
+gk20a_fifo_set_ctx_mmu_error_ch
+gk20a_fifo_set_ctx_mmu_error_tsg
+gk20a_fifo_set_runlist_interleave
+gk20a_fifo_set_runlist_state
+gk20a_fifo_setup_ramfc
+gk20a_fifo_setup_ramfc_for_privileged_channel
+gk20a_fifo_setup_userd
+gk20a_fifo_should_defer_engine_reset
+gk20a_fifo_suspend
+gk20a_fifo_teardown_ch_tsg
+gk20a_fifo_tsg_set_timeslice
+gk20a_fifo_tsg_unbind_channel
+gk20a_fifo_tsg_unbind_channel_verify_status
+gk20a_fifo_update_runlist
+gk20a_fifo_update_runlist_ids
+gk20a_fifo_userd_gp_get
+gk20a_fifo_userd_gp_put
+gk20a_fifo_userd_pb_get
+gk20a_fifo_wait_engine_idle
+gk20a_finalize_poweron
+gk20a_free_fence_pool
+gk20a_free_priv_cmdbuf
+gk20a_get
+gk20a_get_ch_runlist_entry
+gk20a_get_comptags
+gk20a_get_pde_pgsz
+gk20a_get_pte_pgsz
+gk20a_get_tsg_runlist_entry
+gk20a_gr_enable_exceptions
+gk20a_gr_enable_gpc_exceptions
+gk20a_gr_get_esr_sm_sel
+gk20a_gr_get_ovr_perf_regs
+gk20a_gr_get_sm_hww_global_esr
+gk20a_gr_get_sm_hww_warp_esr
+gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask
+gk20a_gr_gpc_offset
+gk20a_gr_handle_fecs_error
+gk20a_gr_handle_notify_pending
+gk20a_gr_handle_semaphore_pending
+gk20a_gr_init_ctxsw_hdr_data
+gk20a_gr_init_ovr_sm_dsm_perf
+gk20a_gr_isr
+gk20a_gr_lock_down_sm
+gk20a_gr_nonstall_isr
+gk20a_gr_reset
+gk20a_gr_resume_all_sms
+gk20a_gr_resume_single_sm
+gk20a_gr_set_shader_exceptions
+gk20a_gr_sm_debugger_attached
+gk20a_gr_suspend
+gk20a_gr_suspend_all_sms
+gk20a_gr_suspend_single_sm
+gk20a_gr_tpc_offset
+gk20a_gr_wait_for_sm_lock_down
+gk20a_gr_wait_initialized
+_gk20a_gr_zbc_set_table
+gk20a_gr_zbc_set_table
+gk20a_idle
+gk20a_idle_nosuspend
+gk20a_init_ce_support
+gk20a_init_channel_support
+gk20a_init_fence
+gk20a_init_fifo_reset_enable_hw
+gk20a_init_fifo_setup_hw
+gk20a_init_fifo_setup_sw
+gk20a_init_fifo_setup_sw_common
+gk20a_init_fifo_support
+gk20a_init_gpu_characteristics
+gk20a_init_gr
+gk20a_init_gr_support
+gk20a_init_inst_block
+gk20a_init_mm_setup_hw
+gk20a_init_pmu_setup_hw1
+gk20a_init_pstate_pmu_support
+gk20a_init_pstate_support
+gk20a_init_sw_bundle
+gk20a_init_therm_support
+gk20a_init_tsg_support
+gk20a_is_channel_ctx_resident
+gk20a_is_channel_marked_as_tsg
+gk20a_is_fault_engine_subid_gpc
+gk20a_is_pmu_supported
+gk20a_locked_gmmu_map
+gk20a_locked_gmmu_unmap
+gk20a_mc_boot_0
+gk20a_mc_disable
+gk20a_mc_enable
+gk20a_mc_reset
+gk20a_mm_cbc_clean
+gk20a_mm_fb_flush
+gk20a_mm_get_iommu_bit
+gk20a_mm_get_mmu_levels
+gk20a_mm_init_pdb
+gk20a_mm_l2_flush
+gk20a_mm_l2_invalidate
+gk20a_open_new_channel
+gk20a_perfbuf_disable_locked
+gk20a_perfbuf_enable_locked
+gk20a_pmu_dump_elpg_stats
+gk20a_pmu_dump_falcon_stats
+gk20a_pmu_elpg_statistics
+gk20a_pmu_engine_reset
+gk20a_pmu_get_irqdest
+gk20a_pmu_init_perfmon_counter
+gk20a_pmu_is_engine_in_reset
+gk20a_pmu_is_interrupted
+gk20a_pmu_isr
+gk20a_pmu_msgq_tail
+gk20a_pmu_mutex_acquire
+gk20a_pmu_mutex_release
+gk20a_pmu_pg_engines_list
+gk20a_pmu_pg_feature_list
+gk20a_pmu_pg_idle_counter_config
+gk20a_pmu_queue_head
+gk20a_pmu_queue_tail
+gk20a_pmu_read_idle_counter
+gk20a_pmu_reset_idle_counter
+gk20a_pmu_save_zbc
+gk20a_pramin_enter
+gk20a_pramin_exit
+gk20a_prepare_poweroff
+gk20a_priv_ring_isr
+gk20a_put
+gk20a_read_ptimer
+gk20a_refch_from_inst_ptr
+gk20a_runlist_construct_locked
+gk20a_tsg_bind_channel
+gk20a_tsg_event_id_post_event
+gk20a_tsg_get_timeslice
+gk20a_tsg_open
+gk20a_tsg_release
+gk20a_tsg_set_runlist_interleave
+gk20a_tsg_set_timeslice
+gk20a_tsg_unbind_channel
+__gk20a_vm_bind_channel
+gk20a_vm_bind_channel
+gk20a_vm_release_share
+gk20a_wait_channel_idle
+gk20a_wait_for_idle
+gk20a_wait_until_counter_is_N
+__gk20a_warn_on_no_regs
+gk20a_write_dmatrfbase
+gm20a_gr_disable_rd_coalesce
+gm20b_alloc_blob_space
+gm20b_apply_smpc_war
+gm20b_blcg_bus_load_gating_prod
+gm20b_blcg_ctxsw_firmware_load_gating_prod
+gm20b_blcg_fb_load_gating_prod
+gm20b_blcg_fifo_load_gating_prod
+gm20b_blcg_gr_load_gating_prod
+gm20b_blcg_ltc_load_gating_prod
+gm20b_blcg_pmu_load_gating_prod
+gm20b_blcg_pwr_csb_load_gating_prod
+gm20b_blcg_xbar_load_gating_prod
+gm20b_bootstrap_hs_flcn
+gm20b_bus_bar1_bind
+gm20b_clk_get_gpcclk_clock_counter
+gm20b_clk_get_pll_debug_data
+gm20b_clk_get_voltage
+gm20b_clk_is_prepared
+gm20b_clk_pll_reg_write
+gm20b_clk_prepare
+gm20b_clk_unprepare
+gm20b_determine_L2_size_bytes
+gm20b_device_info_data_parse
+gm20b_fb_compressible_page_size
+gm20b_fb_compression_align_mask
+gm20b_fb_compression_page_size
+gm20b_fb_debug_mode_enabled
+gm20b_fb_dump_vpr_wpr_info
+gm20b_fb_read_wpr_info
+gm20b_fb_set_debug_mode
+gm20b_fb_set_mmu_page_size
+gm20b_fb_set_use_full_comp_tag_line
+gm20b_fb_vpr_info_fetch
+gm20b_fifo_get_num_fifos
+gm20b_fifo_init_pbdma_intr_descs
+gm20b_fifo_trigger_mmu_fault
+gm20b_fifo_tsg_verify_status_ctx_reload
+gm20b_flcn_populate_bl_dmem_desc
+gm20b_flush_ltc
+gm20b_fuse_check_priv_security
+gm20b_get_context_whitelist_ranges
+gm20b_get_context_whitelist_ranges_count
+gm20b_get_global_whitelist_ranges
+gm20b_get_global_whitelist_ranges_count
+gm20b_get_gpc_pll_parms
+gm20b_get_kind_invalid
+gm20b_get_kind_pitch
+gm20b_get_litter_value
+gm20b_get_qctl_whitelist
+gm20b_get_qctl_whitelist_count
+gm20b_get_qctl_whitelist_ranges
+gm20b_get_qctl_whitelist_ranges_count
+gm20b_get_runcontrol_whitelist
+gm20b_get_runcontrol_whitelist_count
+gm20b_get_runcontrol_whitelist_ranges
+gm20b_get_runcontrol_whitelist_ranges_count
+gm20b_gpcclk_set_rate
+gm20b_gpu_phys_addr
+gm20b_gr_clear_sm_error_state
+gm20b_gr_clear_sm_hww
+gm20b_gr_record_sm_error_state
+gm20b_gr_update_sm_error_state
+gm20b_init_clk_setup_sw
+gm20b_init_clk_support
+gm20b_init_hal
+gm20b_init_nspmu_setup_hw1
+gm20b_init_pmu_setup_hw1
+gm20b_init_therm_setup_hw
+gm20b_is_lazy_bootstrap
+gm20b_is_pmu_supported
+gm20b_is_priv_load
+gm20b_load_falcon_ucode
+gm20b_ltc_cbc_ctrl
+gm20b_ltc_cbc_fix_config
+gm20b_ltc_init_cbc
+gm20b_ltc_init_comptags
+gm20b_ltc_init_fs_state
+gm20b_ltc_isr
+gm20b_ltc_set_enabled
+gm20b_ltc_set_zbc_color_entry
+gm20b_ltc_set_zbc_depth_entry
+gm20b_mm_get_big_page_sizes
+gm20b_mm_get_default_big_page_size
+gm20b_mm_is_bar1_supported
+gm20b_mm_set_big_page_size
+gm20b_mm_support_sparse
+gm20b_pmu_init_acr
+gm20b_pmu_load_lsf
+gm20b_pmu_populate_loader_cfg
+gm20b_pmu_setup_elpg
+gm20b_recalc_rate
+gm20b_round_rate
+gm20b_setup_apertures
+gm20b_slcg_bus_load_gating_prod
+gm20b_slcg_ce2_load_gating_prod
+gm20b_slcg_chiplet_load_gating_prod
+gm20b_slcg_ctxsw_firmware_load_gating_prod
+gm20b_slcg_fb_load_gating_prod
+gm20b_slcg_fifo_load_gating_prod
+gm20b_slcg_perf_load_gating_prod
+gm20b_slcg_pmu_load_gating_prod
+gm20b_slcg_priring_load_gating_prod
+gm20b_slcg_pwr_csb_load_gating_prod
+gm20b_slcg_therm_load_gating_prod
+gm20b_slcg_xbar_load_gating_prod
+gm20b_suspend_clk_support
+gm20b_update_lspmu_cmdline_args
+gm20b_wpr_info
+gm20b_write_dmatrfbase
+gp106_alloc_blob_space
+gp106_apply_smpc_war
+gp106_bios_init
+gp106_bios_preos_wait_for_halt
+gp106_blcg_bus_load_gating_prod
+gp106_blcg_ce_load_gating_prod
+gp106_blcg_fb_load_gating_prod
+gp106_blcg_fifo_load_gating_prod
+gp106_blcg_gr_load_gating_prod
+gp106_blcg_ltc_load_gating_prod
+gp106_blcg_pmu_load_gating_prod
+gp106_blcg_xbar_load_gating_prod
+gp106_bootstrap_hs_flcn
+gp106_clk_measure_freq
+gp106_configure_therm_alert
+gp106_crystal_clk_hz
+gp106_elcg_init_idle_filters
+gp106_falcon_hal_sw_init
+gp106_fb_reset
+gp106_fifo_get_num_fifos
+gp106_flcn_populate_bl_dmem_desc
+gp106_fuse_check_priv_security
+gp106_get_arbiter_clk_default
+gp106_get_arbiter_clk_domains
+gp106_get_arbiter_clk_range
+gp106_get_context_whitelist_ranges
+gp106_get_context_whitelist_ranges_count
+gp106_get_global_whitelist_ranges
+gp106_get_global_whitelist_ranges_count
+gp106_get_internal_sensor_curr_temp
+gp106_get_internal_sensor_limits
+gp106_get_qctl_whitelist
+gp106_get_qctl_whitelist_count
+gp106_get_qctl_whitelist_ranges
+gp106_get_qctl_whitelist_ranges_count
+gp106_get_runcontrol_whitelist
+gp106_get_runcontrol_whitelist_count
+gp106_get_runcontrol_whitelist_ranges
+gp106_get_runcontrol_whitelist_ranges_count
+gp106_init_clk_support
+gp106_init_hal
+gp106_is_lazy_bootstrap
+gp106_is_pmu_supported
+gp106_is_priv_load
+gp106_load_falcon_ucode
+gp106_mclk_change
+gp106_mclk_deinit
+gp106_mclk_init
+gp106_mm_get_vidmem_size
+gp106_pg_param_init
+gp106_pmu_elpg_statistics
+gp106_pmu_engine_reset
+gp106_pmu_is_engine_in_reset
+gp106_pmu_is_lpwr_feature_supported
+gp106_pmu_pg_engines_list
+gp106_pmu_pg_feature_list
+gp106_pmu_populate_loader_cfg
+gp106_prepare_ucode_blob
+gp106_sec2_reset
+gp106_slcg_bus_load_gating_prod
+gp106_slcg_ce2_load_gating_prod
+gp106_slcg_chiplet_load_gating_prod
+gp106_slcg_ctxsw_firmware_load_gating_prod
+gp106_slcg_fb_load_gating_prod
+gp106_slcg_fifo_load_gating_prod
+gp106_slcg_perf_load_gating_prod
+gp106_slcg_pmu_load_gating_prod
+gp106_slcg_priring_load_gating_prod
+gp106_slcg_therm_load_gating_prod
+gp106_slcg_xbar_load_gating_prod
+gp106_suspend_clk_support
+gp106_wpr_info
+gp10b_apply_smpc_war
+gp10b_blcg_bus_load_gating_prod
+gp10b_blcg_ce_load_gating_prod
+gp10b_blcg_ctxsw_firmware_load_gating_prod
+gp10b_blcg_fb_load_gating_prod
+gp10b_blcg_fifo_load_gating_prod
+gp10b_blcg_gr_load_gating_prod
+gp10b_blcg_ltc_load_gating_prod
+gp10b_blcg_pmu_load_gating_prod
+gp10b_blcg_pwr_csb_load_gating_prod
+gp10b_blcg_xbar_load_gating_prod
+gp10b_ce_isr
+gp10b_ce_nonstall_isr
+gp10b_determine_L2_size_bytes
+gp10b_device_info_data_parse
+gp10b_elcg_init_idle_filters
+gp10b_fb_compressible_page_size
+gp10b_fb_compression_page_size
+gp10b_fifo_engine_enum_from_type
+gp10b_fifo_get_mmu_fault_info
+gp10b_fifo_get_pbdma_signature
+gp10b_fifo_init_pbdma_intr_descs
+gp10b_fifo_resetup_ramfc
+gp10b_fuse_check_priv_security
+gp10b_get_context_whitelist_ranges
+gp10b_get_context_whitelist_ranges_count
+gp10b_get_global_whitelist_ranges
+gp10b_get_global_whitelist_ranges_count
+gp10b_get_litter_value
+gp10b_get_qctl_whitelist
+gp10b_get_qctl_whitelist_count
+gp10b_get_qctl_whitelist_ranges
+gp10b_get_qctl_whitelist_ranges_count
+gp10b_get_runcontrol_whitelist
+gp10b_get_runcontrol_whitelist_count
+gp10b_get_runcontrol_whitelist_ranges
+gp10b_get_runcontrol_whitelist_ranges_count
+gp10b_gr_get_sm_hww_warp_esr
+gp10b_init_bar2_mm_hw_setup
+gp10b_init_bar2_vm
+gp10b_init_gpu_characteristics
+gp10b_init_hal
+gp10b_init_mm_setup_hw
+gp10b_init_pmu_setup_hw1
+gp10b_init_therm_setup_hw
+gp10b_is_lazy_bootstrap
+gp10b_is_pmu_supported
+gp10b_is_priv_load
+gp10b_load_falcon_ucode
+gp10b_ltc_cbc_ctrl
+gp10b_ltc_init_comptags
+gp10b_ltc_init_fs_state
+gp10b_ltc_isr
+gp10b_ltc_set_enabled
+gp10b_mm_get_default_big_page_size
+gp10b_mm_get_iommu_bit
+gp10b_mm_get_mmu_levels
+gp10b_mm_init_pdb
+gp10b_pg_gr_init
+gp10b_pmu_elpg_statistics
+gp10b_pmu_setup_elpg
+gp10b_priv_ring_decode_error_code
+gp10b_priv_ring_isr
+gp10b_remove_bar2_vm
+gp10b_replayable_pagefault_buffer_clear_overflow
+gp10b_replayable_pagefault_buffer_deinit
+gp10b_replayable_pagefault_buffer_get_index
+gp10b_replayable_pagefault_buffer_info
+gp10b_replayable_pagefault_buffer_init
+gp10b_replayable_pagefault_buffer_is_empty
+gp10b_replayable_pagefault_buffer_is_full
+gp10b_replayable_pagefault_buffer_is_overflow
+gp10b_replayable_pagefault_buffer_put_index
+gp10b_slcg_bus_load_gating_prod
+gp10b_slcg_ce2_load_gating_prod
+gp10b_slcg_chiplet_load_gating_prod
+gp10b_slcg_ctxsw_firmware_load_gating_prod
+gp10b_slcg_fb_load_gating_prod
+gp10b_slcg_fifo_load_gating_prod
+gp10b_slcg_perf_load_gating_prod
+gp10b_slcg_pmu_load_gating_prod
+gp10b_slcg_priring_load_gating_prod
+gp10b_slcg_pwr_csb_load_gating_prod
+gp10b_slcg_therm_load_gating_prod
+gp10b_slcg_xbar_load_gating_prod
+gp10b_write_dmatrfbase
+gpccs_ucode_details
+gpu_init_hal
+gr_gk20a_add_ctxsw_reg_perf_pma
+gr_gk20a_add_ctxsw_reg_pm_fbpa
+gr_gk20a_add_zbc
+gr_gk20a_add_zbc_color
+gr_gk20a_add_zbc_depth
+gr_gk20a_alloc_gr_ctx
+gr_gk20a_bind_ctxsw_zcull
+gr_gk20a_blcg_gr_load_gating_prod
+gr_gk20a_clear_sm_errors
+gr_gk20a_commit_global_ctx_buffers
+gr_gk20a_commit_global_pagepool
+gr_gk20a_commit_global_timeslice
+gr_gk20a_commit_inst
+gr_gk20a_create_priv_addr_table
+gr_gk20a_ctx_patch_write
+gr_gk20a_ctx_patch_write_begin
+gr_gk20a_ctx_patch_write_end
+gr_gk20a_ctx_wait_ucode
+gr_gk20a_decode_priv_addr
+gr_gk20a_disable_ctxsw
+gr_gk20a_enable_ctxsw
+gr_gk20a_enable_hww_exceptions
+__gr_gk20a_exec_ctx_ops
+gr_gk20a_exec_ctx_ops
+gr_gk20a_fecs_ctx_bind_channel
+gr_gk20a_fecs_ctx_image_save
+gr_gk20a_fecs_get_reglist_img_size
+gr_gk20a_fecs_host_int_enable
+gr_gk20a_fecs_set_reglist_bind_inst
+gr_gk20a_fecs_set_reglist_virtual_addr
+gr_gk20a_free_gr_ctx
+gr_gk20a_free_tsg_gr_ctx
+gr_gk20a_get_ctx_buffer_offsets
+gr_gk20a_get_ctx_id
+gr_gk20a_get_ctxsw_zcull_size
+gr_gk20a_get_patch_slots
+gr_gk20a_get_pm_ctx_buffer_offsets
+gr_gk20a_get_tpc_count
+gr_gk20a_get_zcull_info
+gr_gk20a_halt_pipe
+gr_gk20a_handle_sm_exception
+gr_gk20a_handle_tex_exception
+gr_gk20a_init_blcg_mode
+gr_gk20a_init_cg_mode
+gr_gk20a_init_ctx_state
+gr_gk20a_init_ctxsw_ucode
+gr_gk20a_init_ctx_vars
+gr_gk20a_init_ctx_vars_sim
+gr_gk20a_init_elcg_mode
+gr_gk20a_init_fs_state
+gr_gk20a_init_sm_id_table
+gr_gk20a_inval_icache
+gr_gk20a_load_ctxsw_ucode
+gr_gk20a_load_ctxsw_ucode_boot
+gr_gk20a_load_ctxsw_ucode_header
+gr_gk20a_load_falcon_bind_instblk
+gr_gk20a_load_golden_ctx_image
+gr_gk20a_load_zbc_default_table
+gr_gk20a_pg_gr_load_gating_prod
+gr_gk20a_pmu_save_zbc
+gr_gk20a_program_zcull_mapping
+gr_gk20a_query_zbc
+gr_gk20a_resume_context
+gr_gk20a_resume_contexts
+gr_gk20a_resume_from_pause
+gr_gk20a_set_sm_debug_mode
+gr_gk20a_setup_rop_mapping
+gr_gk20a_slcg_gr_load_gating_prod
+gr_gk20a_slcg_perf_load_gating_prod
+gr_gk20a_slcg_therm_load_gating_prod
+gr_gk20a_split_ppc_broadcast_addr
+gr_gk20a_submit_fecs_method_op
+gr_gk20a_submit_fecs_sideband_method_op
+gr_gk20a_suspend_context
+gr_gk20a_suspend_contexts
+gr_gk20a_tpc_enabled_exceptions
+gr_gk20a_trigger_suspend
+gr_gk20a_update_hwpm_ctxsw_mode
+gr_gk20a_update_smpc_ctxsw_mode
+gr_gk20a_wait_fe_idle
+gr_gk20a_wait_for_pause
+gr_gk20a_wait_idle
+gr_gk20a_write_pm_ptr
+gr_gk20a_write_zcull_ptr
+gr_gm20b_alloc_gr_ctx
+gr_gm20b_bpt_reg_info
+gr_gm20b_bundle_cb_defaults
+gr_gm20b_calc_global_ctx_buffer_size
+gr_gm20b_cb_size_default
+gr_gm20b_commit_global_attrib_cb
+gr_gm20b_commit_global_bundle_cb
+gr_gm20b_commit_global_cb_manager
+gr_gm20b_commit_global_pagepool
+gr_gm20b_detect_sm_arch
+gr_gm20b_dump_gr_status_regs
+gr_gm20b_enable_cde_in_fecs
+gr_gm20b_get_access_map
+gr_gm20b_get_fbp_en_mask
+gr_gm20b_get_gpc_tpc_mask
+gr_gm20b_get_max_fbps_count
+gr_gm20b_get_max_ltc_per_fbp
+gr_gm20b_get_max_lts_per_ltc
+gr_gm20b_get_netlist_name
+gr_gm20b_get_pmm_per_chiplet_offset
+gr_gm20b_get_preemption_mode_flags
+gr_gm20b_get_sm_dsm_perf_ctrl_regs
+gr_gm20b_get_sm_dsm_perf_regs
+gr_gm20b_get_tpc_num
+gr_gm20b_handle_sw_method
+gr_gm20b_init_cyclestats
+gr_gm20b_init_fs_state
+gr_gm20b_init_gpc_mmu
+gr_gm20b_init_sm_dsm_reg_info
+gr_gm20b_is_firmware_defined
+gr_gm20b_is_ltcn_ltss_addr
+gr_gm20b_is_ltcs_ltss_addr
+gr_gm20b_is_tpc_addr
+gr_gm20b_is_valid_class
+gr_gm20b_is_valid_compute_class
+gr_gm20b_is_valid_gfx_class
+gr_gm20b_load_ctxsw_ucode
+gr_gm20b_load_ctxsw_ucode_segments
+gr_gm20b_load_smid_config
+gr_gm20b_load_tpc_mask
+gr_gm20b_pagepool_default_size
+gr_gm20b_pg_gr_load_gating_prod
+gr_gm20b_program_sm_id_numbering
+gr_gm20b_rop_l2_en_mask
+gr_gm20b_set_alpha_circular_buffer_size
+gr_gm20b_set_circular_buffer_size
+gr_gm20b_set_gpc_tpc_mask
+gr_gm20b_set_hww_esr_report_mask
+gr_gm20b_set_rd_coalesce
+gr_gm20b_slcg_gr_load_gating_prod
+gr_gm20b_split_ltc_broadcast_addr
+gr_gm20b_split_lts_broadcast_addr
+gr_gm20b_update_ctxsw_preemption_mode
+gr_gm20b_update_pc_sampling
+gr_gp106_cb_size_default
+gr_gp106_get_netlist_name
+gr_gp106_handle_sw_method
+gr_gp106_is_firmware_defined
+gr_gp106_is_valid_class
+gr_gp106_pagepool_default_size
+gr_gp106_pg_gr_load_gating_prod
+gr_gp106_set_ctxsw_preemption_mode
+gr_gp106_slcg_gr_load_gating_prod
+gr_gp10b_add_zbc_color
+gr_gp10b_add_zbc_depth
+gr_gp10b_alloc_buffer
+gr_gp10b_alloc_gr_ctx
+gr_gp10b_calc_global_ctx_buffer_size
+gr_gp10b_cb_size_default
+gr_gp10b_commit_global_attrib_cb
+gr_gp10b_commit_global_bundle_cb
+gr_gp10b_commit_global_cb_manager
+gr_gp10b_commit_global_pagepool
+gr_gp10b_dump_ctxsw_stats
+gr_gp10b_dump_gr_status_regs
+gr_gp10b_get_access_map
+gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg
+gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg
+gr_gp10b_get_max_gfxp_wfi_timeout_count
+gr_gp10b_get_netlist_name
+gr_gp10b_get_preemption_mode_flags
+gr_gp10b_handle_fecs_error
+gr_gp10b_handle_sm_exception
+gr_gp10b_handle_sw_method
+gr_gp10b_handle_tex_exception
+gr_gp10b_init_ctx_state
+gr_gp10b_init_ctxsw_hdr_data
+gr_gp10b_init_czf_bypass
+gr_gp10b_init_fs_state
+gr_gp10b_init_gfxp_wfi_timeout_count
+gr_gp10b_init_preemption_state
+gr_gp10b_is_firmware_defined
+gr_gp10b_is_valid_class
+gr_gp10b_is_valid_compute_class
+gr_gp10b_is_valid_gfx_class
+gr_gp10b_load_smid_config
+gr_gp10b_pagepool_default_size
+gr_gp10b_pg_gr_load_gating_prod
+gr_gp10b_pre_process_sm_exception
+gr_gp10b_set_alpha_circular_buffer_size
+gr_gp10b_set_bes_crop_debug3
+gr_gp10b_set_bes_crop_debug4
+gr_gp10b_set_boosted_ctx
+gr_gp10b_set_cilp_preempt_pending
+gr_gp10b_set_circular_buffer_size
+gr_gp10b_set_ctxsw_preemption_mode
+gr_gp10b_set_czf_bypass
+gr_gp10b_set_gpc_tpc_mask
+gr_gp10b_set_preemption_buffer_va
+gr_gp10b_set_preemption_mode
+gr_gp10b_slcg_gr_load_gating_prod
+gr_gp10b_suspend_context
+gr_gp10b_suspend_contexts
+gr_gp10b_update_boosted_ctx
+gr_gp10b_update_ctxsw_preemption_mode
+gr_gp10b_wait_empty
+gr_gv100_add_ctxsw_reg_perf_pma
+gr_gv100_add_ctxsw_reg_pm_fbpa
+gr_gv100_bundle_cb_defaults
+gr_gv100_cb_size_default
+gr_gv100_get_netlist_name
+gr_gv100_get_patch_slots
+gr_gv100_init_sm_id_table
+gr_gv100_is_firmware_defined
+gr_gv100_set_gpc_tpc_mask
+gr_gv11b_add_zbc_stencil
+gr_gv11b_add_zbc_type_s
+gr_gv11b_alloc_buffer
+gr_gv11b_bundle_cb_defaults
+gr_gv11b_calc_global_ctx_buffer_size
+gr_gv11b_cb_size_default
+gr_gv11b_commit_global_attrib_cb
+gr_gv11b_commit_global_timeslice
+gr_gv11b_commit_inst
+gr_gv11b_create_priv_addr_table
+gr_gv11b_decode_priv_addr
+gr_gv11b_detect_sm_arch
+gr_gv11b_dump_gr_status_regs
+gr_gv11b_ecc_init_scrub_reg
+gr_gv11b_enable_exceptions
+gr_gv11b_enable_gpc_exceptions
+gr_gv11b_enable_hww_exceptions
+gr_gv11b_fecs_host_int_enable
+gr_gv11b_get_access_map
+gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg
+gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg
+gr_gv11b_get_max_gfxp_wfi_timeout_count
+gr_gv11b_get_netlist_name
+gr_gv11b_get_pmm_per_chiplet_offset
+gr_gv11b_handle_fecs_error
+gr_gv11b_handle_gcc_exception
+gr_gv11b_handle_gpc_gpccs_exception
+gr_gv11b_handle_gpc_gpcmmu_exception
+gr_gv11b_handle_ssync_hww
+gr_gv11b_handle_sw_method
+gr_gv11b_handle_tex_exception
+gr_gv11b_handle_tpc_mpc_exception
+gr_gv11b_handle_tpc_sm_ecc_exception
+gr_gv11b_init_elcg_mode
+gr_gv11b_init_fs_state
+gr_gv11b_init_gfxp_wfi_timeout_count
+gr_gv11b_init_gpc_mmu
+gr_gv11b_init_preemption_state
+gr_gv11b_init_sw_veid_bundle
+gr_gv11b_is_firmware_defined
+gr_gv11b_is_valid_class
+gr_gv11b_is_valid_compute_class
+gr_gv11b_is_valid_gfx_class
+gr_gv11b_load_smid_config
+gr_gv11b_load_stencil_default_tbl
+gr_gv11b_load_stencil_tbl
+gr_gv11b_load_tpc_mask
+gr_gv11b_pagepool_default_size
+gr_gv11b_pg_gr_load_gating_prod
+gr_gv11b_pre_process_sm_exception
+gr_gv11b_program_sm_id_numbering
+gr_gv11b_program_zcull_mapping
+gr_gv11b_set_alpha_circular_buffer_size
+gr_gv11b_set_circular_buffer_size
+gr_gv11b_set_ctxsw_preemption_mode
+gr_gv11b_set_gpc_tpc_mask
+gr_gv11b_set_preemption_buffer_va
+gr_gv11b_setup_rop_mapping
+gr_gv11b_slcg_gr_load_gating_prod
+gr_gv11b_update_ctxsw_preemption_mode
+gr_gv11b_wait_empty
+gr_gv11b_write_pm_ptr
+gr_gv11b_write_zcull_ptr
+gr_gv11b_zbc_s_query_table
+gv100_apply_ctxsw_timeout_intr
+gv100_apply_smpc_war
+gv100_bios_preos_reload_check
+gv100_bios_preos_wait_for_halt
+gv100_falcon_hal_sw_init
+gv100_fb_enable_nvlink
+gv100_fb_init_nvlink
+gv100_fb_memory_unlock
+gv100_fb_reset
+gv100_fifo_get_num_fifos
+gv100_fifo_get_preempt_timeout
+gv100_get_context_whitelist_ranges
+gv100_get_context_whitelist_ranges_count
+gv100_get_global_whitelist_ranges
+gv100_get_global_whitelist_ranges_count
+gv100_get_qctl_whitelist
+gv100_get_qctl_whitelist_count
+gv100_get_qctl_whitelist_ranges
+gv100_get_qctl_whitelist_ranges_count
+gv100_get_runcontrol_whitelist
+gv100_get_runcontrol_whitelist_count
+gv100_get_runcontrol_whitelist_ranges
+gv100_get_runcontrol_whitelist_ranges_count
+gv100_init_gpu_characteristics
+gv100_init_hal
+gv100_load_falcon_ucode
+gv100_mc_is_intr_nvlink_pending
+gv100_mc_is_stall_and_eng_intr_pending
+gv100_mm_get_flush_retries
+gv100_mm_get_vidmem_size
+gv100_nvlink_discover_ioctrl
+gv100_nvlink_discover_link
+gv100_nvlink_early_init
+gv100_nvlink_init
+gv100_nvlink_interface_init
+gv100_nvlink_isr
+gv100_nvlink_link_early_init
+gv100_nvlink_link_get_mode
+gv100_nvlink_link_get_rx_sublink_state
+gv100_nvlink_link_get_state
+gv100_nvlink_link_get_sublink_mode
+gv100_nvlink_link_get_tx_sublink_state
+gv100_nvlink_link_set_mode
+gv100_nvlink_link_set_sublink_mode
+gv100_nvlink_reg_init
+gv100_nvlink_shutdown
+gv100_pmu_init_acr
+gv11b_alloc_blob_space
+gv11b_alloc_subctx_header
+gv11b_apply_smpc_war
+gv11b_blcg_bus_load_gating_prod
+gv11b_blcg_ce_load_gating_prod
+gv11b_blcg_ctxsw_firmware_load_gating_prod
+gv11b_blcg_fb_load_gating_prod
+gv11b_blcg_fifo_load_gating_prod
+gv11b_blcg_gr_load_gating_prod
+gv11b_blcg_ltc_load_gating_prod
+gv11b_blcg_pmu_load_gating_prod
+gv11b_blcg_pwr_csb_load_gating_prod
+gv11b_blcg_xbar_load_gating_prod
+gv11b_bootstrap_hs_flcn
+gv11b_ce_get_num_lce
+gv11b_ce_get_num_pce
+gv11b_ce_isr
+gv11b_ce_mthd_buffer_fault_in_bar2_fault
+gv11b_detect_ecc_enabled_units
+gv11b_dump_channel_status_ramfc
+gv11b_dump_eng_status
+gv11b_elcg_init_idle_filters
+gv11b_fb_disable_hub_intr
+gv11b_fb_enable_hub_intr
+gv11b_fb_fault_buf_configure_hw
+gv11b_fb_fault_buf_set_state_hw
+gv11b_fb_hub_isr
+gv11b_fb_init_cbc
+gv11b_fb_init_fs_state
+gv11b_fb_is_fault_buf_enabled
+gv11b_fb_mmu_fault_pending
+gv11b_fb_reset
+gv11b_fifo_deinit_eng_method_buffers
+gv11b_fifo_enable_tsg
+gv11b_fifo_get_num_fifos
+gv11b_fifo_get_preempt_timeout
+gv11b_fifo_handle_ctxsw_timeout
+gv11b_fifo_handle_pbdma_intr_0
+gv11b_fifo_handle_pbdma_intr_1
+gv11b_fifo_handle_sched_error
+gv11b_fifo_init_eng_method_buffers
+gv11b_fifo_init_pbdma_intr_descs
+gv11b_fifo_intr_0_error_mask
+gv11b_fifo_is_preempt_pending
+gv11b_fifo_preempt_channel
+gv11b_fifo_preempt_ch_tsg
+gv11b_fifo_preempt_tsg
+gv11b_fifo_reset_pbdma_and_eng_faulted
+gv11b_fifo_teardown_ch_tsg
+gv11b_fifo_tsg_verify_status_faulted
+gv11b_free_subctx_header
+gv11b_get_ch_runlist_entry
+gv11b_get_context_whitelist_ranges
+gv11b_get_context_whitelist_ranges_count
+gv11b_get_global_whitelist_ranges
+gv11b_get_global_whitelist_ranges_count
+gv11b_get_litter_value
+gv11b_get_qctl_whitelist
+gv11b_get_qctl_whitelist_count
+gv11b_get_qctl_whitelist_ranges
+gv11b_get_qctl_whitelist_ranges_count
+gv11b_get_runcontrol_whitelist
+gv11b_get_runcontrol_whitelist_count
+gv11b_get_runcontrol_whitelist_ranges
+gv11b_get_runcontrol_whitelist_ranges_count
+gv11b_get_tsg_runlist_entry
+gv11b_gpu_phys_addr
+gv11b_gr_access_smpc_reg
+gv11b_gr_bpt_reg_info
+gv11b_gr_clear_sm_hww
+gv11b_gr_decode_egpc_addr
+gv11b_gr_egpc_etpc_priv_addr_table
+gv11b_gr_get_egpc_base
+gv11b_gr_get_egpc_etpc_num
+gv11b_gr_get_esr_sm_sel
+gv11b_gr_get_ovr_perf_regs
+gv11b_gr_get_sm_dsm_perf_ctrl_regs
+gv11b_gr_get_sm_dsm_perf_regs
+gv11b_gr_get_sm_hww_global_esr
+gv11b_gr_get_sm_hww_warp_esr
+gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask
+gv11b_gr_init_ovr_sm_dsm_perf
+gv11b_gr_init_sm_dsm_reg_info
+gv11b_gr_lock_down_sm
+gv11b_gr_pri_is_egpc_addr
+gv11b_gr_pri_is_etpc_addr
+gv11b_gr_record_sm_error_state
+gv11b_gr_resume_all_sms
+gv11b_gr_resume_from_pause
+gv11b_gr_resume_single_sm
+gv11b_gr_set_hww_esr_report_mask
+gv11b_gr_set_sm_debug_mode
+gv11b_gr_sm_debugger_attached
+gv11b_gr_sm_offset
+gv11b_gr_sm_trigger_suspend
+gv11b_gr_suspend_all_sms
+gv11b_gr_suspend_single_sm
+gv11b_gr_update_sm_error_state
+gv11b_gr_wait_for_sm_lock_down
+gv11b_init_bar2_mm_hw_setup
+gv11b_init_fifo_reset_enable_hw
+gv11b_init_fifo_setup_hw
+gv11b_init_gpu_characteristics
+gv11b_init_hal
+gv11b_init_inst_block
+gv11b_init_mm_setup_hw
+gv11b_init_pmu_setup_hw1
+gv11b_init_subcontext_pdb
+gv11b_init_therm_setup_hw
+gv11b_is_fault_engine_subid_gpc
+gv11b_is_lazy_bootstrap
+gv11b_is_pmu_supported
+gv11b_is_priv_load
+gv11b_ltc_init_fs_state
+gv11b_ltc_isr
+gv11b_ltc_set_zbc_stencil_entry
+gv11b_mc_is_intr_hub_pending
+gv11b_mc_is_stall_and_eng_intr_pending
+gv11b_mm_fault_info_mem_destroy
+gv11b_mm_is_bar1_supported
+gv11b_mm_l2_flush
+gv11b_mm_mmu_fault_pending
+gv11b_mm_remove_bar2_vm
+gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid
+gv11b_perfbuf_disable_locked
+gv11b_perfbuf_enable_locked
+gv11b_pg_gr_init
+gv11b_pg_set_subfeature_mask
+gv11b_pmu_bootstrap
+gv11b_pmu_get_irqdest
+gv11b_pmu_handle_ext_irq
+gv11b_pmu_setup_elpg
+gv11b_setup_apertures
+gv11b_slcg_bus_load_gating_prod
+gv11b_slcg_ce2_load_gating_prod
+gv11b_slcg_chiplet_load_gating_prod
+gv11b_slcg_ctxsw_firmware_load_gating_prod
+gv11b_slcg_fb_load_gating_prod
+gv11b_slcg_fifo_load_gating_prod
+gv11b_slcg_perf_load_gating_prod
+gv11b_slcg_pmu_load_gating_prod
+gv11b_slcg_priring_load_gating_prod
+gv11b_slcg_pwr_csb_load_gating_prod
+gv11b_slcg_therm_load_gating_prod
+gv11b_slcg_xbar_load_gating_prod
+gv11b_update_subctx_header
+gv11b_userd_gp_get
+gv11b_userd_gp_put
+gv11b_userd_pb_get
+_init
+init_pmu_setup_hw1
+init_rppg
+init_sec2_setup_hw1
+is_bar0_global_offset_whitelisted_gk20a
+is_boardobjgrp_pmucmd_id_valid_v0
+is_boardobjgrp_pmucmd_id_valid_v1
+__locked_fifo_preempt
+__locked_fifo_preempt_timeout_rc
+lsf_gen_wpr_requirements
+lsfm_add_ucode_img
+lsfm_discover_ucode_images
+lsfm_fill_flcn_bl_gen_desc
+lsfm_fill_static_lsb_hdr_info
+lsfm_free_nonpmu_ucode_img_res
+lsfm_free_ucode_img_res
+lsfm_init_wpr_contents
+ltc_gk20a_slcg_ltc_load_gating_prod
+ltc_gm20b_slcg_ltc_load_gating_prod
+ltc_gp106_slcg_ltc_load_gating_prod
+ltc_gp10b_slcg_ltc_load_gating_prod
+ltc_gv11b_slcg_ltc_load_gating_prod
+mc_gk20a_handle_intr_nonstall
+mc_gk20a_intr_enable
+mc_gk20a_intr_nonstall
+mc_gk20a_intr_nonstall_pause
+mc_gk20a_intr_nonstall_resume
+mc_gk20a_intr_stall
+mc_gk20a_intr_stall_pause
+mc_gk20a_intr_stall_resume
+mc_gk20a_intr_unit_config
+mc_gk20a_is_intr1_pending
+mc_gk20a_isr_stall
+mc_gp10b_intr_enable
+mc_gp10b_intr_nonstall
+mc_gp10b_intr_nonstall_pause
+mc_gp10b_intr_nonstall_resume
+mc_gp10b_intr_stall
+mc_gp10b_intr_stall_pause
+mc_gp10b_intr_stall_resume
+mc_gp10b_intr_unit_config
+mc_gp10b_is_intr1_pending
+mc_gp10b_isr_stall
+mc_gv100_intr_enable
+mc_gv11b_intr_enable
+nvgpu_aelpg_init
+nvgpu_aelpg_init_and_enable
+nvgpu_alloc
+nvgpu_alloc_base
+__nvgpu_alloc_common_init
+nvgpu_alloc_destroy
+nvgpu_alloc_end
+nvgpu_alloc_fixed
+nvgpu_alloc_initialized
+nvgpu_alloc_length
+nvgpu_alloc_release_carveout
+nvgpu_alloc_reserve_carveout
+nvgpu_alloc_space
+__nvgpu_aperture_mask
+nvgpu_aperture_mask
+nvgpu_bar1_readl
+nvgpu_bar1_writel
+__nvgpu_big_alloc
+nvgpu_big_free
+nvgpu_big_pages_possible
+nvgpu_bios_execute_script
+nvgpu_bios_get_nvlink_config_data
+nvgpu_bios_get_perf_table_ptrs
+nvgpu_bios_parse_rom
+nvgpu_bios_read_s8
+nvgpu_bios_read_u16
+nvgpu_bios_read_u32
+nvgpu_bios_read_u8
+nvgpu_bitmap_allocator_init
+__nvgpu_buddy_allocator_init
+nvgpu_buddy_allocator_init
+nvgpu_channel_worker_deinit
+nvgpu_channel_worker_init
+nvgpu_check_and_set_context_reservation
+nvgpu_check_and_set_global_reservation
+__nvgpu_check_gpu_state
+nvgpu_clk_arb_cleanup_arbiter
+nvgpu_clk_arb_commit_request_fd
+nvgpu_clk_arb_get_arbiter_actual_mhz
+nvgpu_clk_arb_get_arbiter_clk_domains
+nvgpu_clk_arb_get_arbiter_clk_f_points
+nvgpu_clk_arb_get_arbiter_clk_range
+nvgpu_clk_arb_get_arbiter_effective_mhz
+nvgpu_clk_arb_get_current_pstate
+nvgpu_clk_arb_get_session_target_mhz
+nvgpu_clk_arb_init_arbiter
+nvgpu_clk_arb_init_session
+nvgpu_clk_arb_install_event_fd
+nvgpu_clk_arb_install_request_fd
+nvgpu_clk_arb_install_session_fd
+nvgpu_clk_arb_is_valid_domain
+nvgpu_clk_arb_pstate_change_lock
+nvgpu_clk_arb_release_session
+nvgpu_clk_arb_schedule_alarm
+nvgpu_clk_arb_schedule_vf_table_update
+nvgpu_clk_arb_send_thermal_alarm
+nvgpu_clk_arb_set_session_target_mhz
+nvgpu_cond_broadcast
+nvgpu_cond_broadcast_interruptible
+nvgpu_cond_destroy
+nvgpu_cond_init
+nvgpu_cond_signal
+nvgpu_cond_signal_interruptible
+nvgpu_current_pid
+nvgpu_current_tid
+nvgpu_current_time_ms
+nvgpu_dbg_gpu_get_session_channel
+nvgpu_dma_alloc
+nvgpu_dma_alloc_flags
+nvgpu_dma_alloc_flags_sys
+nvgpu_dma_alloc_flags_vid
+nvgpu_dma_alloc_flags_vid_at
+nvgpu_dma_alloc_map
+nvgpu_dma_alloc_map_flags
+nvgpu_dma_alloc_map_flags_sys
+nvgpu_dma_alloc_map_flags_vid
+nvgpu_dma_alloc_map_sys
+nvgpu_dma_alloc_map_vid
+nvgpu_dma_alloc_sys
+nvgpu_dma_alloc_vid
+nvgpu_dma_free
+nvgpu_dma_unmap_free
+nvgpu_find_hex_in_string
+nvgpu_flcn_bootstrap
+nvgpu_flcn_clear_halt_intr_status
+nvgpu_flcn_copy_from_dmem
+nvgpu_flcn_copy_from_imem
+nvgpu_flcn_copy_to_dmem
+nvgpu_flcn_copy_to_imem
+nvgpu_flcn_dump_stats
+nvgpu_flcn_get_cpu_halted_status
+nvgpu_flcn_get_idle_status
+nvgpu_flcn_get_mem_scrubbing_status
+nvgpu_flcn_mailbox_read
+nvgpu_flcn_mailbox_write
+nvgpu_flcn_mem_scrub_wait
+nvgpu_flcn_print_dmem
+nvgpu_flcn_print_imem
+nvgpu_flcn_reset
+nvgpu_flcn_set_irq
+nvgpu_flcn_sw_init
+nvgpu_flcn_wait_for_halt
+nvgpu_flcn_wait_idle
+nvgpu_free
+nvgpu_free_enabled_flags
+nvgpu_free_fixed
+nvgpu_free_inst_block
+nvgpu_get_gpfifo_entry_size
+nvgpu_get_gp_free_count
+__nvgpu_get_pte
+nvgpu_get_timestamps_zipper
+nvgpu_gmmu_init_page_table
+nvgpu_gmmu_map
+nvgpu_gmmu_map_fixed
+nvgpu_gmmu_unmap
+nvgpu_gp_free_count
+nvgpu_hr_timestamp
+nvgpu_init_enabled_flags
+nvgpu_init_ltc_support
+nvgpu_init_mm_ce_context
+nvgpu_init_mm_support
+nvgpu_init_pmu_fw_support
+nvgpu_init_pmu_support
+nvgpu_init_pramin
+nvgpu_insert_mapped_buf
+nvgpu_inst_block_addr
+nvgpu_io_exists
+nvgpu_iommuable
+nvgpu_io_valid_reg
+nvgpu_is_bpmp_running
+nvgpu_is_enabled
+nvgpu_is_error_notifier_set
+nvgpu_is_hypervisor_mode
+__nvgpu_kcalloc
+nvgpu_kernel_restart
+__nvgpu_kfree
+nvgpu_kill_task_pg_init
+__nvgpu_kmalloc
+nvgpu_kmem_cache_alloc
+nvgpu_kmem_cache_create
+nvgpu_kmem_cache_destroy
+nvgpu_kmem_cache_free
+nvgpu_kmem_fini
+nvgpu_kmem_init
+__nvgpu_kzalloc
+nvgpu_lockless_allocator_init
+__nvgpu_log_dbg
+__nvgpu_log_msg
+nvgpu_lpwr_disable_pg
+nvgpu_lpwr_enable_pg
+nvgpu_lpwr_is_mscg_supported
+nvgpu_lpwr_is_rppg_supported
+nvgpu_lpwr_pg_setup
+nvgpu_lpwr_post_init
+nvgpu_ltc_alloc_cbc
+nvgpu_ltc_sync_enabled
+nvgpu_lwpr_mclk_change
+nvgpu_mem_begin
+nvgpu_mem_create_from_mem
+nvgpu_mem_end
+nvgpu_mem_get_addr
+nvgpu_mem_get_phys_addr
+nvgpu_mem_iommu_translate
+nvgpu_mem_rd
+nvgpu_mem_rd32
+nvgpu_mem_rd_n
+nvgpu_memset
+nvgpu_mem_wr
+nvgpu_mem_wr32
+nvgpu_mem_wr_n
+nvgpu_mm_get_available_big_page_sizes
+nvgpu_mm_get_default_big_page_size
+nvgpu_mm_suspend
+nvgpu_msleep
+nvgpu_mutex_acquire
+nvgpu_mutex_destroy
+nvgpu_mutex_init
+nvgpu_mutex_release
+nvgpu_mutex_tryacquire
+nvgpu_nvlink_enumerate
+nvgpu_nvlink_train
+nvgpu_os_buf_get_size
+nvgpu_page_allocator_init
+__nvgpu_pd_alloc
+__nvgpu_pd_cache_alloc_direct
+nvgpu_pd_cache_fini
+__nvgpu_pd_cache_free_direct
+nvgpu_pd_cache_init
+__nvgpu_pd_free
+nvgpu_platform_is_fpga
+nvgpu_platform_is_silicon
+nvgpu_platform_is_simulation
+nvgpu_pmu_ap_send_command
+nvgpu_pmu_cmd_post
+nvgpu_pmu_destroy
+nvgpu_pmu_disable_elpg
+nvgpu_pmu_dump_elpg_stats
+nvgpu_pmu_dump_falcon_stats
+nvgpu_pmu_enable_elpg
+nvgpu_pmu_get_load_counters
+nvgpu_pmu_get_pg_stats
+nvgpu_pmu_handle_perfmon_event
+nvgpu_pmu_handle_therm_event
+nvgpu_pmu_init_bind_fecs
+nvgpu_pmu_init_perfmon
+nvgpu_pmu_init_perfmon_rpc
+nvgpu_pmu_init_powergating
+nvgpu_pmu_load_norm
+nvgpu_pmu_load_update
+nvgpu_pmu_mutex_acquire
+nvgpu_pmu_mutex_release
+nvgpu_pmu_perfmon_get_samples_rpc
+nvgpu_pmu_perfmon_start_sampling
+nvgpu_pmu_perfmon_start_sampling_rpc
+nvgpu_pmu_perfmon_stop_sampling
+nvgpu_pmu_perfmon_stop_sampling_rpc
+nvgpu_pmu_pg_global_enable
+nvgpu_pmu_prepare_ns_ucode_blob
+nvgpu_pmu_process_init_msg
+nvgpu_pmu_process_message
+nvgpu_pmu_queue_init
+nvgpu_pmu_queue_is_empty
+nvgpu_pmu_reset
+nvgpu_pmu_reset_load_counters
+nvgpu_pmu_rpc_execute
+nvgpu_pmu_seq_init
+nvgpu_pmu_setup_hw_load_zbc
+nvgpu_pmu_state_change
+nvgpu_pmu_super_surface_alloc
+nvgpu_pmu_surface_describe
+nvgpu_pmu_surface_free
+nvgpu_pmu_sysmem_surface_alloc
+nvgpu_pmu_vidmem_surface_alloc
+nvgpu_posix_cleanup
+__nvgpu_posix_ffs
+__nvgpu_posix_fls
+nvgpu_posix_probe
+nvgpu_pramin_access_batched
+__nvgpu_pte_words
+nvgpu_raw_spinlock_acquire
+nvgpu_raw_spinlock_init
+nvgpu_raw_spinlock_release
+nvgpu_rbtree_enum_next
+nvgpu_rbtree_enum_start
+nvgpu_rbtree_insert
+nvgpu_rbtree_less_than_search
+nvgpu_rbtree_range_search
+nvgpu_rbtree_search
+nvgpu_rbtree_unlink
+__nvgpu_readl
+nvgpu_readl
+nvgpu_release_firmware
+nvgpu_release_profiler_reservation
+nvgpu_remove_mapped_buf
+nvgpu_request_firmware
+nvgpu_rwsem_down_read
+nvgpu_rwsem_down_write
+nvgpu_rwsem_init
+nvgpu_rwsem_up_read
+nvgpu_rwsem_up_write
+nvgpu_semaphore_alloc
+nvgpu_semaphore_free_hw_sema
+nvgpu_semaphore_get
+nvgpu_semaphore_get_sea
+nvgpu_semaphore_pool_alloc
+nvgpu_semaphore_pool_get
+__nvgpu_semaphore_pool_gpu_va
+nvgpu_semaphore_pool_map
+nvgpu_semaphore_pool_put
+nvgpu_semaphore_pool_unmap
+nvgpu_semaphore_put
+nvgpu_semaphore_sea_create
+nvgpu_semaphore_sea_destroy
+__nvgpu_set_enabled
+nvgpu_set_error_notifier
+nvgpu_set_error_notifier_if_empty
+nvgpu_set_error_notifier_locked
+__nvgpu_set_pte
+nvgpu_sgt_alignment
+nvgpu_sgt_create_from_mem
+nvgpu_sgt_free
+nvgpu_sgt_get_dma
+nvgpu_sgt_get_gpu_addr
+nvgpu_sgt_get_length
+nvgpu_sgt_get_next
+nvgpu_sgt_get_phys
+nvgpu_sgt_iommuable
+nvgpu_spinlock_acquire
+nvgpu_spinlock_init
+nvgpu_spinlock_release
+nvgpu_tegra_fuse_read_gcplex_config_fuse
+nvgpu_tegra_fuse_read_reserved_calib
+nvgpu_tegra_fuse_write_access_sw
+nvgpu_tegra_fuse_write_bypass
+nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable
+nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable
+nvgpu_tegra_get_gpu_speedo_id
+nvgpu_thread_create
+nvgpu_thread_is_running
+nvgpu_thread_should_stop
+nvgpu_thread_stop
+__nvgpu_timeout_expired_msg
+nvgpu_timeout_init
+nvgpu_timeout_peek_expired
+nvgpu_udelay
+nvgpu_usermode_writel
+nvgpu_usleep_range
+__nvgpu_vfree
+__nvgpu_vmalloc
+__nvgpu_vm_alloc_va
+nvgpu_vm_area_alloc
+nvgpu_vm_area_find
+nvgpu_vm_area_free
+nvgpu_vm_area_validate_buffer
+__nvgpu_vm_find_mapped_buf
+__nvgpu_vm_find_mapped_buf_less_than
+__nvgpu_vm_find_mapped_buf_range
+nvgpu_vm_find_mapping
+__nvgpu_vm_free_va
+nvgpu_vm_get
+nvgpu_vm_get_buffers
+__nvgpu_vm_init
+nvgpu_vm_init
+nvgpu_vm_map
+nvgpu_vm_mapping_batch_finish
+nvgpu_vm_mapping_batch_finish_locked
+nvgpu_vm_mapping_batch_start
+nvgpu_vm_pde_coverage_bit_count
+nvgpu_vm_put
+nvgpu_vm_put_buffers
+nvgpu_vm_unmap
+__nvgpu_vm_unmap_ref
+nvgpu_vm_unmap_system
+nvgpu_volt_rail_get_voltage_gp10x
+nvgpu_volt_rail_get_voltage_gv10x
+nvgpu_volt_send_load_cmd_to_pmu_gp10x
+nvgpu_volt_send_load_cmd_to_pmu_gv10x
+nvgpu_volt_set_voltage_gp10x
+nvgpu_volt_set_voltage_gv10x
+__nvgpu_vzalloc
+nvgpu_wait_for_deferred_interrupts
+nvgpu_writel
+nvgpu_writel_check
+perf_pmu_vfe_load
+pmgr_device_sw_setup
+pmgr_domain_pmu_setup
+pmgr_domain_sw_setup
+pmgr_monitor_sw_setup
+pmgr_pmu_pwr_devices_query_blocking
+pmgr_policy_sw_setup
+pmgr_pwr_devices_get_current
+pmgr_pwr_devices_get_power
+pmgr_pwr_devices_get_voltage
+pmgr_send_pmgr_tables_to_pmu
+pmu_bootstrap
+pmu_dump_security_fuses_gm20b
+pmu_dump_security_fuses_gp10b
+pmu_enable_irq
+pmu_exec_gen_bl
+pmu_handle_fecs_boot_acr_msg
+pmu_ucode_details
+pmu_wait_for_halt
+pmu_wait_message_cond
+prepare_ucode_blob
+pstate_find
+pstate_get_clk_set_info
+reg_op_is_gr_ctx
+reg_op_is_read
+sec2_clear_halt_interrupt_status
+sec2_wait_for_halt
+set_bit
+test_and_clear_bit
+test_and_set_bit
+test_bit
+therm_channel_sw_setup
+therm_configure_therm_alert
+therm_device_sw_setup
+therm_domain_pmu_setup
+therm_domain_sw_setup
+therm_send_pmgr_tables_to_pmu
+tsg_gk20a_from_ch
+vfe_equ_pmu_setup
+vfe_equ_sw_setup
+vfe_var_pmu_setup
+vfe_var_sw_setup
+vm_aspace_id
+volt_dev_pmu_setup
+volt_dev_sw_setup
+volt_get_voltage
+volt_policy_pmu_setup
+volt_policy_sw_setup
+volt_rail_pmu_setup
+volt_rail_sw_setup
+volt_rail_vbios_volt_domain_convert_to_internal
+volt_rail_volt_dev_register
+volt_rail_volt_domain_convert_to_idx
+volt_set_noiseaware_vmin
+volt_set_voltage
+__warn
+xve_available_speeds_gp106
+xve_disable_aspm_gp106
+xve_disable_shadow_rom_gp106
+xve_enable_shadow_rom_gp106
+xve_get_link_control_status
+xve_get_speed_gp106
+xve_reset_gpu_gp106
+xve_set_speed_gp106
+xve_xve_readl_gp106
+xve_xve_writel_gp106
diff --git a/include/trace/events/gk20a.h b/include/trace/events/gk20a.h
index 9600b201..99726e4c 100644
--- a/include/trace/events/gk20a.h
+++ b/include/trace/events/gk20a.h
@@ -13,6 +13,8 @@
  * more details.
  */
 
+#ifdef __KERNEL__
+
 #undef TRACE_SYSTEM
 #define TRACE_SYSTEM gk20a
 
@@ -577,3 +579,26 @@ DEFINE_EVENT(gk20a_cde, gk20a_cde_finished_ctx_cb,
 
 /* This part must be outside protection */
 #include <trace/define_trace.h>
+
+#else /* Not __KERNEL__ */
+
+#define trace_gk20a_mmu_fault(arg...)                   ((void)(NULL))
+#define trace_gk20a_release_used_channel(arg...)        ((void)(NULL))
+#define trace_gk20a_free_channel(arg...)                ((void)(NULL))
+#define trace_gk20a_channel_get(arg...)                 ((void)(NULL))
+#define trace_gk20a_channel_put(arg...)                 ((void)(NULL))
+#define trace_gk20a_open_new_channel(arg...)            ((void)(NULL))
+#define trace_gk20a_channel_update(arg...)              ((void)(NULL))
+
+#define trace_gk20a_mm_fb_flush(arg...)                 ((void)(NULL))
+#define trace_gk20a_mm_fb_flush_done(arg...)            ((void)(NULL))
+#define trace_gk20a_mm_l2_invalidate(arg...)            ((void)(NULL))
+#define trace_gk20a_mm_l2_invalidate_done(arg...)       ((void)(NULL))
+#define trace_gk20a_mm_l2_flush(arg...)                 ((void)(NULL))
+#define trace_gk20a_mm_l2_flush_done(arg...)            ((void)(NULL))
+#define trace_gk20a_mm_tlb_invalidate(arg...)           ((void)(NULL))
+#define trace_gk20a_mm_tlb_invalidate_done(arg...)      ((void)(NULL))
+#define trace_gk20a_ltc_cbc_ctrl_start(arg...)          ((void)(NULL))
+#define trace_gk20a_ltc_cbc_ctrl_done(arg...)           ((void)(NULL))
+
+#endif
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index 8a578102..d97f8fb6 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -21,6 +21,7 @@
 
 #if !defined(__KERNEL__)
 #define __user
+#define __packed __attribute__((packed))
 #endif
 
 /*
diff --git a/userspace/.gitignore b/userspace/.gitignore
new file mode 100644
index 00000000..d1638636
--- /dev/null
+++ b/userspace/.gitignore
@@ -0,0 +1 @@
+build/
\ No newline at end of file
diff --git a/userspace/Makefile b/userspace/Makefile
new file mode 100644
index 00000000..70e93bad
--- /dev/null
+++ b/userspace/Makefile
@@ -0,0 +1,73 @@
+# Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+# Turn off suffix rules. They are deprecated.
+.SUFFIXES:
+
+# Full paths. Makes submakefiles easier. That said this make file _must_ be run
+# from <NVGPU>/userspace/.
+TWD=$(CURDIR)
+
+# Top level out dir.
+OUT=$(TWD)/build
+
+# Nvgpu driver code.
+NVGPU_SRC=$(TWD)/../drivers/gpu/nvgpu
+NVGPU_OUT=$(OUT)/libnvgpu
+
+INCLUDES=                       \
+        -I$(NVGPU_SRC)          \
+        -I$(NVGPU_SRC)/include  \
+        -I../include            \
+        -I../include/uapi
+
+CONFIGS=                        \
+        -D__NVGPU_POSIX__
+
+# Compiler, c-flags, etc.
+
+# CC    = clang
+CC      = gcc
+CFLAGS  = -Wall -ggdb  -Werror -fPIC $(INCLUDES) $(CONFIGS)
+LIBS    = -lpthread -pthread
+
+# Source files. We expect $(OBJS) and $(HEADERS) to get filled in here.
+include Makefile.sources
+
+# Linuxy configs. We want these so that we can mirror builds from the actual
+# Linux kernel.
+include Makefile.configs
+
+all: $(OUT)/libnvgpu-drv.so
+
+$(OUT)/libnvgpu-drv.so: $(OBJS)
+        $(CC) -shared -o $(OUT)/libnvgpu-drv.so $(OBJS) -lgcov
+
+# Default build target for all the object files we want to build in userspace.
+$(NVGPU_OUT)/%.o : $(NVGPU_SRC)/%.c $(HEADERS)
+        @if [ ! -d $(dir $@) ] ; then \
+                mkdir -p $(dir $@) ; \
+        fi
+        $(CC) $(CFLAGS) $(configs) -c -o $@ $<
+
+.PHONY: clean
+
+clean:
+        rm -rf $(OUT)
diff --git a/userspace/Makefile.configs b/userspace/Makefile.configs
new file mode 100644
index 00000000..d7e807af
--- /dev/null
+++ b/userspace/Makefile.configs
@@ -0,0 +1,15 @@
+#
+# Define various configs such as VIDMEM, etc. This is a bit annoying since
+# this really should be specific to Linux, but many header files need to
+# be aware of the CONFIG_* defines. As such we replicate some of the configs
+# that we potientially will want enabled in testing.
+#
+
+configs :=
+
+# Enabled configs.
+# None right now!
+
+# Uncomment these to enable the config.
+# configs += -DCONFIG_NVGPU_TRACK_MEM_USAGE=y
+# configs += -DCONFIG_GK20A_VIDMEM
diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources
new file mode 100644
index 00000000..3598c971
--- /dev/null
+++ b/userspace/Makefile.sources
@@ -0,0 +1,34 @@
+# -*- mode: makefile -*-
+#
+# Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+include ../drivers/gpu/nvgpu/Makefile.sources
+
+OBJS := $(srcs:%.c=$(NVGPU_OUT)/%.o)
+
+
+HEADERS :=      \
+        $(NVGPU_SRC)/include/nvgpu/*.h          \
+        $(NVGPU_SRC)/include/nvgpu/hw/*/*.h     \
+        $(NVGPU_SRC)/gk20a/*.h                  \
+        $(NVGPU_SRC)/gm20b/*.h                  \
+        $(NVGPU_SRC)/gp10b/*.h                  \
+        $(NVGPU_SRC)/gv11b/*.h
diff --git a/userspace/README.txt b/userspace/README.txt
new file mode 100644
index 00000000..2599716a
--- /dev/null
+++ b/userspace/README.txt
@@ -0,0 +1,12 @@
+
+
+                              NVGPU in userspace!
+                              ~~~~~~~~~~~~~~~~~~~
+
+1. Why do this?
+
+    Unit testing. Safety. Code coverage. Etc.
+
+2. Design and implementation
+
+    Hrmm.
diff --git a/userspace/src/Makefile.tmk b/userspace/src/Makefile.tmk
new file mode 100644
index 00000000..f2da773d
--- /dev/null
+++ b/userspace/src/Makefile.tmk
@@ -0,0 +1,46 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2014-2016 NVIDIA CORPORATION.  All Rights Reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+# tmake for SW Mobile component makefile
+#
+# Component makefile for compiling host submit tests as a part of an umbrella.
+#
+###############################################################################
+
+ifdef NV_COMPONENT_FLAG_NVTEST_EXECUTABLE_SECTION
+include $(NV_BUILD_START_COMPONENT)
+
+NV_COMPONENT_NAME               := nvgpu_unit
+
+NV_COMPONENT_SOURCES            := unit_main.c  \
+                                   nvgpu.c      \
+                                   args.c       \
+                                   io.c         \
+                                   module.c     \
+                                   results.c    \
+                                   exec.c
+
+# The actual userspace nvgpu library.
+NV_COMPONENT_NEEDED_INTERFACE_DIRS := ../../drivers/gpu/nvgpu
+
+NV_COMPONENT_INCLUDES           := ../include                   \
+                                   ../../drivers/gpu/nvgpu      \
+                                   ../../drivers/gpu/nvgpu/include
+
+
+
+include $(NV_BUILD_NVTEST_EXECUTABLE)
+endif
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab: