diff options
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 350 |
1 files changed, 161 insertions, 189 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 204c0105..823da61a 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -100,15 +100,15 @@ | |||
100 | static const struct gpu_ops vgpu_gv11b_ops = { | 100 | static const struct gpu_ops vgpu_gv11b_ops = { |
101 | .ltc = { | 101 | .ltc = { |
102 | .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, | 102 | .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, |
103 | .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, | 103 | .set_zbc_s_entry = NULL, |
104 | .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, | 104 | .set_zbc_color_entry = NULL, |
105 | .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, | 105 | .set_zbc_depth_entry = NULL, |
106 | .init_cbc = NULL, | 106 | .init_cbc = NULL, |
107 | .init_fs_state = vgpu_ltc_init_fs_state, | 107 | .init_fs_state = vgpu_ltc_init_fs_state, |
108 | .init_comptags = vgpu_ltc_init_comptags, | 108 | .init_comptags = vgpu_ltc_init_comptags, |
109 | .cbc_ctrl = NULL, | 109 | .cbc_ctrl = NULL, |
110 | .isr = gv11b_ltc_isr, | 110 | .isr = NULL, |
111 | .flush = gm20b_flush_ltc, | 111 | .flush = NULL, |
112 | .set_enabled = NULL, | 112 | .set_enabled = NULL, |
113 | .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr, | 113 | .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr, |
114 | .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr, | 114 | .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr, |
@@ -117,12 +117,12 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
117 | .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr, | 117 | .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr, |
118 | }, | 118 | }, |
119 | .ce2 = { | 119 | .ce2 = { |
120 | .isr_stall = gv11b_ce_isr, | 120 | .isr_stall = NULL, |
121 | .isr_nonstall = gp10b_ce_nonstall_isr, | 121 | .isr_nonstall = NULL, |
122 | .get_num_pce = vgpu_ce_get_num_pce, | 122 | .get_num_pce = vgpu_ce_get_num_pce, |
123 | }, | 123 | }, |
124 | .gr = { | 124 | .gr = { |
125 | .init_gpc_mmu = gr_gv11b_init_gpc_mmu, | 125 | .init_gpc_mmu = NULL, |
126 | .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, | 126 | .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, |
127 | .cb_size_default = gr_gv11b_cb_size_default, | 127 | .cb_size_default = gr_gv11b_cb_size_default, |
128 | .calc_global_ctx_buffer_size = | 128 | .calc_global_ctx_buffer_size = |
@@ -131,21 +131,20 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
131 | .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, | 131 | .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, |
132 | .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, | 132 | .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, |
133 | .commit_global_pagepool = gr_gp10b_commit_global_pagepool, | 133 | .commit_global_pagepool = gr_gp10b_commit_global_pagepool, |
134 | .handle_sw_method = gr_gv11b_handle_sw_method, | 134 | .handle_sw_method = NULL, |
135 | .set_alpha_circular_buffer_size = | 135 | .set_alpha_circular_buffer_size = NULL, |
136 | gr_gv11b_set_alpha_circular_buffer_size, | 136 | .set_circular_buffer_size = NULL, |
137 | .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, | 137 | .enable_hww_exceptions = NULL, |
138 | .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions, | ||
139 | .is_valid_class = gr_gv11b_is_valid_class, | 138 | .is_valid_class = gr_gv11b_is_valid_class, |
140 | .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, | 139 | .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, |
141 | .is_valid_compute_class = gr_gv11b_is_valid_compute_class, | 140 | .is_valid_compute_class = gr_gv11b_is_valid_compute_class, |
142 | .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, | 141 | .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, |
143 | .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, | 142 | .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, |
144 | .init_fs_state = vgpu_gr_init_fs_state, | 143 | .init_fs_state = vgpu_gr_init_fs_state, |
145 | .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, | 144 | .set_hww_esr_report_mask = NULL, |
146 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | 145 | .falcon_load_ucode = NULL, |
147 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, | 146 | .load_ctxsw_ucode = NULL, |
148 | .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, | 147 | .set_gpc_tpc_mask = NULL, |
149 | .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, | 148 | .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, |
150 | .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, | 149 | .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, |
151 | .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, | 150 | .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, |
@@ -153,12 +152,12 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
153 | .is_tpc_addr = gr_gm20b_is_tpc_addr, | 152 | .is_tpc_addr = gr_gm20b_is_tpc_addr, |
154 | .get_tpc_num = gr_gm20b_get_tpc_num, | 153 | .get_tpc_num = gr_gm20b_get_tpc_num, |
155 | .detect_sm_arch = vgpu_gr_detect_sm_arch, | 154 | .detect_sm_arch = vgpu_gr_detect_sm_arch, |
156 | .add_zbc_color = gr_gp10b_add_zbc_color, | 155 | .add_zbc_color = NULL, |
157 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | 156 | .add_zbc_depth = NULL, |
158 | .zbc_set_table = vgpu_gr_add_zbc, | 157 | .zbc_set_table = vgpu_gr_add_zbc, |
159 | .zbc_query_table = vgpu_gr_query_zbc, | 158 | .zbc_query_table = vgpu_gr_query_zbc, |
160 | .pmu_save_zbc = gk20a_pmu_save_zbc, | 159 | .pmu_save_zbc = NULL, |
161 | .add_zbc = gr_gk20a_add_zbc, | 160 | .add_zbc = NULL, |
162 | .pagepool_default_size = gr_gv11b_pagepool_default_size, | 161 | .pagepool_default_size = gr_gv11b_pagepool_default_size, |
163 | .init_ctx_state = vgpu_gr_gp10b_init_ctx_state, | 162 | .init_ctx_state = vgpu_gr_gp10b_init_ctx_state, |
164 | .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx, | 163 | .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx, |
@@ -173,66 +172,66 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
173 | .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, | 172 | .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, |
174 | .get_max_fbps_count = vgpu_gr_get_max_fbps_count, | 173 | .get_max_fbps_count = vgpu_gr_get_max_fbps_count, |
175 | .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, | 174 | .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, |
176 | .wait_empty = gr_gv11b_wait_empty, | 175 | .wait_empty = NULL, |
177 | .init_cyclestats = vgpu_gr_gm20b_init_cyclestats, | 176 | .init_cyclestats = vgpu_gr_gm20b_init_cyclestats, |
178 | .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, | 177 | .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, |
179 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, | 178 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, |
180 | .bpt_reg_info = gv11b_gr_bpt_reg_info, | 179 | .bpt_reg_info = NULL, |
181 | .get_access_map = gr_gv11b_get_access_map, | 180 | .get_access_map = gr_gv11b_get_access_map, |
182 | .handle_fecs_error = gr_gv11b_handle_fecs_error, | 181 | .handle_fecs_error = NULL, |
183 | .handle_sm_exception = gr_gk20a_handle_sm_exception, | 182 | .handle_sm_exception = NULL, |
184 | .handle_tex_exception = gr_gv11b_handle_tex_exception, | 183 | .handle_tex_exception = NULL, |
185 | .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions, | 184 | .enable_gpc_exceptions = NULL, |
186 | .enable_exceptions = gr_gv11b_enable_exceptions, | 185 | .enable_exceptions = NULL, |
187 | .get_lrf_tex_ltc_dram_override = get_ecc_override_val, | 186 | .get_lrf_tex_ltc_dram_override = NULL, |
188 | .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, | 187 | .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, |
189 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, | 188 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, |
190 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | 189 | .record_sm_error_state = gv11b_gr_record_sm_error_state, |
191 | .update_sm_error_state = gv11b_gr_update_sm_error_state, | 190 | .update_sm_error_state = NULL, |
192 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, | 191 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, |
193 | .suspend_contexts = vgpu_gr_suspend_contexts, | 192 | .suspend_contexts = vgpu_gr_suspend_contexts, |
194 | .resume_contexts = vgpu_gr_resume_contexts, | 193 | .resume_contexts = vgpu_gr_resume_contexts, |
195 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | 194 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, |
196 | .init_sm_id_table = vgpu_gr_init_sm_id_table, | 195 | .init_sm_id_table = vgpu_gr_init_sm_id_table, |
197 | .load_smid_config = gr_gv11b_load_smid_config, | 196 | .load_smid_config = NULL, |
198 | .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, | 197 | .program_sm_id_numbering = NULL, |
199 | .setup_rop_mapping = gr_gv11b_setup_rop_mapping, | 198 | .setup_rop_mapping = NULL, |
200 | .program_zcull_mapping = gr_gv11b_program_zcull_mapping, | 199 | .program_zcull_mapping = NULL, |
201 | .commit_global_timeslice = gr_gv11b_commit_global_timeslice, | 200 | .commit_global_timeslice = NULL, |
202 | .commit_inst = vgpu_gr_gv11b_commit_inst, | 201 | .commit_inst = vgpu_gr_gv11b_commit_inst, |
203 | .write_zcull_ptr = gr_gv11b_write_zcull_ptr, | 202 | .write_zcull_ptr = gr_gv11b_write_zcull_ptr, |
204 | .write_pm_ptr = gr_gv11b_write_pm_ptr, | 203 | .write_pm_ptr = gr_gv11b_write_pm_ptr, |
205 | .load_tpc_mask = gr_gv11b_load_tpc_mask, | 204 | .load_tpc_mask = NULL, |
206 | .trigger_suspend = gv11b_gr_sm_trigger_suspend, | 205 | .trigger_suspend = NULL, |
207 | .wait_for_pause = gr_gk20a_wait_for_pause, | 206 | .wait_for_pause = gr_gk20a_wait_for_pause, |
208 | .resume_from_pause = gv11b_gr_resume_from_pause, | 207 | .resume_from_pause = NULL, |
209 | .clear_sm_errors = gr_gk20a_clear_sm_errors, | 208 | .clear_sm_errors = gr_gk20a_clear_sm_errors, |
210 | .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, | 209 | .tpc_enabled_exceptions = NULL, |
211 | .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, | 210 | .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, |
212 | .sm_debugger_attached = gv11b_gr_sm_debugger_attached, | 211 | .sm_debugger_attached = NULL, |
213 | .suspend_single_sm = gv11b_gr_suspend_single_sm, | 212 | .suspend_single_sm = NULL, |
214 | .suspend_all_sms = gv11b_gr_suspend_all_sms, | 213 | .suspend_all_sms = NULL, |
215 | .resume_single_sm = gv11b_gr_resume_single_sm, | 214 | .resume_single_sm = NULL, |
216 | .resume_all_sms = gv11b_gr_resume_all_sms, | 215 | .resume_all_sms = NULL, |
217 | .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr, | 216 | .get_sm_hww_warp_esr = NULL, |
218 | .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr, | 217 | .get_sm_hww_global_esr = NULL, |
219 | .get_sm_no_lock_down_hww_global_esr_mask = | 218 | .get_sm_no_lock_down_hww_global_esr_mask = |
220 | gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, | 219 | gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, |
221 | .lock_down_sm = gv11b_gr_lock_down_sm, | 220 | .lock_down_sm = NULL, |
222 | .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, | 221 | .wait_for_sm_lock_down = NULL, |
223 | .clear_sm_hww = gv11b_gr_clear_sm_hww, | 222 | .clear_sm_hww = NULL, |
224 | .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, | 223 | .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, |
225 | .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, | 224 | .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, |
226 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | 225 | .disable_rd_coalesce = NULL, |
227 | .set_boosted_ctx = NULL, | 226 | .set_boosted_ctx = NULL, |
228 | .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode, | 227 | .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode, |
229 | .set_czf_bypass = NULL, | 228 | .set_czf_bypass = NULL, |
230 | .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, | 229 | .pre_process_sm_exception = NULL, |
231 | .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, | 230 | .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, |
232 | .init_preemption_state = NULL, | 231 | .init_preemption_state = NULL, |
233 | .update_boosted_ctx = NULL, | 232 | .update_boosted_ctx = NULL, |
234 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, | 233 | .set_bes_crop_debug3 = NULL, |
235 | .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4, | 234 | .set_bes_crop_debug4 = NULL, |
236 | .set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode, | 235 | .set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode, |
237 | .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, | 236 | .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, |
238 | .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, | 237 | .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, |
@@ -274,19 +273,18 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
274 | gr_gk20a_get_offset_in_gpccs_segment, | 273 | gr_gk20a_get_offset_in_gpccs_segment, |
275 | }, | 274 | }, |
276 | .fb = { | 275 | .fb = { |
277 | .reset = gv11b_fb_reset, | 276 | .reset = NULL, |
278 | .init_hw = gk20a_fb_init_hw, | 277 | .init_hw = NULL, |
279 | .init_fs_state = gv11b_fb_init_fs_state, | 278 | .init_fs_state = NULL, |
280 | .init_cbc = gv11b_fb_init_cbc, | 279 | .init_cbc = NULL, |
281 | .set_mmu_page_size = gm20b_fb_set_mmu_page_size, | 280 | .set_mmu_page_size = NULL, |
282 | .set_use_full_comp_tag_line = | 281 | .set_use_full_comp_tag_line = NULL, |
283 | gm20b_fb_set_use_full_comp_tag_line, | ||
284 | .compression_page_size = gp10b_fb_compression_page_size, | 282 | .compression_page_size = gp10b_fb_compression_page_size, |
285 | .compressible_page_size = gp10b_fb_compressible_page_size, | 283 | .compressible_page_size = gp10b_fb_compressible_page_size, |
286 | .compression_align_mask = gm20b_fb_compression_align_mask, | 284 | .compression_align_mask = gm20b_fb_compression_align_mask, |
287 | .vpr_info_fetch = gm20b_fb_vpr_info_fetch, | 285 | .vpr_info_fetch = NULL, |
288 | .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, | 286 | .dump_vpr_wpr_info = NULL, |
289 | .read_wpr_info = gm20b_fb_read_wpr_info, | 287 | .read_wpr_info = NULL, |
290 | .is_debug_mode_enabled = NULL, | 288 | .is_debug_mode_enabled = NULL, |
291 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, | 289 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, |
292 | .tlb_invalidate = vgpu_mm_tlb_invalidate, | 290 | .tlb_invalidate = vgpu_mm_tlb_invalidate, |
@@ -312,54 +310,30 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
312 | .read_mmu_fault_status = fb_gv11b_read_mmu_fault_status, | 310 | .read_mmu_fault_status = fb_gv11b_read_mmu_fault_status, |
313 | }, | 311 | }, |
314 | .clock_gating = { | 312 | .clock_gating = { |
315 | .slcg_bus_load_gating_prod = | 313 | .slcg_bus_load_gating_prod = NULL, |
316 | gv11b_slcg_bus_load_gating_prod, | 314 | .slcg_ce2_load_gating_prod = NULL, |
317 | .slcg_ce2_load_gating_prod = | 315 | .slcg_chiplet_load_gating_prod = NULL, |
318 | gv11b_slcg_ce2_load_gating_prod, | 316 | .slcg_ctxsw_firmware_load_gating_prod = NULL, |
319 | .slcg_chiplet_load_gating_prod = | 317 | .slcg_fb_load_gating_prod = NULL, |
320 | gv11b_slcg_chiplet_load_gating_prod, | 318 | .slcg_fifo_load_gating_prod = NULL, |
321 | .slcg_ctxsw_firmware_load_gating_prod = | 319 | .slcg_gr_load_gating_prod = NULL, |
322 | gv11b_slcg_ctxsw_firmware_load_gating_prod, | 320 | .slcg_ltc_load_gating_prod = NULL, |
323 | .slcg_fb_load_gating_prod = | 321 | .slcg_perf_load_gating_prod = NULL, |
324 | gv11b_slcg_fb_load_gating_prod, | 322 | .slcg_priring_load_gating_prod = NULL, |
325 | .slcg_fifo_load_gating_prod = | 323 | .slcg_pmu_load_gating_prod = NULL, |
326 | gv11b_slcg_fifo_load_gating_prod, | 324 | .slcg_therm_load_gating_prod = NULL, |
327 | .slcg_gr_load_gating_prod = | 325 | .slcg_xbar_load_gating_prod = NULL, |
328 | gr_gv11b_slcg_gr_load_gating_prod, | 326 | .blcg_bus_load_gating_prod = NULL, |
329 | .slcg_ltc_load_gating_prod = | 327 | .blcg_ce_load_gating_prod = NULL, |
330 | ltc_gv11b_slcg_ltc_load_gating_prod, | 328 | .blcg_ctxsw_firmware_load_gating_prod = NULL, |
331 | .slcg_perf_load_gating_prod = | 329 | .blcg_fb_load_gating_prod = NULL, |
332 | gv11b_slcg_perf_load_gating_prod, | 330 | .blcg_fifo_load_gating_prod = NULL, |
333 | .slcg_priring_load_gating_prod = | 331 | .blcg_gr_load_gating_prod = NULL, |
334 | gv11b_slcg_priring_load_gating_prod, | 332 | .blcg_ltc_load_gating_prod = NULL, |
335 | .slcg_pmu_load_gating_prod = | 333 | .blcg_pwr_csb_load_gating_prod = NULL, |
336 | gv11b_slcg_pmu_load_gating_prod, | 334 | .blcg_pmu_load_gating_prod = NULL, |
337 | .slcg_therm_load_gating_prod = | 335 | .blcg_xbar_load_gating_prod = NULL, |
338 | gv11b_slcg_therm_load_gating_prod, | 336 | .pg_gr_load_gating_prod = NULL, |
339 | .slcg_xbar_load_gating_prod = | ||
340 | gv11b_slcg_xbar_load_gating_prod, | ||
341 | .blcg_bus_load_gating_prod = | ||
342 | gv11b_blcg_bus_load_gating_prod, | ||
343 | .blcg_ce_load_gating_prod = | ||
344 | gv11b_blcg_ce_load_gating_prod, | ||
345 | .blcg_ctxsw_firmware_load_gating_prod = | ||
346 | gv11b_blcg_ctxsw_firmware_load_gating_prod, | ||
347 | .blcg_fb_load_gating_prod = | ||
348 | gv11b_blcg_fb_load_gating_prod, | ||
349 | .blcg_fifo_load_gating_prod = | ||
350 | gv11b_blcg_fifo_load_gating_prod, | ||
351 | .blcg_gr_load_gating_prod = | ||
352 | gv11b_blcg_gr_load_gating_prod, | ||
353 | .blcg_ltc_load_gating_prod = | ||
354 | gv11b_blcg_ltc_load_gating_prod, | ||
355 | .blcg_pwr_csb_load_gating_prod = | ||
356 | gv11b_blcg_pwr_csb_load_gating_prod, | ||
357 | .blcg_pmu_load_gating_prod = | ||
358 | gv11b_blcg_pmu_load_gating_prod, | ||
359 | .blcg_xbar_load_gating_prod = | ||
360 | gv11b_blcg_xbar_load_gating_prod, | ||
361 | .pg_gr_load_gating_prod = | ||
362 | gr_gv11b_pg_gr_load_gating_prod, | ||
363 | }, | 337 | }, |
364 | .fifo = { | 338 | .fifo = { |
365 | .init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw, | 339 | .init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw, |
@@ -406,16 +380,16 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
406 | .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, | 380 | .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, |
407 | .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, | 381 | .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, |
408 | .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, | 382 | .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, |
409 | .dump_pbdma_status = gk20a_dump_pbdma_status, | 383 | .dump_pbdma_status = NULL, |
410 | .dump_eng_status = gv11b_dump_eng_status, | 384 | .dump_eng_status = NULL, |
411 | .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, | 385 | .dump_channel_status_ramfc = NULL, |
412 | .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, | 386 | .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, |
413 | .is_preempt_pending = gv11b_fifo_is_preempt_pending, | 387 | .is_preempt_pending = gv11b_fifo_is_preempt_pending, |
414 | .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, | 388 | .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, |
415 | .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, | 389 | .reset_enable_hw = NULL, |
416 | .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, | 390 | .teardown_ch_tsg = NULL, |
417 | .handle_sched_error = gv11b_fifo_handle_sched_error, | 391 | .handle_sched_error = NULL, |
418 | .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, | 392 | .handle_pbdma_intr_0 = NULL, |
419 | .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, | 393 | .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, |
420 | .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, | 394 | .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, |
421 | .deinit_eng_method_buffers = | 395 | .deinit_eng_method_buffers = |
@@ -446,8 +420,8 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
446 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | 420 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, |
447 | .free_channel_ctx_header = vgpu_gv11b_free_subctx_header, | 421 | .free_channel_ctx_header = vgpu_gv11b_free_subctx_header, |
448 | .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, | 422 | .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, |
449 | .runlist_hw_submit = gk20a_fifo_runlist_hw_submit, | 423 | .runlist_hw_submit = NULL, |
450 | .runlist_wait_pending = gk20a_fifo_runlist_wait_pending, | 424 | .runlist_wait_pending = NULL, |
451 | .ring_channel_doorbell = gv11b_ring_channel_doorbell, | 425 | .ring_channel_doorbell = gv11b_ring_channel_doorbell, |
452 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, | 426 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, |
453 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, | 427 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, |
@@ -485,7 +459,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
485 | .fb_flush = vgpu_mm_fb_flush, | 459 | .fb_flush = vgpu_mm_fb_flush, |
486 | .l2_invalidate = vgpu_mm_l2_invalidate, | 460 | .l2_invalidate = vgpu_mm_l2_invalidate, |
487 | .l2_flush = vgpu_mm_l2_flush, | 461 | .l2_flush = vgpu_mm_l2_flush, |
488 | .cbc_clean = gk20a_mm_cbc_clean, | 462 | .cbc_clean = NULL, |
489 | .set_big_page_size = gm20b_mm_set_big_page_size, | 463 | .set_big_page_size = gm20b_mm_set_big_page_size, |
490 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | 464 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, |
491 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, | 465 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, |
@@ -496,7 +470,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
496 | .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw, | 470 | .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw, |
497 | .is_bar1_supported = gv11b_mm_is_bar1_supported, | 471 | .is_bar1_supported = gv11b_mm_is_bar1_supported, |
498 | .init_inst_block = gv11b_init_inst_block, | 472 | .init_inst_block = gv11b_init_inst_block, |
499 | .mmu_fault_pending = gv11b_mm_mmu_fault_pending, | 473 | .mmu_fault_pending = NULL, |
500 | .get_kind_invalid = gm20b_get_kind_invalid, | 474 | .get_kind_invalid = gm20b_get_kind_invalid, |
501 | .get_kind_pitch = gm20b_get_kind_pitch, | 475 | .get_kind_pitch = gm20b_get_kind_pitch, |
502 | .init_bar2_vm = gp10b_init_bar2_vm, | 476 | .init_bar2_vm = gp10b_init_bar2_vm, |
@@ -504,38 +478,38 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
504 | .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, | 478 | .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, |
505 | }, | 479 | }, |
506 | .therm = { | 480 | .therm = { |
507 | .init_therm_setup_hw = gp10b_init_therm_setup_hw, | 481 | .init_therm_setup_hw = NULL, |
508 | .init_elcg_mode = gv11b_therm_init_elcg_mode, | 482 | .init_elcg_mode = NULL, |
509 | .init_blcg_mode = gm20b_therm_init_blcg_mode, | 483 | .init_blcg_mode = NULL, |
510 | .elcg_init_idle_filters = gv11b_elcg_init_idle_filters, | 484 | .elcg_init_idle_filters = NULL, |
511 | }, | 485 | }, |
512 | .pmu = { | 486 | .pmu = { |
513 | .pmu_setup_elpg = gp10b_pmu_setup_elpg, | 487 | .pmu_setup_elpg = NULL, |
514 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | 488 | .pmu_get_queue_head = NULL, |
515 | .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, | 489 | .pmu_get_queue_head_size = NULL, |
516 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | 490 | .pmu_get_queue_tail = NULL, |
517 | .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, | 491 | .pmu_get_queue_tail_size = NULL, |
518 | .pmu_queue_head = gk20a_pmu_queue_head, | 492 | .pmu_queue_head = NULL, |
519 | .pmu_queue_tail = gk20a_pmu_queue_tail, | 493 | .pmu_queue_tail = NULL, |
520 | .pmu_msgq_tail = gk20a_pmu_msgq_tail, | 494 | .pmu_msgq_tail = NULL, |
521 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | 495 | .pmu_mutex_size = NULL, |
522 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | 496 | .pmu_mutex_acquire = NULL, |
523 | .pmu_mutex_release = gk20a_pmu_mutex_release, | 497 | .pmu_mutex_release = NULL, |
524 | .write_dmatrfbase = gp10b_write_dmatrfbase, | 498 | .write_dmatrfbase = NULL, |
525 | .pmu_elpg_statistics = gp106_pmu_elpg_statistics, | 499 | .pmu_elpg_statistics = NULL, |
526 | .pmu_init_perfmon = nvgpu_pmu_init_perfmon_rpc, | 500 | .pmu_init_perfmon = NULL, |
527 | .pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling_rpc, | 501 | .pmu_perfmon_start_sampling = NULL, |
528 | .pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling_rpc, | 502 | .pmu_perfmon_stop_sampling = NULL, |
529 | .pmu_perfmon_get_samples_rpc = nvgpu_pmu_perfmon_get_samples_rpc, | 503 | .pmu_perfmon_get_samples_rpc = NULL, |
530 | .pmu_pg_init_param = gv11b_pg_gr_init, | 504 | .pmu_pg_init_param = NULL, |
531 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, | 505 | .pmu_pg_supported_engines_list = NULL, |
532 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, | 506 | .pmu_pg_engines_feature_list = NULL, |
533 | .dump_secure_fuses = pmu_dump_security_fuses_gm20b, | 507 | .dump_secure_fuses = NULL, |
534 | .reset_engine = gp106_pmu_engine_reset, | 508 | .reset_engine = NULL, |
535 | .is_engine_in_reset = gp106_pmu_is_engine_in_reset, | 509 | .is_engine_in_reset = NULL, |
536 | .pmu_nsbootstrap = gv11b_pmu_bootstrap, | 510 | .pmu_nsbootstrap = NULL, |
537 | .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask, | 511 | .pmu_pg_set_sub_feature_mask = NULL, |
538 | .is_pmu_supported = gv11b_is_pmu_supported, | 512 | .is_pmu_supported = NULL, |
539 | }, | 513 | }, |
540 | .regops = { | 514 | .regops = { |
541 | .exec_regops = vgpu_exec_regops, | 515 | .exec_regops = vgpu_exec_regops, |
@@ -562,24 +536,24 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
562 | .apply_smpc_war = gv11b_apply_smpc_war, | 536 | .apply_smpc_war = gv11b_apply_smpc_war, |
563 | }, | 537 | }, |
564 | .mc = { | 538 | .mc = { |
565 | .intr_mask = mc_gp10b_intr_mask, | 539 | .intr_mask = NULL, |
566 | .intr_enable = mc_gv11b_intr_enable, | 540 | .intr_enable = NULL, |
567 | .intr_unit_config = mc_gp10b_intr_unit_config, | 541 | .intr_unit_config = NULL, |
568 | .isr_stall = mc_gp10b_isr_stall, | 542 | .isr_stall = NULL, |
569 | .intr_stall = mc_gp10b_intr_stall, | 543 | .intr_stall = NULL, |
570 | .intr_stall_pause = mc_gp10b_intr_stall_pause, | 544 | .intr_stall_pause = NULL, |
571 | .intr_stall_resume = mc_gp10b_intr_stall_resume, | 545 | .intr_stall_resume = NULL, |
572 | .intr_nonstall = mc_gp10b_intr_nonstall, | 546 | .intr_nonstall = NULL, |
573 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, | 547 | .intr_nonstall_pause = NULL, |
574 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, | 548 | .intr_nonstall_resume = NULL, |
575 | .isr_nonstall = mc_gk20a_isr_nonstall, | 549 | .isr_nonstall = NULL, |
576 | .enable = gk20a_mc_enable, | 550 | .enable = NULL, |
577 | .disable = gk20a_mc_disable, | 551 | .disable = NULL, |
578 | .reset = gk20a_mc_reset, | 552 | .reset = NULL, |
579 | .boot_0 = gk20a_mc_boot_0, | 553 | .boot_0 = NULL, |
580 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | 554 | .is_intr1_pending = NULL, |
581 | .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, | 555 | .is_intr_hub_pending = NULL, |
582 | .log_pending_intrs = mc_gp10b_log_pending_intrs, | 556 | .log_pending_intrs = NULL , |
583 | }, | 557 | }, |
584 | .debug = { | 558 | .debug = { |
585 | .show_dump = NULL, | 559 | .show_dump = NULL, |
@@ -599,11 +573,11 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
599 | .perfbuffer_disable = vgpu_perfbuffer_disable, | 573 | .perfbuffer_disable = vgpu_perfbuffer_disable, |
600 | }, | 574 | }, |
601 | .bus = { | 575 | .bus = { |
602 | .init_hw = gk20a_bus_init_hw, | 576 | .init_hw = NULL, |
603 | .isr = gk20a_bus_isr, | 577 | .isr = NULL, |
604 | .bar1_bind = gm20b_bus_bar1_bind, | 578 | .bar1_bind = NULL, |
605 | .bar2_bind = NULL, | 579 | .bar2_bind = NULL, |
606 | .set_bar0_window = gk20a_bus_set_bar0_window, | 580 | .set_bar0_window = NULL, |
607 | }, | 581 | }, |
608 | .ptimer = { | 582 | .ptimer = { |
609 | .isr = NULL, | 583 | .isr = NULL, |
@@ -625,23 +599,21 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
625 | .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, | 599 | .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, |
626 | }, | 600 | }, |
627 | .priv_ring = { | 601 | .priv_ring = { |
628 | .enable_priv_ring = gm20b_priv_ring_enable, | 602 | .enable_priv_ring = NULL, |
629 | .isr = gp10b_priv_ring_isr, | 603 | .isr = NULL, |
630 | .set_ppriv_timeout_settings = | 604 | .set_ppriv_timeout_settings = NULL, |
631 | gm20b_priv_set_timeout_settings, | 605 | .enum_ltc = NULL, |
632 | .enum_ltc = gm20b_priv_ring_enum_ltc, | ||
633 | }, | 606 | }, |
634 | .fuse = { | 607 | .fuse = { |
635 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | 608 | .is_opt_ecc_enable = NULL, |
636 | .is_opt_feature_override_disable = | 609 | .is_opt_feature_override_disable = NULL, |
637 | gp10b_fuse_is_opt_feature_override_disable, | 610 | .fuse_status_opt_fbio = NULL, |
638 | .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, | 611 | .fuse_status_opt_fbp = NULL, |
639 | .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, | 612 | .fuse_status_opt_rop_l2_fbp = NULL, |
640 | .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, | 613 | .fuse_status_opt_tpc_gpc = NULL, |
641 | .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, | 614 | .fuse_ctrl_opt_tpc_gpc = NULL, |
642 | .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, | 615 | .fuse_opt_sec_debug_en = NULL, |
643 | .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, | 616 | .fuse_opt_priv_sec_en = NULL, |
644 | .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, | ||
645 | .read_vin_cal_fuse_rev = NULL, | 617 | .read_vin_cal_fuse_rev = NULL, |
646 | .read_vin_cal_slope_intercept_fuse = NULL, | 618 | .read_vin_cal_slope_intercept_fuse = NULL, |
647 | .read_vin_cal_gain_offset_fuse = NULL, | 619 | .read_vin_cal_gain_offset_fuse = NULL, |