diff options
-rw-r--r-- | drivers/gpu/nvgpu/gp106/xve_gp106.c | 35 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h | 50 |
2 files changed, 84 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp106/xve_gp106.c b/drivers/gpu/nvgpu/gp106/xve_gp106.c index a0ee8108..561140c6 100644 --- a/drivers/gpu/nvgpu/gp106/xve_gp106.c +++ b/drivers/gpu/nvgpu/gp106/xve_gp106.c | |||
@@ -59,6 +59,40 @@ static u32 xve_xve_readl_gp106(struct gk20a *g, u32 reg) | |||
59 | } | 59 | } |
60 | 60 | ||
61 | /** | 61 | /** |
62 | * Resets the GPU (except the XVE/XP). | ||
63 | */ | ||
64 | static void xve_reset_gpu_gp106(struct gk20a *g) | ||
65 | { | ||
66 | u32 reset; | ||
67 | |||
68 | /* | ||
69 | * This resets the GPU except for the XVE/XP (since then we would lose | ||
70 | * the dGPU from the bus). t18x has a HW limitation where once that | ||
71 | * happens the GPU is gone until the entire system is reset. | ||
72 | * | ||
73 | * We have to use the auto-deassert register since we won't be able to | ||
74 | * access the GPU after the GPU goes into reset. This appears like the | ||
75 | * GPU has dropped from the bus and causes nvgpu to reset the entire | ||
76 | * system. Whoops! | ||
77 | */ | ||
78 | reset = xve_reset_reset_m() | | ||
79 | xve_reset_gpu_on_sw_reset_m() | | ||
80 | xve_reset_counter_en_m() | | ||
81 | xve_reset_counter_val_f(0x7ff) | | ||
82 | xve_reset_clock_on_sw_reset_m() | | ||
83 | xve_reset_clock_counter_en_m() | | ||
84 | xve_reset_clock_counter_val_f(0x7ff); | ||
85 | |||
86 | g->ops.xve.xve_writel(g, xve_reset_r(), reset | xve_reset_reset_m()); | ||
87 | |||
88 | /* | ||
89 | * Don't access GPU until _after_ it's back out of reset! | ||
90 | */ | ||
91 | msleep(100); | ||
92 | g->ops.xve.xve_writel(g, xve_reset_r(), 0); | ||
93 | } | ||
94 | |||
95 | /** | ||
62 | * Places one of: | 96 | * Places one of: |
63 | * | 97 | * |
64 | * %GPU_XVE_SPEED_2P5 | 98 | * %GPU_XVE_SPEED_2P5 |
@@ -632,6 +666,7 @@ int gp106_init_xve_ops(struct gpu_ops *gops) | |||
632 | gops->xve.xve_readl = xve_xve_readl_gp106; | 666 | gops->xve.xve_readl = xve_xve_readl_gp106; |
633 | gops->xve.xve_writel = xve_xve_writel_gp106; | 667 | gops->xve.xve_writel = xve_xve_writel_gp106; |
634 | gops->xve.disable_aspm = xve_disable_aspm_gp106; | 668 | gops->xve.disable_aspm = xve_disable_aspm_gp106; |
669 | gops->xve.reset_gpu = xve_reset_gpu_gp106; | ||
635 | 670 | ||
636 | return 0; | 671 | return 0; |
637 | } | 672 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h index 24434ae0..bfcb4883 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -146,4 +146,52 @@ static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r) | |||
146 | { | 146 | { |
147 | return (r >> 8) & 0x1; | 147 | return (r >> 8) & 0x1; |
148 | } | 148 | } |
149 | static inline u32 xve_reset_r(void) | ||
150 | { | ||
151 | return 0x00000718; | ||
152 | } | ||
153 | static inline u32 xve_reset_reset_m(void) | ||
154 | { | ||
155 | return 0x1 << 0; | ||
156 | } | ||
157 | static inline u32 xve_reset_gpu_on_sw_reset_m(void) | ||
158 | { | ||
159 | return 0x1 << 1; | ||
160 | } | ||
161 | static inline u32 xve_reset_counter_en_m(void) | ||
162 | { | ||
163 | return 0x1 << 2; | ||
164 | } | ||
165 | static inline u32 xve_reset_counter_val_f(u32 v) | ||
166 | { | ||
167 | return (v & 0x7ff) << 4; | ||
168 | } | ||
169 | static inline u32 xve_reset_counter_val_m(void) | ||
170 | { | ||
171 | return 0x7ff << 4; | ||
172 | } | ||
173 | static inline u32 xve_reset_counter_val_v(u32 r) | ||
174 | { | ||
175 | return (r >> 4) & 0x7ff; | ||
176 | } | ||
177 | static inline u32 xve_reset_clock_on_sw_reset_m(void) | ||
178 | { | ||
179 | return 0x1 << 15; | ||
180 | } | ||
181 | static inline u32 xve_reset_clock_counter_en_m(void) | ||
182 | { | ||
183 | return 0x1 << 16; | ||
184 | } | ||
185 | static inline u32 xve_reset_clock_counter_val_f(u32 v) | ||
186 | { | ||
187 | return (v & 0x7ff) << 17; | ||
188 | } | ||
189 | static inline u32 xve_reset_clock_counter_val_m(void) | ||
190 | { | ||
191 | return 0x7ff << 17; | ||
192 | } | ||
193 | static inline u32 xve_reset_clock_counter_val_v(u32 r) | ||
194 | { | ||
195 | return (r >> 17) & 0x7ff; | ||
196 | } | ||
149 | #endif | 197 | #endif |