diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 53 |
3 files changed, 35 insertions, 40 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index b9d083e3..a3ae664f 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -918,6 +918,10 @@ static inline u32 gr_fecs_host_int_status_r(void) | |||
918 | { | 918 | { |
919 | return 0x00409c18; | 919 | return 0x00409c18; |
920 | } | 920 | } |
921 | static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) | ||
922 | { | ||
923 | return (v & 0x1) << 16; | ||
924 | } | ||
921 | static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) | 925 | static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) |
922 | { | 926 | { |
923 | return (v & 0x1) << 17; | 927 | return (v & 0x1) << 17; |
@@ -3114,6 +3118,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) | |||
3114 | { | 3118 | { |
3115 | return 0x0; | 3119 | return 0x0; |
3116 | } | 3120 | } |
3121 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) | ||
3122 | { | ||
3123 | return 0x00000000; | ||
3124 | } | ||
3125 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) | ||
3126 | { | ||
3127 | return 0x00000000; | ||
3128 | } | ||
3117 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) | 3129 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) |
3118 | { | 3130 | { |
3119 | return 0x00504614; | 3131 | return 0x00504614; |
@@ -3130,14 +3142,6 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) | |||
3130 | { | 3142 | { |
3131 | return 0x00419e24; | 3143 | return 0x00419e24; |
3132 | } | 3144 | } |
3133 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) | ||
3134 | { | ||
3135 | return 0x00000000; | ||
3136 | } | ||
3137 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void) | ||
3138 | { | ||
3139 | return 0x00000000; | ||
3140 | } | ||
3141 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) | 3145 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) |
3142 | { | 3146 | { |
3143 | return 0x0050460c; | 3147 | return 0x0050460c; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h index d01667bc..a44eac16 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 6357b372..abe1d6a6 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -930,6 +930,10 @@ static inline u32 gr_fecs_host_int_status_r(void) | |||
930 | { | 930 | { |
931 | return 0x00409c18; | 931 | return 0x00409c18; |
932 | } | 932 | } |
933 | static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) | ||
934 | { | ||
935 | return (v & 0x1) << 16; | ||
936 | } | ||
933 | static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) | 937 | static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) |
934 | { | 938 | { |
935 | return (v & 0x1) << 17; | 939 | return (v & 0x1) << 17; |
@@ -3146,41 +3150,41 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) | |||
3146 | { | 3150 | { |
3147 | return 0x0; | 3151 | return 0x0; |
3148 | } | 3152 | } |
3149 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_0_r(void) | 3153 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) |
3150 | { | 3154 | { |
3151 | return 0x00504614; | 3155 | return 0x00000000; |
3152 | } | 3156 | } |
3153 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_0_r(void) | 3157 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) |
3154 | { | 3158 | { |
3155 | return 0x00504624; | 3159 | return 0x00000000; |
3156 | } | 3160 | } |
3157 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_0_r(void) | 3161 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) |
3158 | { | 3162 | { |
3159 | return 0x00504634; | 3163 | return 0x00504614; |
3160 | } | 3164 | } |
3161 | static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) | 3165 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_2_r(void) |
3162 | { | 3166 | { |
3163 | return 0x00419e24; | 3167 | return 0x0050461c; |
3164 | } | 3168 | } |
3165 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) | 3169 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) |
3166 | { | 3170 | { |
3167 | return 0x00000000; | 3171 | return 0x00504624; |
3168 | } | 3172 | } |
3169 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void) | 3173 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_2_r(void) |
3170 | { | 3174 | { |
3171 | return 0x00000000; | 3175 | return 0x00504750; |
3172 | } | 3176 | } |
3173 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_2_r(void) | 3177 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) |
3174 | { | 3178 | { |
3175 | return 0x0050461c; | 3179 | return 0x00504634; |
3176 | } | 3180 | } |
3177 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_2_r(void) | 3181 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_2_r(void) |
3178 | { | 3182 | { |
3179 | return 0x00504750; | 3183 | return 0x00504758; |
3180 | } | 3184 | } |
3181 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_2_r(void) | 3185 | static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) |
3182 | { | 3186 | { |
3183 | return 0x00504758; | 3187 | return 0x00419e24; |
3184 | } | 3188 | } |
3185 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) | 3189 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) |
3186 | { | 3190 | { |
@@ -3566,7 +3570,6 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m(void) | |||
3566 | { | 3570 | { |
3567 | return 0x1 << 12; | 3571 | return 0x1 << 12; |
3568 | } | 3572 | } |
3569 | |||
3570 | static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) | 3573 | static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) |
3571 | { | 3574 | { |
3572 | return 0x1 << 1; | 3575 | return 0x1 << 1; |
@@ -3671,18 +3674,6 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) | |||
3671 | { | 3674 | { |
3672 | return 0x0; | 3675 | return 0x0; |
3673 | } | 3676 | } |
3674 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) | ||
3675 | { | ||
3676 | return 0x00504614; | ||
3677 | } | ||
3678 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) | ||
3679 | { | ||
3680 | return 0x00504624; | ||
3681 | } | ||
3682 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) | ||
3683 | { | ||
3684 | return 0x00504634; | ||
3685 | } | ||
3686 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) | 3677 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) |
3687 | { | 3678 | { |
3688 | return 0x1 << 30; | 3679 | return 0x1 << 30; |