diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 48 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 3 |
9 files changed, 74 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index d5f12f2b..54010a8e 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -1429,14 +1429,6 @@ static int gk20a_probe(struct platform_device *dev) | |||
1429 | if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) | 1429 | if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) |
1430 | gk20a_scale_init(dev); | 1430 | gk20a_scale_init(dev); |
1431 | 1431 | ||
1432 | if (platform->late_probe) { | ||
1433 | err = platform->late_probe(dev); | ||
1434 | if (err) { | ||
1435 | dev_err(&dev->dev, "late probe failed"); | ||
1436 | return err; | ||
1437 | } | ||
1438 | } | ||
1439 | |||
1440 | /* Set DMA parameters to allow larger sgt lists */ | 1432 | /* Set DMA parameters to allow larger sgt lists */ |
1441 | dev->dev.dma_parms = &gk20a->dma_parms; | 1433 | dev->dev.dma_parms = &gk20a->dma_parms; |
1442 | dma_set_max_seg_size(&dev->dev, UINT_MAX); | 1434 | dma_set_max_seg_size(&dev->dev, UINT_MAX); |
@@ -1475,6 +1467,14 @@ static int gk20a_probe(struct platform_device *dev) | |||
1475 | gk20a->pmu.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US; | 1467 | gk20a->pmu.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US; |
1476 | gk20a->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT; | 1468 | gk20a->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT; |
1477 | 1469 | ||
1470 | if (platform->late_probe) { | ||
1471 | err = platform->late_probe(dev); | ||
1472 | if (err) { | ||
1473 | dev_err(&dev->dev, "late probe failed"); | ||
1474 | return err; | ||
1475 | } | ||
1476 | } | ||
1477 | |||
1478 | gk20a_create_sysfs(dev); | 1478 | gk20a_create_sysfs(dev); |
1479 | 1479 | ||
1480 | #ifdef CONFIG_DEBUG_FS | 1480 | #ifdef CONFIG_DEBUG_FS |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 01d1a167..340f358a 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -207,6 +207,7 @@ struct gpu_ops { | |||
207 | int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc, | 207 | int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc, |
208 | bool *post_event); | 208 | bool *post_event); |
209 | void (*create_gr_sysfs)(struct platform_device *dev); | 209 | void (*create_gr_sysfs)(struct platform_device *dev); |
210 | u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g); | ||
210 | } gr; | 211 | } gr; |
211 | const char *name; | 212 | const char *name; |
212 | struct { | 213 | struct { |
@@ -434,6 +435,8 @@ struct gpu_ops { | |||
434 | u32 *gating_cnt); | 435 | u32 *gating_cnt); |
435 | int (*pmu_pg_grinit_param)(struct gk20a *g, | 436 | int (*pmu_pg_grinit_param)(struct gk20a *g, |
436 | u8 grfeaturemask); | 437 | u8 grfeaturemask); |
438 | int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd) | ||
439 | (struct gk20a *g, u32 mask); | ||
437 | u32 lspmuwprinitdone; | 440 | u32 lspmuwprinitdone; |
438 | u32 lsfloadedfalconid; | 441 | u32 lsfloadedfalconid; |
439 | bool fecsbootstrapdone; | 442 | bool fecsbootstrapdone; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 6c0e0539..187c9c0e 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -7637,4 +7637,5 @@ void gk20a_init_gr_ops(struct gpu_ops *gops) | |||
7637 | gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; | 7637 | gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; |
7638 | gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; | 7638 | gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; |
7639 | gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; | 7639 | gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; |
7640 | gops->gr.get_lrf_tex_ltc_dram_override = NULL; | ||
7640 | } | 7641 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index f73706a2..30592ee2 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -2771,6 +2771,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops) | |||
2771 | gops->pmu.write_dmatrfbase = gk20a_write_dmatrfbase; | 2771 | gops->pmu.write_dmatrfbase = gk20a_write_dmatrfbase; |
2772 | gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; | 2772 | gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; |
2773 | gops->pmu.pmu_pg_grinit_param = NULL; | 2773 | gops->pmu.pmu_pg_grinit_param = NULL; |
2774 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | ||
2774 | } | 2775 | } |
2775 | 2776 | ||
2776 | int gk20a_init_pmu_support(struct gk20a *g) | 2777 | int gk20a_init_pmu_support(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index bf581b90..54d01947 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -50,7 +50,7 @@ | |||
50 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) | 50 | #define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) |
51 | 51 | ||
52 | #define APP_VERSION_NC_1 20313802 | 52 | #define APP_VERSION_NC_1 20313802 |
53 | #define APP_VERSION_NC_0 20120791 | 53 | #define APP_VERSION_NC_0 20360931 |
54 | #define APP_VERSION_GM20B_4 19008461 | 54 | #define APP_VERSION_GM20B_4 19008461 |
55 | #define APP_VERSION_GM20B_3 18935575 | 55 | #define APP_VERSION_GM20B_3 18935575 |
56 | #define APP_VERSION_GM20B_2 18694072 | 56 | #define APP_VERSION_GM20B_2 18694072 |
@@ -451,6 +451,8 @@ struct pmu_ucode_desc { | |||
451 | #define PMU_UNIT_PERFMON_T18X (0x11) | 451 | #define PMU_UNIT_PERFMON_T18X (0x11) |
452 | #define PMU_UNIT_PERFMON (0x12) | 452 | #define PMU_UNIT_PERFMON (0x12) |
453 | #define PMU_UNIT_RC (0x1F) | 453 | #define PMU_UNIT_RC (0x1F) |
454 | #define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E) | ||
455 | |||
454 | #define PMU_UNIT_END (0x23) | 456 | #define PMU_UNIT_END (0x23) |
455 | 457 | ||
456 | #define PMU_UNIT_TEST_START (0xFE) | 458 | #define PMU_UNIT_TEST_START (0xFE) |
@@ -814,6 +816,47 @@ struct pmu_acr_msg { | |||
814 | #define PMU_DOMAIN_GROUP_GPC2CLK 1 | 816 | #define PMU_DOMAIN_GROUP_GPC2CLK 1 |
815 | #define PMU_DOMAIN_GROUP_NUM 2 | 817 | #define PMU_DOMAIN_GROUP_NUM 2 |
816 | 818 | ||
819 | /* FECS mem override command*/ | ||
820 | |||
821 | #define PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS 0 | ||
822 | |||
823 | /*! | ||
824 | * Enable/Disable FECS error feature | ||
825 | */ | ||
826 | struct pmu_cmd_lrf_tex_ltc_dram_en_dis { | ||
827 | /*Command type must be first*/ | ||
828 | u8 cmd_type; | ||
829 | /*unit bitmask*/ | ||
830 | u8 en_dis_mask; | ||
831 | }; | ||
832 | |||
833 | struct pmu_lrf_tex_ltc_dram_cmd { | ||
834 | union { | ||
835 | u8 cmd_type; | ||
836 | struct pmu_cmd_lrf_tex_ltc_dram_en_dis en_dis; | ||
837 | }; | ||
838 | }; | ||
839 | |||
840 | /* FECS mem override messages*/ | ||
841 | #define PMU_LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS 0 | ||
842 | |||
843 | struct pmu_msg_lrf_tex_ltc_dram_en_dis { | ||
844 | /*! | ||
845 | * Must be at start | ||
846 | */ | ||
847 | u8 msg_type; | ||
848 | u8 en_fail_mask; | ||
849 | u8 dis_fail_mask; | ||
850 | u32 pmu_status; | ||
851 | }; | ||
852 | |||
853 | struct pmu_lrf_tex_ltc_dram_msg { | ||
854 | union { | ||
855 | u8 msg_type; | ||
856 | struct pmu_msg_lrf_tex_ltc_dram_en_dis en_dis; | ||
857 | }; | ||
858 | }; | ||
859 | |||
817 | /* TBD: smart strategy */ | 860 | /* TBD: smart strategy */ |
818 | #define PMU_PERFMON_PCT_TO_INC 58 | 861 | #define PMU_PERFMON_PCT_TO_INC 58 |
819 | #define PMU_PERFMON_PCT_TO_DEC 23 | 862 | #define PMU_PERFMON_PCT_TO_DEC 23 |
@@ -958,6 +1001,7 @@ struct pmu_cmd { | |||
958 | struct pmu_pg_cmd pg; | 1001 | struct pmu_pg_cmd pg; |
959 | struct pmu_zbc_cmd zbc; | 1002 | struct pmu_zbc_cmd zbc; |
960 | struct pmu_acr_cmd acr; | 1003 | struct pmu_acr_cmd acr; |
1004 | struct pmu_lrf_tex_ltc_dram_cmd lrf_tex_ltc_dram; | ||
961 | } cmd; | 1005 | } cmd; |
962 | }; | 1006 | }; |
963 | 1007 | ||
@@ -969,6 +1013,7 @@ struct pmu_msg { | |||
969 | struct pmu_pg_msg pg; | 1013 | struct pmu_pg_msg pg; |
970 | struct pmu_rc_msg rc; | 1014 | struct pmu_rc_msg rc; |
971 | struct pmu_acr_msg acr; | 1015 | struct pmu_acr_msg acr; |
1016 | struct pmu_lrf_tex_ltc_dram_msg lrf_tex_ltc_dram; | ||
972 | } msg; | 1017 | } msg; |
973 | }; | 1018 | }; |
974 | 1019 | ||
@@ -1318,6 +1363,7 @@ struct pmu_gk20a { | |||
1318 | u8 pmu_mode; /*Added for GM20b, and ACR*/ | 1363 | u8 pmu_mode; /*Added for GM20b, and ACR*/ |
1319 | u32 falcon_id; | 1364 | u32 falcon_id; |
1320 | u32 aelpg_param[5]; | 1365 | u32 aelpg_param[5]; |
1366 | u32 override_done; | ||
1321 | }; | 1367 | }; |
1322 | 1368 | ||
1323 | int gk20a_init_pmu_support(struct gk20a *g); | 1369 | int gk20a_init_pmu_support(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index ee64b90f..9f137246 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -1300,6 +1300,8 @@ static int gm20b_init_pmu_setup_hw1(struct gk20a *g, | |||
1300 | pmu_enable_irq(pmu, false); | 1300 | pmu_enable_irq(pmu, false); |
1301 | pmu->isr_enabled = false; | 1301 | pmu->isr_enabled = false; |
1302 | mutex_unlock(&pmu->isr_mutex); | 1302 | mutex_unlock(&pmu->isr_mutex); |
1303 | /*Clearing mailbox register used to reflect capabilities*/ | ||
1304 | gk20a_writel(g, pwr_falcon_mailbox1_r(), 0); | ||
1303 | err = bl_bootstrap(pmu, desc, bl_sz); | 1305 | err = bl_bootstrap(pmu, desc, bl_sz); |
1304 | if (err) | 1306 | if (err) |
1305 | return err; | 1307 | return err; |
@@ -1436,6 +1438,8 @@ int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout) | |||
1436 | if (completion) | 1438 | if (completion) |
1437 | gk20a_err(dev_from_gk20a(g), "ACR boot timed out"); | 1439 | gk20a_err(dev_from_gk20a(g), "ACR boot timed out"); |
1438 | else { | 1440 | else { |
1441 | g->acr.capabilities = gk20a_readl(g, pwr_falcon_mailbox1_r()); | ||
1442 | gm20b_dbg_pmu("ACR capabilities %x\n", g->acr.capabilities); | ||
1439 | data = gk20a_readl(g, pwr_falcon_mailbox0_r()); | 1443 | data = gk20a_readl(g, pwr_falcon_mailbox0_r()); |
1440 | if (data) { | 1444 | if (data) { |
1441 | gk20a_err(dev_from_gk20a(g), | 1445 | gk20a_err(dev_from_gk20a(g), |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index 58800c09..414e22b6 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B ACR | 2 | * GM20B ACR |
3 | * | 3 | * |
4 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -124,6 +124,10 @@ | |||
124 | #define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \ | 124 | #define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \ |
125 | (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2) | 125 | (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2) |
126 | 126 | ||
127 | enum acr_capabilities { | ||
128 | ACR_LRF_TEX_LTC_DRAM_PRIV_MASK_ENABLE_LS_OVERRIDE = (0x00000001), | ||
129 | }; | ||
130 | |||
127 | /*Externs*/ | 131 | /*Externs*/ |
128 | 132 | ||
129 | /*Structs*/ | 133 | /*Structs*/ |
@@ -397,6 +401,7 @@ struct acr_gm20b { | |||
397 | struct flcn_bl_dmem_desc bl_dmem_desc; | 401 | struct flcn_bl_dmem_desc bl_dmem_desc; |
398 | const struct firmware *pmu_fw; | 402 | const struct firmware *pmu_fw; |
399 | const struct firmware *pmu_desc; | 403 | const struct firmware *pmu_desc; |
404 | u32 capabilities; | ||
400 | }; | 405 | }; |
401 | 406 | ||
402 | void gm20b_init_secure_pmu(struct gpu_ops *gops); | 407 | void gm20b_init_secure_pmu(struct gpu_ops *gops); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 2a891647..67654cba 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1232,4 +1232,5 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1232 | gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; | 1232 | gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; |
1233 | gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; | 1233 | gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; |
1234 | gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; | 1234 | gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; |
1235 | gops->gr.get_lrf_tex_ltc_dram_override = NULL; | ||
1235 | } | 1236 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 4123e32a..ce3da2b6 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B PMU | 2 | * GM20B PMU |
3 | * | 3 | * |
4 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -308,4 +308,5 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops) | |||
308 | gops->pmu.write_dmatrfbase = gm20b_write_dmatrfbase; | 308 | gops->pmu.write_dmatrfbase = gm20b_write_dmatrfbase; |
309 | gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; | 309 | gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; |
310 | gops->pmu.pmu_pg_grinit_param = NULL; | 310 | gops->pmu.pmu_pg_grinit_param = NULL; |
311 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | ||
311 | } | 312 | } |