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-rw-r--r--drivers/gpu/nvgpu/gk20a/cde_gk20a.c3
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c15
-rw-r--r--drivers/gpu/nvgpu/gk20a/hw_gmmu_gk20a.h12
-rw-r--r--drivers/gpu/nvgpu/gk20a/mm_gk20a.c36
-rw-r--r--drivers/gpu/nvgpu/gk20a/mm_gk20a.h6
-rw-r--r--drivers/gpu/nvgpu/gk20a/semaphore_gk20a.c3
-rw-r--r--drivers/gpu/nvgpu/gm20b/acr_gm20b.c4
-rw-r--r--drivers/gpu/nvgpu/gm20b/hw_gmmu_gm20b.h12
-rw-r--r--drivers/gpu/nvgpu/vgpu/mm_vgpu.c1
10 files changed, 67 insertions, 26 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
index 7f212eca..d15b6e8a 100644
--- a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
@@ -1126,7 +1126,8 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
1126 vaddr = gk20a_gmmu_map(ch->vm, &gr->compbit_store.mem.sgt, 1126 vaddr = gk20a_gmmu_map(ch->vm, &gr->compbit_store.mem.sgt,
1127 g->gr.compbit_store.mem.size, 1127 g->gr.compbit_store.mem.size,
1128 NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, 1128 NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
1129 gk20a_mem_flag_read_only); 1129 gk20a_mem_flag_read_only,
1130 false);
1130 1131
1131 if (!vaddr) { 1132 if (!vaddr) {
1132 gk20a_warn(&cde_ctx->pdev->dev, "cde: cannot map compression bit backing store"); 1133 gk20a_warn(&cde_ctx->pdev->dev, "cde: cannot map compression bit backing store");
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 72f1178b..25712a64 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -350,6 +350,7 @@ struct gpu_ops {
350 int rw_flag, 350 int rw_flag,
351 bool clear_ctags, 351 bool clear_ctags,
352 bool sparse, 352 bool sparse,
353 bool priv,
353 struct vm_gk20a_mapping_batch *batch); 354 struct vm_gk20a_mapping_batch *batch);
354 void (*gmmu_unmap)(struct vm_gk20a *vm, 355 void (*gmmu_unmap)(struct vm_gk20a *vm,
355 u64 vaddr, 356 u64 vaddr,
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index e232bf17..cf9cab0e 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -1748,7 +1748,8 @@ static int gr_gk20a_init_ctxsw_ucode_vaspace(struct gk20a *g)
1748 &ucode_info->surface_desc.sgt, 1748 &ucode_info->surface_desc.sgt,
1749 ucode_info->surface_desc.size, 1749 ucode_info->surface_desc.size,
1750 0, /* flags */ 1750 0, /* flags */
1751 gk20a_mem_flag_read_only); 1751 gk20a_mem_flag_read_only,
1752 false);
1752 if (!ucode_info->surface_desc.gpu_va) { 1753 if (!ucode_info->surface_desc.gpu_va) {
1753 gk20a_err(d, "failed to update gmmu ptes\n"); 1754 gk20a_err(d, "failed to update gmmu ptes\n");
1754 return -ENOMEM; 1755 return -ENOMEM;
@@ -2375,7 +2376,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g,
2375 2376
2376 gpu_va = gk20a_gmmu_map(ch_vm, &sgt, size, 2377 gpu_va = gk20a_gmmu_map(ch_vm, &sgt, size,
2377 NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, 2378 NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
2378 gk20a_mem_flag_none); 2379 gk20a_mem_flag_none, true);
2379 if (!gpu_va) 2380 if (!gpu_va)
2380 goto clean_up; 2381 goto clean_up;
2381 g_bfr_va[CIRCULAR_VA] = gpu_va; 2382 g_bfr_va[CIRCULAR_VA] = gpu_va;
@@ -2392,7 +2393,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g,
2392 2393
2393 gpu_va = gk20a_gmmu_map(ch_vm, &sgt, size, 2394 gpu_va = gk20a_gmmu_map(ch_vm, &sgt, size,
2394 NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, 2395 NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
2395 gk20a_mem_flag_none); 2396 gk20a_mem_flag_none, false);
2396 if (!gpu_va) 2397 if (!gpu_va)
2397 goto clean_up; 2398 goto clean_up;
2398 g_bfr_va[ATTRIBUTE_VA] = gpu_va; 2399 g_bfr_va[ATTRIBUTE_VA] = gpu_va;
@@ -2409,7 +2410,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g,
2409 2410
2410 gpu_va = gk20a_gmmu_map(ch_vm, &sgt, size, 2411 gpu_va = gk20a_gmmu_map(ch_vm, &sgt, size,
2411 NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, 2412 NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
2412 gk20a_mem_flag_none); 2413 gk20a_mem_flag_none, true);
2413 if (!gpu_va) 2414 if (!gpu_va)
2414 goto clean_up; 2415 goto clean_up;
2415 g_bfr_va[PAGEPOOL_VA] = gpu_va; 2416 g_bfr_va[PAGEPOOL_VA] = gpu_va;
@@ -2419,7 +2420,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g,
2419 sgt = gr->global_ctx_buffer[GOLDEN_CTX].mem.sgt; 2420 sgt = gr->global_ctx_buffer[GOLDEN_CTX].mem.sgt;
2420 size = gr->global_ctx_buffer[GOLDEN_CTX].mem.size; 2421 size = gr->global_ctx_buffer[GOLDEN_CTX].mem.size;
2421 gpu_va = gk20a_gmmu_map(ch_vm, &sgt, size, 0, 2422 gpu_va = gk20a_gmmu_map(ch_vm, &sgt, size, 0,
2422 gk20a_mem_flag_none); 2423 gk20a_mem_flag_none, true);
2423 if (!gpu_va) 2424 if (!gpu_va)
2424 goto clean_up; 2425 goto clean_up;
2425 g_bfr_va[GOLDEN_CTX_VA] = gpu_va; 2426 g_bfr_va[GOLDEN_CTX_VA] = gpu_va;
@@ -2429,7 +2430,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g,
2429 sgt = gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.sgt; 2430 sgt = gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.sgt;
2430 size = gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size; 2431 size = gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size;
2431 gpu_va = gk20a_gmmu_map(ch_vm, &sgt, size, 0, 2432 gpu_va = gk20a_gmmu_map(ch_vm, &sgt, size, 0,
2432 gk20a_mem_flag_none); 2433 gk20a_mem_flag_none, true);
2433 if (!gpu_va) 2434 if (!gpu_va)
2434 goto clean_up; 2435 goto clean_up;
2435 g_bfr_va[PRIV_ACCESS_MAP_VA] = gpu_va; 2436 g_bfr_va[PRIV_ACCESS_MAP_VA] = gpu_va;
@@ -2501,7 +2502,7 @@ int gr_gk20a_alloc_gr_ctx(struct gk20a *g,
2501 2502
2502 gr_ctx->mem.gpu_va = gk20a_gmmu_map(vm, &gr_ctx->mem.sgt, gr_ctx->mem.size, 2503 gr_ctx->mem.gpu_va = gk20a_gmmu_map(vm, &gr_ctx->mem.sgt, gr_ctx->mem.size,
2503 NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, 2504 NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
2504 gk20a_mem_flag_none); 2505 gk20a_mem_flag_none, true);
2505 if (!gr_ctx->mem.gpu_va) 2506 if (!gr_ctx->mem.gpu_va)
2506 goto err_free_mem; 2507 goto err_free_mem;
2507 2508
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gmmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gmmu_gk20a.h
index 45ae59d6..19e44382 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_gmmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_gmmu_gk20a.h
@@ -146,6 +146,18 @@ static inline u32 gmmu_pte_valid_false_f(void)
146{ 146{
147 return 0x0; 147 return 0x0;
148} 148}
149static inline u32 gmmu_pte_privilege_w(void)
150{
151 return 0;
152}
153static inline u32 gmmu_pte_privilege_true_f(void)
154{
155 return 0x2;
156}
157static inline u32 gmmu_pte_privilege_false_f(void)
158{
159 return 0x0;
160}
149static inline u32 gmmu_pte_address_sys_f(u32 v) 161static inline u32 gmmu_pte_address_sys_f(u32 v)
150{ 162{
151 return (v & 0xfffffff) << 4; 163 return (v & 0xfffffff) << 4;
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index f3512f90..112e218a 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -101,7 +101,7 @@ static int update_gmmu_ptes_locked(struct vm_gk20a *vm,
101 u8 kind_v, u32 ctag_offset, bool cacheable, 101 u8 kind_v, u32 ctag_offset, bool cacheable,
102 bool umapped_pte, int rw_flag, 102 bool umapped_pte, int rw_flag,
103 bool sparse, 103 bool sparse,
104 u32 flags); 104 bool priv);
105static int __must_check gk20a_init_system_vm(struct mm_gk20a *mm); 105static int __must_check gk20a_init_system_vm(struct mm_gk20a *mm);
106static int __must_check gk20a_init_bar1_vm(struct mm_gk20a *mm); 106static int __must_check gk20a_init_bar1_vm(struct mm_gk20a *mm);
107static int __must_check gk20a_init_hwpm(struct mm_gk20a *mm); 107static int __must_check gk20a_init_hwpm(struct mm_gk20a *mm);
@@ -1168,6 +1168,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm,
1168 int rw_flag, 1168 int rw_flag,
1169 bool clear_ctags, 1169 bool clear_ctags,
1170 bool sparse, 1170 bool sparse,
1171 bool priv,
1171 struct vm_gk20a_mapping_batch *batch) 1172 struct vm_gk20a_mapping_batch *batch)
1172{ 1173{
1173 int err = 0; 1174 int err = 0;
@@ -1208,7 +1209,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm,
1208 NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE, 1209 NVGPU_AS_MAP_BUFFER_FLAGS_UNMAPPED_PTE,
1209 rw_flag, 1210 rw_flag,
1210 sparse, 1211 sparse,
1211 flags); 1212 priv);
1212 if (err) { 1213 if (err) {
1213 gk20a_err(d, "failed to update ptes on map"); 1214 gk20a_err(d, "failed to update ptes on map");
1214 goto fail_validate; 1215 goto fail_validate;
@@ -1559,6 +1560,7 @@ u64 gk20a_vm_map(struct vm_gk20a *vm,
1559 flags, rw_flag, 1560 flags, rw_flag,
1560 clear_ctags, 1561 clear_ctags,
1561 false, 1562 false,
1563 false,
1562 batch); 1564 batch);
1563 if (!map_offset) 1565 if (!map_offset)
1564 goto clean_up; 1566 goto clean_up;
@@ -1779,6 +1781,7 @@ int gk20a_vm_map_compbits(struct vm_gk20a *vm,
1779 gk20a_mem_flag_read_only, 1781 gk20a_mem_flag_read_only,
1780 false, /* clear_ctags */ 1782 false, /* clear_ctags */
1781 false, /* sparse */ 1783 false, /* sparse */
1784 false, /* priv */
1782 NULL); /* mapping_batch handle */ 1785 NULL); /* mapping_batch handle */
1783 1786
1784 if (!mapped_buffer->ctag_map_win_addr) { 1787 if (!mapped_buffer->ctag_map_win_addr) {
@@ -1802,7 +1805,8 @@ u64 gk20a_gmmu_map(struct vm_gk20a *vm,
1802 struct sg_table **sgt, 1805 struct sg_table **sgt,
1803 u64 size, 1806 u64 size,
1804 u32 flags, 1807 u32 flags,
1805 int rw_flag) 1808 int rw_flag,
1809 bool priv)
1806{ 1810{
1807 struct gk20a *g = gk20a_from_vm(vm); 1811 struct gk20a *g = gk20a_from_vm(vm);
1808 u64 vaddr; 1812 u64 vaddr;
@@ -1818,6 +1822,7 @@ u64 gk20a_gmmu_map(struct vm_gk20a *vm,
1818 flags, rw_flag, 1822 flags, rw_flag,
1819 false, /* clear_ctags */ 1823 false, /* clear_ctags */
1820 false, /* sparse */ 1824 false, /* sparse */
1825 priv, /* priv */
1821 NULL); /* mapping_batch handle */ 1826 NULL); /* mapping_batch handle */
1822 mutex_unlock(&vm->update_gmmu_lock); 1827 mutex_unlock(&vm->update_gmmu_lock);
1823 if (!vaddr) { 1828 if (!vaddr) {
@@ -1932,7 +1937,8 @@ int gk20a_gmmu_alloc_map_attr(struct vm_gk20a *vm,
1932 if (err) 1937 if (err)
1933 return err; 1938 return err;
1934 1939
1935 mem->gpu_va = gk20a_gmmu_map(vm, &mem->sgt, size, 0, gk20a_mem_flag_none); 1940 mem->gpu_va = gk20a_gmmu_map(vm, &mem->sgt, size, 0,
1941 gk20a_mem_flag_none, false);
1936 if (!mem->gpu_va) { 1942 if (!mem->gpu_va) {
1937 err = -ENOMEM; 1943 err = -ENOMEM;
1938 goto fail_free; 1944 goto fail_free;
@@ -2126,7 +2132,7 @@ static int update_gmmu_pde_locked(struct vm_gk20a *vm,
2126 u64 *iova, 2132 u64 *iova,
2127 u32 kind_v, u32 *ctag, 2133 u32 kind_v, u32 *ctag,
2128 bool cacheable, bool unammped_pte, 2134 bool cacheable, bool unammped_pte,
2129 int rw_flag, bool sparse, u32 flags) 2135 int rw_flag, bool sparse, bool priv)
2130{ 2136{
2131 struct gk20a *g = gk20a_from_vm(vm); 2137 struct gk20a *g = gk20a_from_vm(vm);
2132 bool small_valid, big_valid; 2138 bool small_valid, big_valid;
@@ -2176,7 +2182,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm,
2176 u64 *iova, 2182 u64 *iova,
2177 u32 kind_v, u32 *ctag, 2183 u32 kind_v, u32 *ctag,
2178 bool cacheable, bool unmapped_pte, 2184 bool cacheable, bool unmapped_pte,
2179 int rw_flag, bool sparse, u32 flags) 2185 int rw_flag, bool sparse, bool priv)
2180{ 2186{
2181 struct gk20a *g = gk20a_from_vm(vm); 2187 struct gk20a *g = gk20a_from_vm(vm);
2182 u32 ctag_granularity = g->ops.fb.compression_page_size(g); 2188 u32 ctag_granularity = g->ops.fb.compression_page_size(g);
@@ -2193,6 +2199,9 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm,
2193 gmmu_pte_address_sys_f(*iova 2199 gmmu_pte_address_sys_f(*iova
2194 >> gmmu_pte_address_shift_v()); 2200 >> gmmu_pte_address_shift_v());
2195 2201
2202 if (priv)
2203 pte_w[0] |= gmmu_pte_privilege_true_f();
2204
2196 pte_w[1] = gmmu_pte_aperture_video_memory_f() | 2205 pte_w[1] = gmmu_pte_aperture_video_memory_f() |
2197 gmmu_pte_kind_f(kind_v) | 2206 gmmu_pte_kind_f(kind_v) |
2198 gmmu_pte_comptagline_f(*ctag / ctag_granularity); 2207 gmmu_pte_comptagline_f(*ctag / ctag_granularity);
@@ -2270,7 +2279,7 @@ static int update_gmmu_level_locked(struct vm_gk20a *vm,
2270 int rw_flag, 2279 int rw_flag,
2271 bool sparse, 2280 bool sparse,
2272 int lvl, 2281 int lvl,
2273 u32 flags) 2282 bool priv)
2274{ 2283{
2275 const struct gk20a_mmu_level *l = &vm->mmu_levels[lvl]; 2284 const struct gk20a_mmu_level *l = &vm->mmu_levels[lvl];
2276 const struct gk20a_mmu_level *next_l = &vm->mmu_levels[lvl+1]; 2285 const struct gk20a_mmu_level *next_l = &vm->mmu_levels[lvl+1];
@@ -2318,7 +2327,7 @@ static int update_gmmu_level_locked(struct vm_gk20a *vm,
2318 err = l->update_entry(vm, pte, pde_i, pgsz_idx, 2327 err = l->update_entry(vm, pte, pde_i, pgsz_idx,
2319 sgl, offset, iova, 2328 sgl, offset, iova,
2320 kind_v, ctag, cacheable, unmapped_pte, 2329 kind_v, ctag, cacheable, unmapped_pte,
2321 rw_flag, sparse, flags); 2330 rw_flag, sparse, priv);
2322 if (err) 2331 if (err)
2323 return err; 2332 return err;
2324 2333
@@ -2339,7 +2348,7 @@ static int update_gmmu_level_locked(struct vm_gk20a *vm,
2339 gpu_va, 2348 gpu_va,
2340 next, 2349 next,
2341 kind_v, ctag, cacheable, unmapped_pte, 2350 kind_v, ctag, cacheable, unmapped_pte,
2342 rw_flag, sparse, lvl+1, flags); 2351 rw_flag, sparse, lvl+1, priv);
2343 unmap_gmmu_pages(next_pte); 2352 unmap_gmmu_pages(next_pte);
2344 2353
2345 if (err) 2354 if (err)
@@ -2364,7 +2373,7 @@ static int update_gmmu_ptes_locked(struct vm_gk20a *vm,
2364 bool cacheable, bool unmapped_pte, 2373 bool cacheable, bool unmapped_pte,
2365 int rw_flag, 2374 int rw_flag,
2366 bool sparse, 2375 bool sparse,
2367 u32 flags) 2376 bool priv)
2368{ 2377{
2369 struct gk20a *g = gk20a_from_vm(vm); 2378 struct gk20a *g = gk20a_from_vm(vm);
2370 int ctag_granularity = g->ops.fb.compression_page_size(g); 2379 int ctag_granularity = g->ops.fb.compression_page_size(g);
@@ -2377,7 +2386,7 @@ static int update_gmmu_ptes_locked(struct vm_gk20a *vm,
2377 2386
2378 gk20a_dbg(gpu_dbg_pte, "size_idx=%d, iova=%llx, buffer offset %lld, nents %d", 2387 gk20a_dbg(gpu_dbg_pte, "size_idx=%d, iova=%llx, buffer offset %lld, nents %d",
2379 pgsz_idx, 2388 pgsz_idx,
2380 sgt ? g->ops.mm.get_iova_addr(vm->mm->g, sgt->sgl, flags) 2389 sgt ? g->ops.mm.get_iova_addr(vm->mm->g, sgt->sgl, 0)
2381 : 0ULL, 2390 : 0ULL,
2382 buffer_offset, 2391 buffer_offset,
2383 sgt ? sgt->nents : 0); 2392 sgt ? sgt->nents : 0);
@@ -2386,7 +2395,7 @@ static int update_gmmu_ptes_locked(struct vm_gk20a *vm,
2386 return -EINVAL; 2395 return -EINVAL;
2387 2396
2388 if (sgt) { 2397 if (sgt) {
2389 iova = g->ops.mm.get_iova_addr(vm->mm->g, sgt->sgl, flags); 2398 iova = g->ops.mm.get_iova_addr(vm->mm->g, sgt->sgl, 0);
2390 if (!vm->mm->bypass_smmu && iova) { 2399 if (!vm->mm->bypass_smmu && iova) {
2391 iova += space_to_skip; 2400 iova += space_to_skip;
2392 } else { 2401 } else {
@@ -2422,7 +2431,7 @@ static int update_gmmu_ptes_locked(struct vm_gk20a *vm,
2422 &iova, 2431 &iova,
2423 gpu_va, gpu_end, 2432 gpu_va, gpu_end,
2424 kind_v, &ctag, 2433 kind_v, &ctag,
2425 cacheable, unmapped_pte, rw_flag, sparse, 0, flags); 2434 cacheable, unmapped_pte, rw_flag, sparse, 0, priv);
2426 unmap_gmmu_pages(&vm->pdb); 2435 unmap_gmmu_pages(&vm->pdb);
2427 2436
2428 smp_mb(); 2437 smp_mb();
@@ -2835,6 +2844,7 @@ int gk20a_vm_alloc_space(struct gk20a_as_share *as_share,
2835 gk20a_mem_flag_none, 2844 gk20a_mem_flag_none,
2836 false, 2845 false,
2837 true, 2846 true,
2847 false,
2838 NULL); 2848 NULL);
2839 if (!map_offset) { 2849 if (!map_offset) {
2840 mutex_unlock(&vm->update_gmmu_lock); 2850 mutex_unlock(&vm->update_gmmu_lock);
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
index ee99c821..3af35b26 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
@@ -221,7 +221,7 @@ struct gk20a_mmu_level {
221 u64 *iova, 221 u64 *iova,
222 u32 kind_v, u32 *ctag, 222 u32 kind_v, u32 *ctag,
223 bool cacheable, bool unmapped_pte, 223 bool cacheable, bool unmapped_pte,
224 int rw_flag, bool sparse, u32 flags); 224 int rw_flag, bool sparse, bool priv);
225 size_t entry_size; 225 size_t entry_size;
226}; 226};
227 227
@@ -441,7 +441,8 @@ u64 gk20a_gmmu_map(struct vm_gk20a *vm,
441 struct sg_table **sgt, 441 struct sg_table **sgt,
442 u64 size, 442 u64 size,
443 u32 flags, 443 u32 flags,
444 int rw_flag); 444 int rw_flag,
445 bool priv);
445 446
446int gk20a_gmmu_alloc_map(struct vm_gk20a *vm, 447int gk20a_gmmu_alloc_map(struct vm_gk20a *vm,
447 size_t size, 448 size_t size,
@@ -498,6 +499,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm,
498 int rw_flag, 499 int rw_flag,
499 bool clear_ctags, 500 bool clear_ctags,
500 bool sparse, 501 bool sparse,
502 bool priv,
501 struct vm_gk20a_mapping_batch *batch); 503 struct vm_gk20a_mapping_batch *batch);
502 504
503void gk20a_gmmu_unmap(struct vm_gk20a *vm, 505void gk20a_gmmu_unmap(struct vm_gk20a *vm,
diff --git a/drivers/gpu/nvgpu/gk20a/semaphore_gk20a.c b/drivers/gpu/nvgpu/gk20a/semaphore_gk20a.c
index 053550f6..cf855463 100644
--- a/drivers/gpu/nvgpu/gk20a/semaphore_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/semaphore_gk20a.c
@@ -111,7 +111,8 @@ int gk20a_semaphore_pool_map(struct gk20a_semaphore_pool *p,
111 map->vm = vm; 111 map->vm = vm;
112 map->rw_flag = rw_flag; 112 map->rw_flag = rw_flag;
113 map->gpu_va = gk20a_gmmu_map(vm, &p->sgt, p->size, 113 map->gpu_va = gk20a_gmmu_map(vm, &p->sgt, p->size,
114 0/*uncached*/, rw_flag); 114 0/*uncached*/, rw_flag,
115 false);
115 if (!map->gpu_va) { 116 if (!map->gpu_va) {
116 kfree(map); 117 kfree(map);
117 return -ENOMEM; 118 return -ENOMEM;
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index a238c523..3a19d6b6 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -333,7 +333,7 @@ int prepare_ucode_blob(struct gk20a *g)
333 sg_dma_address(sgt->sgl) = 0; 333 sg_dma_address(sgt->sgl) = 0;
334 334
335 g->pmu.wpr_buf.gpu_va = gk20a_gmmu_map(vm, &sgt, wprsize, 335 g->pmu.wpr_buf.gpu_va = gk20a_gmmu_map(vm, &sgt, wprsize,
336 0, gk20a_mem_flag_none); 336 0, gk20a_mem_flag_none, false);
337 gm20b_dbg_pmu("wpr mapped gpu va :%llx\n", g->pmu.wpr_buf.gpu_va); 337 gm20b_dbg_pmu("wpr mapped gpu va :%llx\n", g->pmu.wpr_buf.gpu_va);
338 338
339 /* Discover all managed falcons*/ 339 /* Discover all managed falcons*/
@@ -1323,7 +1323,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt)
1323 acr->hsbl_ucode.gpu_va = gk20a_gmmu_map(vm, &acr->hsbl_ucode.sgt, 1323 acr->hsbl_ucode.gpu_va = gk20a_gmmu_map(vm, &acr->hsbl_ucode.sgt,
1324 bl_sz, 1324 bl_sz,
1325 0, /* flags */ 1325 0, /* flags */
1326 gk20a_mem_flag_read_only); 1326 gk20a_mem_flag_read_only, false);
1327 if (!acr->hsbl_ucode.gpu_va) { 1327 if (!acr->hsbl_ucode.gpu_va) {
1328 gk20a_err(d, "failed to map pmu ucode memory!!"); 1328 gk20a_err(d, "failed to map pmu ucode memory!!");
1329 goto err_free_ucode; 1329 goto err_free_ucode;
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gmmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gmmu_gm20b.h
index 9a1c0e71..32b65912 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_gmmu_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_gmmu_gm20b.h
@@ -146,6 +146,18 @@ static inline u32 gmmu_pte_valid_false_f(void)
146{ 146{
147 return 0x0; 147 return 0x0;
148} 148}
149static inline u32 gmmu_pte_privilege_w(void)
150{
151 return 0;
152}
153static inline u32 gmmu_pte_privilege_true_f(void)
154{
155 return 0x2;
156}
157static inline u32 gmmu_pte_privilege_false_f(void)
158{
159 return 0x0;
160}
149static inline u32 gmmu_pte_address_sys_f(u32 v) 161static inline u32 gmmu_pte_address_sys_f(u32 v)
150{ 162{
151 return (v & 0xfffffff) << 4; 163 return (v & 0xfffffff) << 4;
diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
index be1fa47d..640111b5 100644
--- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
@@ -67,6 +67,7 @@ static u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm,
67 int rw_flag, 67 int rw_flag,
68 bool clear_ctags, 68 bool clear_ctags,
69 bool sparse, 69 bool sparse,
70 bool priv,
70 struct vm_gk20a_mapping_batch *batch) 71 struct vm_gk20a_mapping_batch *batch)
71{ 72{
72 int err = 0; 73 int err = 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 15:16:55 -0400