diff options
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/mc_carveout_reg.h | 22 |
2 files changed, 8 insertions, 35 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 387f01ab..1e07f139 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -20,11 +20,12 @@ | |||
20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
21 | #include "../../../../arch/arm/mach-tegra/iomap.h" | 21 | #include "../../../../arch/arm/mach-tegra/iomap.h" |
22 | 22 | ||
23 | #include <linux/platform/tegra/mc.h> | ||
24 | |||
23 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
24 | #include "gk20a/pmu_gk20a.h" | 26 | #include "gk20a/pmu_gk20a.h" |
25 | #include "gk20a/semaphore_gk20a.h" | 27 | #include "gk20a/semaphore_gk20a.h" |
26 | #include "hw_pwr_gm20b.h" | 28 | #include "hw_pwr_gm20b.h" |
27 | #include "mc_carveout_reg.h" | ||
28 | 29 | ||
29 | /*Defines*/ | 30 | /*Defines*/ |
30 | #define gm20b_dbg_pmu(fmt, arg...) \ | 31 | #define gm20b_dbg_pmu(fmt, arg...) \ |
@@ -53,7 +54,6 @@ static int acr_ucode_patch_sig(struct gk20a *g, | |||
53 | static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr *plsfm); | 54 | static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr *plsfm); |
54 | 55 | ||
55 | /*Globals*/ | 56 | /*Globals*/ |
56 | static void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE); | ||
57 | static get_ucode_details pmu_acr_supp_ucode_list[] = { | 57 | static get_ucode_details pmu_acr_supp_ucode_list[] = { |
58 | pmu_ucode_details, | 58 | pmu_ucode_details, |
59 | fecs_ucode_details, | 59 | fecs_ucode_details, |
@@ -255,10 +255,6 @@ int prepare_ucode_blob(struct gk20a *g) | |||
255 | g->acr.ucode_blob_start = g->ops.mm.get_iova_addr(g, | 255 | g->acr.ucode_blob_start = g->ops.mm.get_iova_addr(g, |
256 | plsfm->mem.sgt->sgl, 0); | 256 | plsfm->mem.sgt->sgl, 0); |
257 | g->acr.ucode_blob_size = plsfm->wpr_size; | 257 | g->acr.ucode_blob_size = plsfm->wpr_size; |
258 | gm20b_dbg_pmu("base reg carveout 2:%x\n", | ||
259 | readl(mc + MC_SECURITY_CARVEOUT2_BOM_0)); | ||
260 | gm20b_dbg_pmu("base reg carveout 3:%x\n", | ||
261 | readl(mc + MC_SECURITY_CARVEOUT3_BOM_0)); | ||
262 | } else { | 258 | } else { |
263 | gm20b_dbg_pmu("LSFM is managing no falcons.\n"); | 259 | gm20b_dbg_pmu("LSFM is managing no falcons.\n"); |
264 | } | 260 | } |
@@ -363,6 +359,7 @@ static int pmu_populate_loader_cfg(struct gk20a *g, | |||
363 | struct lsfm_managed_ucode_img *lsfm, | 359 | struct lsfm_managed_ucode_img *lsfm, |
364 | union flcn_bl_generic_desc *p_bl_gen_desc, u32 *p_bl_gen_desc_size) | 360 | union flcn_bl_generic_desc *p_bl_gen_desc, u32 *p_bl_gen_desc_size) |
365 | { | 361 | { |
362 | struct mc_carveout_info inf; | ||
366 | struct pmu_gk20a *pmu = &g->pmu; | 363 | struct pmu_gk20a *pmu = &g->pmu; |
367 | struct flcn_ucode_img *p_img = &(lsfm->ucode_img); | 364 | struct flcn_ucode_img *p_img = &(lsfm->ucode_img); |
368 | struct loader_config *ldr_cfg = | 365 | struct loader_config *ldr_cfg = |
@@ -385,7 +382,8 @@ static int pmu_populate_loader_cfg(struct gk20a *g, | |||
385 | physical addresses of each respective segment. | 382 | physical addresses of each respective segment. |
386 | */ | 383 | */ |
387 | addr_base = lsfm->lsb_header.ucode_off; | 384 | addr_base = lsfm->lsb_header.ucode_off; |
388 | addr_base += readl(mc + MC_SECURITY_CARVEOUT2_BOM_0); | 385 | mc_get_carveout_info(&inf, NULL, MC_SECURITY_CARVEOUT2); |
386 | addr_base += inf.base; | ||
389 | gm20b_dbg_pmu("pmu loader cfg u32 addrbase %x\n", (u32)addr_base); | 387 | gm20b_dbg_pmu("pmu loader cfg u32 addrbase %x\n", (u32)addr_base); |
390 | /*From linux*/ | 388 | /*From linux*/ |
391 | addr_code = u64_lo32((addr_base + | 389 | addr_code = u64_lo32((addr_base + |
@@ -430,7 +428,7 @@ static int flcn_populate_bl_dmem_desc(struct gk20a *g, | |||
430 | struct lsfm_managed_ucode_img *lsfm, | 428 | struct lsfm_managed_ucode_img *lsfm, |
431 | union flcn_bl_generic_desc *p_bl_gen_desc, u32 *p_bl_gen_desc_size) | 429 | union flcn_bl_generic_desc *p_bl_gen_desc, u32 *p_bl_gen_desc_size) |
432 | { | 430 | { |
433 | 431 | struct mc_carveout_info inf; | |
434 | struct flcn_ucode_img *p_img = &(lsfm->ucode_img); | 432 | struct flcn_ucode_img *p_img = &(lsfm->ucode_img); |
435 | struct flcn_bl_dmem_desc *ldr_cfg = | 433 | struct flcn_bl_dmem_desc *ldr_cfg = |
436 | (struct flcn_bl_dmem_desc *)(&p_bl_gen_desc->bl_dmem_desc); | 434 | (struct flcn_bl_dmem_desc *)(&p_bl_gen_desc->bl_dmem_desc); |
@@ -452,7 +450,8 @@ static int flcn_populate_bl_dmem_desc(struct gk20a *g, | |||
452 | physical addresses of each respective segment. | 450 | physical addresses of each respective segment. |
453 | */ | 451 | */ |
454 | addr_base = lsfm->lsb_header.ucode_off; | 452 | addr_base = lsfm->lsb_header.ucode_off; |
455 | addr_base += readl(mc + MC_SECURITY_CARVEOUT2_BOM_0); | 453 | mc_get_carveout_info(&inf, NULL, MC_SECURITY_CARVEOUT2); |
454 | addr_base += inf.base; | ||
456 | gm20b_dbg_pmu("gen loader cfg %x u32 addrbase %x ID\n", (u32)addr_base, | 455 | gm20b_dbg_pmu("gen loader cfg %x u32 addrbase %x ID\n", (u32)addr_base, |
457 | lsfm->wpr_header.falcon_id); | 456 | lsfm->wpr_header.falcon_id); |
458 | addr_code = u64_lo32((addr_base + | 457 | addr_code = u64_lo32((addr_base + |
@@ -1214,8 +1213,6 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1214 | if (clear_halt_interrupt_status(g, gk20a_get_gr_idle_timeout(g))) | 1213 | if (clear_halt_interrupt_status(g, gk20a_get_gr_idle_timeout(g))) |
1215 | goto err_unmap_bl; | 1214 | goto err_unmap_bl; |
1216 | 1215 | ||
1217 | gm20b_dbg_pmu("err reg :%x\n", readl(mc + | ||
1218 | MC_ERR_GENERALIZED_CARVEOUT_STATUS_0)); | ||
1219 | gm20b_dbg_pmu("phys sec reg %x\n", gk20a_readl(g, | 1216 | gm20b_dbg_pmu("phys sec reg %x\n", gk20a_readl(g, |
1220 | pwr_falcon_mmu_phys_sec_r())); | 1217 | pwr_falcon_mmu_phys_sec_r())); |
1221 | gm20b_dbg_pmu("sctl reg %x\n", gk20a_readl(g, pwr_falcon_sctl_r())); | 1218 | gm20b_dbg_pmu("sctl reg %x\n", gk20a_readl(g, pwr_falcon_sctl_r())); |
@@ -1233,8 +1230,6 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1233 | goto err_unmap_bl; | 1230 | goto err_unmap_bl; |
1234 | } | 1231 | } |
1235 | gm20b_dbg_pmu("after waiting for halt, err %x\n", err); | 1232 | gm20b_dbg_pmu("after waiting for halt, err %x\n", err); |
1236 | gm20b_dbg_pmu("err reg :%x\n", readl(mc + | ||
1237 | MC_ERR_GENERALIZED_CARVEOUT_STATUS_0)); | ||
1238 | gm20b_dbg_pmu("phys sec reg %x\n", gk20a_readl(g, | 1233 | gm20b_dbg_pmu("phys sec reg %x\n", gk20a_readl(g, |
1239 | pwr_falcon_mmu_phys_sec_r())); | 1234 | pwr_falcon_mmu_phys_sec_r())); |
1240 | gm20b_dbg_pmu("sctl reg %x\n", gk20a_readl(g, pwr_falcon_sctl_r())); | 1235 | gm20b_dbg_pmu("sctl reg %x\n", gk20a_readl(g, pwr_falcon_sctl_r())); |
diff --git a/drivers/gpu/nvgpu/gm20b/mc_carveout_reg.h b/drivers/gpu/nvgpu/gm20b/mc_carveout_reg.h deleted file mode 100644 index a9273a62..00000000 --- a/drivers/gpu/nvgpu/gm20b/mc_carveout_reg.h +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | /* | ||
2 | * GM20B MC registers used by ACR | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _MC_CARVEOUT_REG_H_ | ||
17 | #define _MC_CARVEOUT_REG_H_ | ||
18 | |||
19 | #define MC_SECURITY_CARVEOUT2_BOM_0 0xc5c | ||
20 | #define MC_SECURITY_CARVEOUT3_BOM_0 0xcac | ||
21 | #define MC_ERR_GENERALIZED_CARVEOUT_STATUS_0 0xc00 | ||
22 | #endif /*_MC_CARVEOUT_REG_H_*/ | ||