diff options
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/mm_gm20b.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/regops_gm20b.h | 6 |
9 files changed, 32 insertions, 32 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index e22da730..7c9743ab 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B ACR | 2 | * GM20B ACR |
3 | * | 3 | * |
4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -22,8 +22,8 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifndef __ACR_GM20B_H_ | 25 | #ifndef NVGPU_GM20B_ACR_GM20B_H |
26 | #define __ACR_GM20B_H_ | 26 | #define NVGPU_GM20B_ACR_GM20B_H |
27 | 27 | ||
28 | #define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin" | 28 | #define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin" |
29 | #define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin" | 29 | #define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin" |
@@ -59,4 +59,4 @@ int acr_ucode_patch_sig(struct gk20a *g, | |||
59 | unsigned int *p_dbg_sig, | 59 | unsigned int *p_dbg_sig, |
60 | unsigned int *p_patch_loc, | 60 | unsigned int *p_patch_loc, |
61 | unsigned int *p_patch_ind); | 61 | unsigned int *p_patch_ind); |
62 | #endif /*__ACR_GM20B_H_*/ | 62 | #endif /*NVGPU_GM20B_ACR_GM20B_H*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h index 09b1bdcc..d67b280b 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Graphics | 2 | * GM20B Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -21,8 +21,8 @@ | |||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | #ifndef _NVHOST_CLK_GM20B_H_ | 24 | #ifndef NVGPU_GM20B_CLK_GM20B_H |
25 | #define _NVHOST_CLK_GM20B_H_ | 25 | #define NVGPU_GM20B_CLK_GM20B_H |
26 | 26 | ||
27 | #include <nvgpu/lock.h> | 27 | #include <nvgpu/lock.h> |
28 | 28 | ||
@@ -90,4 +90,4 @@ static inline u32 nvgpu_div_to_pl(u32 div) | |||
90 | return div; | 90 | return div; |
91 | } | 91 | } |
92 | 92 | ||
93 | #endif /* _NVHOST_CLK_GM20B_H_ */ | 93 | #endif /* NVGPU_GM20B_CLK_GM20B_H */ |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h index f9e1f95d..b9e20721 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h | |||
@@ -22,8 +22,8 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifndef _NVHOST_GM20B_FIFO | 25 | #ifndef NVGPU_GM20B_FIFO_GM20B_H |
26 | #define _NVHOST_GM20B_FIFO | 26 | #define NVGPU_GM20B_FIFO_GM20B_H |
27 | struct gk20a; | 27 | struct gk20a; |
28 | struct mmu_fault_info; | 28 | struct mmu_fault_info; |
29 | 29 | ||
@@ -38,4 +38,4 @@ void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); | |||
38 | void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch); | 38 | void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch); |
39 | void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault); | 39 | void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault); |
40 | 40 | ||
41 | #endif | 41 | #endif /* NVGPU_GM20B_FIFO_GM20B_H */ |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h index 8712b353..d33a2591 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Graphics Context | 2 | * GM20B Graphics Context |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -21,8 +21,8 @@ | |||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | #ifndef __GR_CTX_GM20B_H__ | 24 | #ifndef NVGPU_GM20B_GR_CTX_GM20B_H |
25 | #define __GR_CTX_GM20B_H__ | 25 | #define NVGPU_GM20B_GR_CTX_GM20B_H |
26 | 26 | ||
27 | #include "gk20a/gr_ctx_gk20a.h" | 27 | #include "gk20a/gr_ctx_gk20a.h" |
28 | 28 | ||
@@ -33,4 +33,4 @@ | |||
33 | int gr_gm20b_get_netlist_name(struct gk20a *g, int index, char *name); | 33 | int gr_gm20b_get_netlist_name(struct gk20a *g, int index, char *name); |
34 | bool gr_gm20b_is_firmware_defined(void); | 34 | bool gr_gm20b_is_firmware_defined(void); |
35 | 35 | ||
36 | #endif /*__GR_CTX_GM20B_H__*/ | 36 | #endif /*NVGPU_GM20B_GR_CTX_GM20B_H*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index 0f5dfe53..0a486c2e 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -22,8 +22,8 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifndef _NVHOST_GM20B_GR_MMU_H | 25 | #ifndef NVGPU_GM20B_GR_GM20B_H |
26 | #define _NVHOST_GM20B_GR_MMU_H | 26 | #define NVGPU_GM20B_GR_GM20B_H |
27 | 27 | ||
28 | struct gk20a; | 28 | struct gk20a; |
29 | struct nvgpu_warpstate; | 29 | struct nvgpu_warpstate; |
@@ -128,4 +128,4 @@ void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | |||
128 | u32 global_esr); | 128 | u32 global_esr); |
129 | u32 gr_gm20b_get_pmm_per_chiplet_offset(void); | 129 | u32 gr_gm20b_get_pmm_per_chiplet_offset(void); |
130 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable); | 130 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable); |
131 | #endif | 131 | #endif /* NVGPU_GM20B_GR_GM20B_H */ |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.h b/drivers/gpu/nvgpu/gm20b/hal_gm20b.h index 22eae182..5deb7ef5 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Graphics | 2 | * GM20B Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -22,10 +22,10 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifndef _NVHOST_HAL_GM20B_H | 25 | #ifndef NVGPU_GM20B_HAL_GM20B_H |
26 | #define _NVHOST_HAL_GM20B_H | 26 | #define NVGPU_GM20B_HAL_GM20B_H |
27 | struct gk20a; | 27 | struct gk20a; |
28 | 28 | ||
29 | int gm20b_init_hal(struct gk20a *g); | 29 | int gm20b_init_hal(struct gk20a *g); |
30 | int gm20b_get_litter_value(struct gk20a *g, int value); | 30 | int gm20b_get_litter_value(struct gk20a *g, int value); |
31 | #endif | 31 | #endif /* NVGPU_GM20B_HAL_GM20B_H */ |
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h index 369fa1eb..be10be38 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h | |||
@@ -20,8 +20,8 @@ | |||
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | 22 | ||
23 | #ifndef _NVHOST_GM20B_MM | 23 | #ifndef NVGPU_GM20B_MM_GM20B_H |
24 | #define _NVHOST_GM20B_MM | 24 | #define NVGPU_GM20B_MM_GM20B_H |
25 | struct gk20a; | 25 | struct gk20a; |
26 | 26 | ||
27 | #define PDE_ADDR_START(x, y) ((x) & ~((0x1UL << (y)) - 1)) | 27 | #define PDE_ADDR_START(x, y) ((x) & ~((0x1UL << (y)) - 1)) |
@@ -37,4 +37,4 @@ u64 gm20b_gpu_phys_addr(struct gk20a *g, | |||
37 | struct nvgpu_gmmu_attrs *attrs, u64 phys); | 37 | struct nvgpu_gmmu_attrs *attrs, u64 phys); |
38 | u32 gm20b_get_kind_invalid(void); | 38 | u32 gm20b_get_kind_invalid(void); |
39 | u32 gm20b_get_kind_pitch(void); | 39 | u32 gm20b_get_kind_pitch(void); |
40 | #endif | 40 | #endif /* NVGPU_GM20B_MM_GM20B_H */ |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h index 1923c047..f1b6cd93 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B PMU | 2 | * GM20B PMU |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -22,8 +22,8 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifndef __PMU_GM20B_H_ | 25 | #ifndef NVGPU_GM20B_PMU_GM20B_H |
26 | #define __PMU_GM20B_H_ | 26 | #define NVGPU_GM20B_PMU_GM20B_H |
27 | 27 | ||
28 | struct gk20a; | 28 | struct gk20a; |
29 | 29 | ||
@@ -35,4 +35,4 @@ int gm20b_pmu_init_acr(struct gk20a *g); | |||
35 | void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr); | 35 | void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr); |
36 | bool gm20b_pmu_is_debug_mode_en(struct gk20a *g); | 36 | bool gm20b_pmu_is_debug_mode_en(struct gk20a *g); |
37 | 37 | ||
38 | #endif /*__PMU_GM20B_H_*/ | 38 | #endif /*NVGPU_GM20B_PMU_GM20B_H*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h index 99044f09..11a35f89 100644 --- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h | |||
@@ -22,8 +22,8 @@ | |||
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
23 | * DEALINGS IN THE SOFTWARE. | 23 | * DEALINGS IN THE SOFTWARE. |
24 | */ | 24 | */ |
25 | #ifndef __REGOPS_GM20B_H_ | 25 | #ifndef NVGPU_GM20B_REGOPS_GM20B_H |
26 | #define __REGOPS_GM20B_H_ | 26 | #define NVGPU_GM20B_REGOPS_GM20B_H |
27 | 27 | ||
28 | struct dbg_session_gk20a; | 28 | struct dbg_session_gk20a; |
29 | 29 | ||
@@ -41,4 +41,4 @@ const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void); | |||
41 | u64 gm20b_get_qctl_whitelist_ranges_count(void); | 41 | u64 gm20b_get_qctl_whitelist_ranges_count(void); |
42 | int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); | 42 | int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); |
43 | 43 | ||
44 | #endif /* __REGOPS_GM20B_H_ */ | 44 | #endif /* NVGPU_GM20B_REGOPS_GM20B_H */ |