diff options
-rw-r--r-- | drivers/gpu/nvgpu/common/falcon/falcon.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | 177 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h | 36 |
6 files changed, 319 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index 4c879e52..c9ab69fe 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c | |||
@@ -210,6 +210,17 @@ int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector) | |||
210 | return status; | 210 | return status; |
211 | } | 211 | } |
212 | 212 | ||
213 | void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn) | ||
214 | { | ||
215 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; | ||
216 | |||
217 | if (flcn_ops->dump_falcon_stats) | ||
218 | flcn_ops->dump_falcon_stats(flcn); | ||
219 | else | ||
220 | nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", | ||
221 | flcn->flcn_id); | ||
222 | } | ||
223 | |||
213 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id) | 224 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id) |
214 | { | 225 | { |
215 | struct nvgpu_falcon *flcn = NULL; | 226 | struct nvgpu_falcon *flcn = NULL; |
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c index a21342c5..8a3c90d8 100644 --- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | |||
@@ -15,7 +15,7 @@ | |||
15 | 15 | ||
16 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
17 | 17 | ||
18 | #include <nvgpu/hw/gk20a/hw_falcon_gk20a.h> | 18 | #include <nvgpu/hw/gm20b/hw_falcon_gm20b.h> |
19 | 19 | ||
20 | static int gk20a_flcn_reset(struct nvgpu_falcon *flcn) | 20 | static int gk20a_flcn_reset(struct nvgpu_falcon *flcn) |
21 | { | 21 | { |
@@ -344,6 +344,180 @@ static int gk20a_falcon_bootstrap(struct nvgpu_falcon *flcn, | |||
344 | return 0; | 344 | return 0; |
345 | } | 345 | } |
346 | 346 | ||
347 | static void gk20a_falcon_dump_imblk(struct nvgpu_falcon *flcn) | ||
348 | { | ||
349 | struct gk20a *g = flcn->g; | ||
350 | u32 base_addr = flcn->flcn_base; | ||
351 | u32 i = 0, j = 0; | ||
352 | u32 data[8] = {0}; | ||
353 | u32 block_count = 0; | ||
354 | |||
355 | block_count = falcon_falcon_hwcfg_imem_size_v(gk20a_readl(g, | ||
356 | flcn->flcn_base + falcon_falcon_hwcfg_r())); | ||
357 | |||
358 | /* block_count must be multiple of 8 */ | ||
359 | block_count &= ~0x7; | ||
360 | nvgpu_err(g, "FALCON IMEM BLK MAPPING (PA->VA) (%d TOTAL):", | ||
361 | block_count); | ||
362 | |||
363 | for (i = 0; i < block_count; i += 8) { | ||
364 | for (j = 0; j < 8; j++) { | ||
365 | gk20a_writel(g, flcn->flcn_base + | ||
366 | falcon_falcon_imctl_debug_r(), | ||
367 | falcon_falcon_imctl_debug_cmd_f(0x2) | | ||
368 | falcon_falcon_imctl_debug_addr_blk_f(i + j)); | ||
369 | |||
370 | data[j] = gk20a_readl(g, base_addr + | ||
371 | falcon_falcon_imstat_r()); | ||
372 | } | ||
373 | |||
374 | nvgpu_err(g, " %#04x: %#010x %#010x %#010x %#010x", | ||
375 | i, data[0], data[1], data[2], data[3]); | ||
376 | nvgpu_err(g, " %#04x: %#010x %#010x %#010x %#010x", | ||
377 | i + 4, data[4], data[5], data[6], data[7]); | ||
378 | } | ||
379 | } | ||
380 | |||
381 | static void gk20a_falcon_dump_pc_trace(struct nvgpu_falcon *flcn) | ||
382 | { | ||
383 | struct gk20a *g = flcn->g; | ||
384 | u32 base_addr = flcn->flcn_base; | ||
385 | u32 trace_pc_count = 0; | ||
386 | u32 pc = 0; | ||
387 | u32 i = 0; | ||
388 | |||
389 | if (gk20a_readl(g, base_addr + falcon_falcon_sctl_r()) & 0x02) { | ||
390 | nvgpu_err(g, " falcon is in HS mode, PC TRACE dump not supported"); | ||
391 | return; | ||
392 | } | ||
393 | |||
394 | trace_pc_count = falcon_falcon_traceidx_maxidx_v(gk20a_readl(g, | ||
395 | base_addr + falcon_falcon_traceidx_r())); | ||
396 | nvgpu_err(g, | ||
397 | "PC TRACE (TOTAL %d ENTRIES. entry 0 is the most recent branch):", | ||
398 | trace_pc_count); | ||
399 | |||
400 | for (i = 0; i < trace_pc_count; i++) { | ||
401 | gk20a_writel(g, base_addr + falcon_falcon_traceidx_r(), | ||
402 | falcon_falcon_traceidx_idx_f(i)); | ||
403 | |||
404 | pc = falcon_falcon_tracepc_pc_v(gk20a_readl(g, | ||
405 | base_addr + falcon_falcon_tracepc_r())); | ||
406 | nvgpu_err(g, "FALCON_TRACEPC(%d) : %#010x", i, pc); | ||
407 | } | ||
408 | } | ||
409 | |||
410 | void gk20a_falcon_dump_stats(struct nvgpu_falcon *flcn) | ||
411 | { | ||
412 | struct gk20a *g = flcn->g; | ||
413 | u32 base_addr = flcn->flcn_base; | ||
414 | unsigned int i; | ||
415 | |||
416 | nvgpu_err(g, "<<< FALCON id-%d DEBUG INFORMATION - START >>>", | ||
417 | flcn->flcn_id); | ||
418 | |||
419 | /* imblk dump */ | ||
420 | gk20a_falcon_dump_imblk(flcn); | ||
421 | /* PC trace dump */ | ||
422 | gk20a_falcon_dump_pc_trace(flcn); | ||
423 | |||
424 | nvgpu_err(g, "FALCON ICD REGISTERS DUMP"); | ||
425 | |||
426 | for (i = 0; i < 4; i++) { | ||
427 | gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(), | ||
428 | falcon_falcon_icd_cmd_opc_rreg_f() | | ||
429 | falcon_falcon_icd_cmd_idx_f(FALCON_REG_PC)); | ||
430 | nvgpu_err(g, "FALCON_REG_PC : 0x%x", | ||
431 | gk20a_readl(g, base_addr + | ||
432 | falcon_falcon_icd_rdata_r())); | ||
433 | |||
434 | gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(), | ||
435 | falcon_falcon_icd_cmd_opc_rreg_f() | | ||
436 | falcon_falcon_icd_cmd_idx_f(FALCON_REG_SP)); | ||
437 | nvgpu_err(g, "FALCON_REG_SP : 0x%x", | ||
438 | gk20a_readl(g, base_addr + | ||
439 | falcon_falcon_icd_rdata_r())); | ||
440 | } | ||
441 | |||
442 | gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(), | ||
443 | falcon_falcon_icd_cmd_opc_rreg_f() | | ||
444 | falcon_falcon_icd_cmd_idx_f(FALCON_REG_IMB)); | ||
445 | nvgpu_err(g, "FALCON_REG_IMB : 0x%x", | ||
446 | gk20a_readl(g, base_addr + falcon_falcon_icd_rdata_r())); | ||
447 | |||
448 | gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(), | ||
449 | falcon_falcon_icd_cmd_opc_rreg_f() | | ||
450 | falcon_falcon_icd_cmd_idx_f(FALCON_REG_DMB)); | ||
451 | nvgpu_err(g, "FALCON_REG_DMB : 0x%x", | ||
452 | gk20a_readl(g, base_addr + falcon_falcon_icd_rdata_r())); | ||
453 | |||
454 | gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(), | ||
455 | falcon_falcon_icd_cmd_opc_rreg_f() | | ||
456 | falcon_falcon_icd_cmd_idx_f(FALCON_REG_CSW)); | ||
457 | nvgpu_err(g, "FALCON_REG_CSW : 0x%x", | ||
458 | gk20a_readl(g, base_addr + falcon_falcon_icd_rdata_r())); | ||
459 | |||
460 | gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(), | ||
461 | falcon_falcon_icd_cmd_opc_rreg_f() | | ||
462 | falcon_falcon_icd_cmd_idx_f(FALCON_REG_CTX)); | ||
463 | nvgpu_err(g, "FALCON_REG_CTX : 0x%x", | ||
464 | gk20a_readl(g, base_addr + falcon_falcon_icd_rdata_r())); | ||
465 | |||
466 | gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(), | ||
467 | falcon_falcon_icd_cmd_opc_rreg_f() | | ||
468 | falcon_falcon_icd_cmd_idx_f(FALCON_REG_EXCI)); | ||
469 | nvgpu_err(g, "FALCON_REG_EXCI : 0x%x", | ||
470 | gk20a_readl(g, base_addr + falcon_falcon_icd_rdata_r())); | ||
471 | |||
472 | for (i = 0; i < 6; i++) { | ||
473 | gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(), | ||
474 | falcon_falcon_icd_cmd_opc_rreg_f() | | ||
475 | falcon_falcon_icd_cmd_idx_f( | ||
476 | falcon_falcon_icd_cmd_opc_rstat_f())); | ||
477 | nvgpu_err(g, "FALCON_REG_RSTAT[%d] : 0x%x", i, | ||
478 | gk20a_readl(g, base_addr + | ||
479 | falcon_falcon_icd_rdata_r())); | ||
480 | } | ||
481 | |||
482 | nvgpu_err(g, " FALCON REGISTERS DUMP"); | ||
483 | nvgpu_err(g, "falcon_falcon_os_r : %d", | ||
484 | gk20a_readl(g, base_addr + falcon_falcon_os_r())); | ||
485 | nvgpu_err(g, "falcon_falcon_cpuctl_r : 0x%x", | ||
486 | gk20a_readl(g, base_addr + falcon_falcon_cpuctl_r())); | ||
487 | nvgpu_err(g, "falcon_falcon_idlestate_r : 0x%x", | ||
488 | gk20a_readl(g, base_addr + falcon_falcon_idlestate_r())); | ||
489 | nvgpu_err(g, "falcon_falcon_mailbox0_r : 0x%x", | ||
490 | gk20a_readl(g, base_addr + falcon_falcon_mailbox0_r())); | ||
491 | nvgpu_err(g, "falcon_falcon_mailbox1_r : 0x%x", | ||
492 | gk20a_readl(g, base_addr + falcon_falcon_mailbox1_r())); | ||
493 | nvgpu_err(g, "falcon_falcon_irqstat_r : 0x%x", | ||
494 | gk20a_readl(g, base_addr + falcon_falcon_irqstat_r())); | ||
495 | nvgpu_err(g, "falcon_falcon_irqmode_r : 0x%x", | ||
496 | gk20a_readl(g, base_addr + falcon_falcon_irqmode_r())); | ||
497 | nvgpu_err(g, "falcon_falcon_irqmask_r : 0x%x", | ||
498 | gk20a_readl(g, base_addr + falcon_falcon_irqmask_r())); | ||
499 | nvgpu_err(g, "falcon_falcon_irqdest_r : 0x%x", | ||
500 | gk20a_readl(g, base_addr + falcon_falcon_irqdest_r())); | ||
501 | nvgpu_err(g, "falcon_falcon_debug1_r : 0x%x", | ||
502 | gk20a_readl(g, base_addr + falcon_falcon_debug1_r())); | ||
503 | nvgpu_err(g, "falcon_falcon_debuginfo_r : 0x%x", | ||
504 | gk20a_readl(g, base_addr + falcon_falcon_debuginfo_r())); | ||
505 | nvgpu_err(g, "falcon_falcon_bootvec_r : 0x%x", | ||
506 | gk20a_readl(g, base_addr + falcon_falcon_bootvec_r())); | ||
507 | nvgpu_err(g, "falcon_falcon_hwcfg_r : 0x%x", | ||
508 | gk20a_readl(g, base_addr + falcon_falcon_hwcfg_r())); | ||
509 | nvgpu_err(g, "falcon_falcon_engctl_r : 0x%x", | ||
510 | gk20a_readl(g, base_addr + falcon_falcon_engctl_r())); | ||
511 | nvgpu_err(g, "falcon_falcon_curctx_r : 0x%x", | ||
512 | gk20a_readl(g, base_addr + falcon_falcon_curctx_r())); | ||
513 | nvgpu_err(g, "falcon_falcon_nxtctx_r : 0x%x", | ||
514 | gk20a_readl(g, base_addr + falcon_falcon_nxtctx_r())); | ||
515 | nvgpu_err(g, "falcon_falcon_exterrstat_r : 0x%x", | ||
516 | gk20a_readl(g, base_addr + falcon_falcon_exterrstat_r())); | ||
517 | nvgpu_err(g, "falcon_falcon_exterraddr_r : 0x%x", | ||
518 | gk20a_readl(g, base_addr + falcon_falcon_exterraddr_r())); | ||
519 | } | ||
520 | |||
347 | static void gk20a_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) | 521 | static void gk20a_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) |
348 | { | 522 | { |
349 | struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops = | 523 | struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops = |
@@ -378,6 +552,7 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn) | |||
378 | flcn_ops->copy_to_dmem = gk20a_flcn_copy_to_dmem; | 552 | flcn_ops->copy_to_dmem = gk20a_flcn_copy_to_dmem; |
379 | flcn_ops->copy_to_imem = gk20a_flcn_copy_to_imem; | 553 | flcn_ops->copy_to_imem = gk20a_flcn_copy_to_imem; |
380 | flcn_ops->bootstrap = gk20a_falcon_bootstrap; | 554 | flcn_ops->bootstrap = gk20a_falcon_bootstrap; |
555 | flcn_ops->dump_falcon_stats = gk20a_falcon_dump_stats; | ||
381 | 556 | ||
382 | gk20a_falcon_engine_dependency_ops(flcn); | 557 | gk20a_falcon_engine_dependency_ops(flcn); |
383 | } | 558 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h index 8acc61ec..a948bf58 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h | |||
@@ -412,6 +412,30 @@ static inline u32 falcon_falcon_dmatrffboffs_r(void) | |||
412 | { | 412 | { |
413 | return 0x0000011c; | 413 | return 0x0000011c; |
414 | } | 414 | } |
415 | static inline u32 falcon_falcon_imstat_r(void) | ||
416 | { | ||
417 | return 0x00000144; | ||
418 | } | ||
419 | static inline u32 falcon_falcon_traceidx_r(void) | ||
420 | { | ||
421 | return 0x00000148; | ||
422 | } | ||
423 | static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) | ||
424 | { | ||
425 | return (r >> 16) & 0xff; | ||
426 | } | ||
427 | static inline u32 falcon_falcon_traceidx_idx_v(u32 r) | ||
428 | { | ||
429 | return (r >> 0) & 0xff; | ||
430 | } | ||
431 | static inline u32 falcon_falcon_tracepc_r(void) | ||
432 | { | ||
433 | return 0x0000014c; | ||
434 | } | ||
435 | static inline u32 falcon_falcon_tracepc_pc_v(u32 r) | ||
436 | { | ||
437 | return (r >> 0) & 0xffffff; | ||
438 | } | ||
415 | static inline u32 falcon_falcon_exterraddr_r(void) | 439 | static inline u32 falcon_falcon_exterraddr_r(void) |
416 | { | 440 | { |
417 | return 0x00000168; | 441 | return 0x00000168; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h index 6be11429..851fb62a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h | |||
@@ -440,6 +440,42 @@ static inline u32 falcon_falcon_dmatrffboffs_r(void) | |||
440 | { | 440 | { |
441 | return 0x0000011c; | 441 | return 0x0000011c; |
442 | } | 442 | } |
443 | static inline u32 falcon_falcon_imctl_debug_r(void) | ||
444 | { | ||
445 | return 0x0000015c; | ||
446 | } | ||
447 | static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) | ||
448 | { | ||
449 | return (v & 0xffffff) << 0; | ||
450 | } | ||
451 | static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) | ||
452 | { | ||
453 | return (v & 0x7) << 24; | ||
454 | } | ||
455 | static inline u32 falcon_falcon_imstat_r(void) | ||
456 | { | ||
457 | return 0x00000144; | ||
458 | } | ||
459 | static inline u32 falcon_falcon_traceidx_r(void) | ||
460 | { | ||
461 | return 0x00000148; | ||
462 | } | ||
463 | static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) | ||
464 | { | ||
465 | return (r >> 16) & 0xff; | ||
466 | } | ||
467 | static inline u32 falcon_falcon_traceidx_idx_f(u32 v) | ||
468 | { | ||
469 | return (v & 0xff) << 0; | ||
470 | } | ||
471 | static inline u32 falcon_falcon_tracepc_r(void) | ||
472 | { | ||
473 | return 0x0000014c; | ||
474 | } | ||
475 | static inline u32 falcon_falcon_tracepc_pc_v(u32 r) | ||
476 | { | ||
477 | return (r >> 0) & 0xffffff; | ||
478 | } | ||
443 | static inline u32 falcon_falcon_exterraddr_r(void) | 479 | static inline u32 falcon_falcon_exterraddr_r(void) |
444 | { | 480 | { |
445 | return 0x00000168; | 481 | return 0x00000168; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h index c744bcec..4f99f2cb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h | |||
@@ -444,6 +444,42 @@ static inline u32 falcon_falcon_dmatrffboffs_r(void) | |||
444 | { | 444 | { |
445 | return 0x0000011c; | 445 | return 0x0000011c; |
446 | } | 446 | } |
447 | static inline u32 falcon_falcon_imctl_debug_r(void) | ||
448 | { | ||
449 | return 0x0000015c; | ||
450 | } | ||
451 | static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) | ||
452 | { | ||
453 | return (v & 0xffffff) << 0; | ||
454 | } | ||
455 | static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) | ||
456 | { | ||
457 | return (v & 0x7) << 24; | ||
458 | } | ||
459 | static inline u32 falcon_falcon_imstat_r(void) | ||
460 | { | ||
461 | return 0x00000144; | ||
462 | } | ||
463 | static inline u32 falcon_falcon_traceidx_r(void) | ||
464 | { | ||
465 | return 0x00000148; | ||
466 | } | ||
467 | static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) | ||
468 | { | ||
469 | return (r >> 16) & 0xff; | ||
470 | } | ||
471 | static inline u32 falcon_falcon_traceidx_idx_f(u32 v) | ||
472 | { | ||
473 | return (v & 0xff) << 0; | ||
474 | } | ||
475 | static inline u32 falcon_falcon_tracepc_r(void) | ||
476 | { | ||
477 | return 0x0000014c; | ||
478 | } | ||
479 | static inline u32 falcon_falcon_tracepc_pc_v(u32 r) | ||
480 | { | ||
481 | return (r >> 0) & 0xffffff; | ||
482 | } | ||
447 | static inline u32 falcon_falcon_exterraddr_r(void) | 483 | static inline u32 falcon_falcon_exterraddr_r(void) |
448 | { | 484 | { |
449 | return 0x00000168; | 485 | return 0x00000168; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h index 7f9d0b5d..67b7ad75 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h | |||
@@ -420,6 +420,42 @@ static inline u32 falcon_falcon_dmatrfmoffs_r(void) | |||
420 | { | 420 | { |
421 | return 0x00000114; | 421 | return 0x00000114; |
422 | } | 422 | } |
423 | static inline u32 falcon_falcon_imctl_debug_r(void) | ||
424 | { | ||
425 | return 0x0000015c; | ||
426 | } | ||
427 | static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) | ||
428 | { | ||
429 | return (v & 0xffffff) << 0; | ||
430 | } | ||
431 | static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) | ||
432 | { | ||
433 | return (v & 0x7) << 24; | ||
434 | } | ||
435 | static inline u32 falcon_falcon_imstat_r(void) | ||
436 | { | ||
437 | return 0x00000144; | ||
438 | } | ||
439 | static inline u32 falcon_falcon_traceidx_r(void) | ||
440 | { | ||
441 | return 0x00000148; | ||
442 | } | ||
443 | static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) | ||
444 | { | ||
445 | return (r >> 16) & 0xff; | ||
446 | } | ||
447 | static inline u32 falcon_falcon_traceidx_idx_f(u32 v) | ||
448 | { | ||
449 | return (v & 0xff) << 0; | ||
450 | } | ||
451 | static inline u32 falcon_falcon_tracepc_r(void) | ||
452 | { | ||
453 | return 0x0000014c; | ||
454 | } | ||
455 | static inline u32 falcon_falcon_tracepc_pc_v(u32 r) | ||
456 | { | ||
457 | return (r >> 0) & 0xffffff; | ||
458 | } | ||
423 | static inline u32 falcon_falcon_dmatrfcmd_r(void) | 459 | static inline u32 falcon_falcon_dmatrfcmd_r(void) |
424 | { | 460 | { |
425 | return 0x00000118; | 461 | return 0x00000118; |