diff options
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 32 |
3 files changed, 65 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 542ed1ff..7993e071 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -1069,6 +1069,31 @@ static void gr_gv11b_set_coalesce_buffer_size(struct gk20a *g, u32 data) | |||
1069 | gk20a_dbg_fn("done"); | 1069 | gk20a_dbg_fn("done"); |
1070 | } | 1070 | } |
1071 | 1071 | ||
1072 | static void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data) | ||
1073 | { | ||
1074 | u32 val; | ||
1075 | bool flag; | ||
1076 | |||
1077 | gk20a_dbg_fn(""); | ||
1078 | |||
1079 | val = gk20a_readl(g, gr_gpcs_tpcs_tex_in_dbg_r()); | ||
1080 | flag = (data & NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE) ? 1 : 0; | ||
1081 | val = set_field(val, gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(), | ||
1082 | gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(flag)); | ||
1083 | gk20a_writel(g, gr_gpcs_tpcs_tex_in_dbg_r(), val); | ||
1084 | |||
1085 | val = gk20a_readl(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r()); | ||
1086 | flag = (data & | ||
1087 | NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD) ? 1 : 0; | ||
1088 | val = set_field(val, gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(), | ||
1089 | gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(flag)); | ||
1090 | flag = (data & | ||
1091 | NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST) ? 1 : 0; | ||
1092 | val = set_field(val, gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(), | ||
1093 | gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(flag)); | ||
1094 | gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val); | ||
1095 | } | ||
1096 | |||
1072 | 1097 | ||
1073 | static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) | 1098 | static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) |
1074 | { | 1099 | { |
@@ -1120,6 +1145,9 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, | |||
1120 | case NVC097_SET_COALESCE_BUFFER_SIZE: | 1145 | case NVC097_SET_COALESCE_BUFFER_SIZE: |
1121 | gr_gv11b_set_coalesce_buffer_size(g, data); | 1146 | gr_gv11b_set_coalesce_buffer_size(g, data); |
1122 | break; | 1147 | break; |
1148 | case NVC397_SET_TEX_IN_DBG: | ||
1149 | gr_gv11b_set_tex_in_dbg(g, data); | ||
1150 | break; | ||
1123 | default: | 1151 | default: |
1124 | goto fail; | 1152 | goto fail; |
1125 | } | 1153 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 9283a597..ff5782d9 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -39,6 +39,11 @@ enum { | |||
39 | #define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 | 39 | #define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 |
40 | #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc | 40 | #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc |
41 | #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c | 41 | #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c |
42 | #define NVC397_SET_TEX_IN_DBG 0x10bc | ||
43 | |||
44 | #define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1 | ||
45 | #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2 | ||
46 | #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST 0x4 | ||
42 | 47 | ||
43 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 | 48 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 |
44 | 49 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 29a8b33c..75a64be5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -3830,6 +3830,38 @@ static inline u32 gr_zcull_subregion_qty_v(void) | |||
3830 | { | 3830 | { |
3831 | return 0x00000010; | 3831 | return 0x00000010; |
3832 | } | 3832 | } |
3833 | static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) | ||
3834 | { | ||
3835 | return 0x00419a00; | ||
3836 | } | ||
3837 | static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) | ||
3838 | { | ||
3839 | return (v & 0x1) << 19; | ||
3840 | } | ||
3841 | static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) | ||
3842 | { | ||
3843 | return 0x1 << 19; | ||
3844 | } | ||
3845 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) | ||
3846 | { | ||
3847 | return 0x00419bf0; | ||
3848 | } | ||
3849 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) | ||
3850 | { | ||
3851 | return (v & 0x1) << 5; | ||
3852 | } | ||
3853 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) | ||
3854 | { | ||
3855 | return 0x1 << 5; | ||
3856 | } | ||
3857 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) | ||
3858 | { | ||
3859 | return (v & 0x1) << 10; | ||
3860 | } | ||
3861 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) | ||
3862 | { | ||
3863 | return 0x1 << 10; | ||
3864 | } | ||
3833 | static inline u32 gr_fe_pwr_mode_r(void) | 3865 | static inline u32 gr_fe_pwr_mode_r(void) |
3834 | { | 3866 | { |
3835 | return 0x00404170; | 3867 | return 0x00404170; |