1 files changed, 20 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 28812792..033d83d5 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -1683,15 +1683,29 @@ void gr_gv11b_commit_global_attrib_cb(struct gk20a *g,
 
 void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 {
+        u32 tpc_count_mask;
+        u32 fuse_val;
+
+        if (!g->gr.gpc_tpc_mask[gpc_index])
+                return;
+
+        /*
+         * For s/w value g->gr.gpc_tpc_mask[gpc_index], bit value 1 indicates
+         * corresponding TPC is enabled. But for h/w fuse register, bit value 1
+         * indicates corresponding TPC is disabled.
+         * So we need to flip the bits and ensure we don't write to bits greater
+         * than TPC count
+         */
+        tpc_count_mask = (1 << gr_gk20a_get_tpc_count(&g->gr, gpc_index)) - 1;
+
+        fuse_val = g->gr.gpc_tpc_mask[gpc_index];
+        fuse_val = ~fuse_val;
+        fuse_val = fuse_val & tpc_count_mask;
+
         nvgpu_tegra_fuse_write_bypass(g, 0x1);
         nvgpu_tegra_fuse_write_access_sw(g, 0x0);
 
-        if (g->gr.gpc_tpc_mask[gpc_index] == 0x1)
-                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x2);
-        else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2)
-                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1);
-        else
-                nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0);
+        nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, fuse_val);
 }
 
 void gr_gv11b_get_access_map(struct gk20a *g,