diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 1 |
6 files changed, 0 insertions, 38 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 61d2dd84..7dc72f7b 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -750,8 +750,6 @@ struct gpu_ops { | |||
750 | int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock); | 750 | int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock); |
751 | int (*pmu_lpwr_disable_pg)(struct gk20a *g, bool pstate_lock); | 751 | int (*pmu_lpwr_disable_pg)(struct gk20a *g, bool pstate_lock); |
752 | u32 (*pmu_pg_param_post_init)(struct gk20a *g); | 752 | u32 (*pmu_pg_param_post_init)(struct gk20a *g); |
753 | int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd) | ||
754 | (struct gk20a *g, u32 mask); | ||
755 | void (*dump_secure_fuses)(struct gk20a *g); | 753 | void (*dump_secure_fuses)(struct gk20a *g); |
756 | int (*reset)(struct gk20a *g); | 754 | int (*reset)(struct gk20a *g); |
757 | int (*falcon_wait_for_halt)(struct gk20a *g, | 755 | int (*falcon_wait_for_halt)(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index fefa77fc..7fe25190 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -739,7 +739,6 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops) | |||
739 | gops->pmu.pmu_lpwr_enable_pg = NULL; | 739 | gops->pmu.pmu_lpwr_enable_pg = NULL; |
740 | gops->pmu.pmu_lpwr_disable_pg = NULL; | 740 | gops->pmu.pmu_lpwr_disable_pg = NULL; |
741 | gops->pmu.pmu_pg_param_post_init = NULL; | 741 | gops->pmu.pmu_pg_param_post_init = NULL; |
742 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | ||
743 | gops->pmu.dump_secure_fuses = NULL; | 742 | gops->pmu.dump_secure_fuses = NULL; |
744 | gops->pmu.is_lazy_bootstrap = NULL; | 743 | gops->pmu.is_lazy_bootstrap = NULL; |
745 | gops->pmu.is_priv_load = NULL; | 744 | gops->pmu.is_priv_load = NULL; |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index b486acfd..6c5a2502 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -308,7 +308,6 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops) | |||
308 | gops->pmu.pmu_lpwr_enable_pg = NULL; | 308 | gops->pmu.pmu_lpwr_enable_pg = NULL; |
309 | gops->pmu.pmu_lpwr_disable_pg = NULL; | 309 | gops->pmu.pmu_lpwr_disable_pg = NULL; |
310 | gops->pmu.pmu_pg_param_post_init = NULL; | 310 | gops->pmu.pmu_pg_param_post_init = NULL; |
311 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | ||
312 | gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gm20b; | 311 | gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gm20b; |
313 | gops->pmu.reset = NULL; | 312 | gops->pmu.reset = NULL; |
314 | } | 313 | } |
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index 7662f4eb..9b169c38 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c | |||
@@ -438,7 +438,6 @@ void gp106_init_pmu_ops(struct gpu_ops *gops) | |||
438 | gops->pmu.pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg; | 438 | gops->pmu.pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg; |
439 | gops->pmu.pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg; | 439 | gops->pmu.pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg; |
440 | gops->pmu.pmu_pg_param_post_init = nvgpu_lpwr_post_init; | 440 | gops->pmu.pmu_pg_param_post_init = nvgpu_lpwr_post_init; |
441 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | ||
442 | gops->pmu.dump_secure_fuses = NULL; | 441 | gops->pmu.dump_secure_fuses = NULL; |
443 | gops->pmu.reset = gp106_falcon_reset; | 442 | gops->pmu.reset = gp106_falcon_reset; |
444 | gops->pmu.mclk_init = gp106_mclk_init; | 443 | gops->pmu.mclk_init = gp106_mclk_init; |
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c index 5a242bb5..1c90d2f9 100644 --- a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c +++ b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c | |||
@@ -23,36 +23,6 @@ | |||
23 | 23 | ||
24 | #define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH) | 24 | #define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH) |
25 | 25 | ||
26 | static ssize_t ecc_enable_store(struct device *dev, | ||
27 | struct device_attribute *attr, const char *buf, size_t count) | ||
28 | { | ||
29 | struct gk20a *g = get_gk20a(dev); | ||
30 | u32 ecc_mask; | ||
31 | u32 err = 0; | ||
32 | |||
33 | err = sscanf(buf, "%d", &ecc_mask); | ||
34 | if (err == 1) { | ||
35 | err = g->ops.pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd | ||
36 | (g, ecc_mask); | ||
37 | if (err) | ||
38 | nvgpu_err(g, "ECC override did not happen"); | ||
39 | } else | ||
40 | return -EINVAL; | ||
41 | return count; | ||
42 | } | ||
43 | |||
44 | static ssize_t ecc_enable_read(struct device *dev, | ||
45 | struct device_attribute *attr, char *buf) | ||
46 | { | ||
47 | struct gk20a *g = get_gk20a(dev); | ||
48 | |||
49 | return sprintf(buf, "ecc override =0x%x\n", | ||
50 | g->ops.gr.get_lrf_tex_ltc_dram_override(g)); | ||
51 | } | ||
52 | |||
53 | static DEVICE_ATTR(ecc_enable, ROOTRW, ecc_enable_read, ecc_enable_store); | ||
54 | |||
55 | |||
56 | static ssize_t czf_bypass_store(struct device *dev, | 26 | static ssize_t czf_bypass_store(struct device *dev, |
57 | struct device_attribute *attr, const char *buf, size_t count) | 27 | struct device_attribute *attr, const char *buf, size_t count) |
58 | { | 28 | { |
@@ -87,7 +57,6 @@ void gp10b_create_sysfs(struct device *dev) | |||
87 | 57 | ||
88 | g->gr.czf_bypass = gr_gpc0_prop_debug1_czf_bypass_init_v(); | 58 | g->gr.czf_bypass = gr_gpc0_prop_debug1_czf_bypass_init_v(); |
89 | 59 | ||
90 | error |= device_create_file(dev, &dev_attr_ecc_enable); | ||
91 | error |= device_create_file(dev, &dev_attr_czf_bypass); | 60 | error |= device_create_file(dev, &dev_attr_czf_bypass); |
92 | if (error) | 61 | if (error) |
93 | nvgpu_err(g, "Failed to create sysfs attributes!"); | 62 | nvgpu_err(g, "Failed to create sysfs attributes!"); |
@@ -95,6 +64,5 @@ void gp10b_create_sysfs(struct device *dev) | |||
95 | 64 | ||
96 | void gp10b_remove_sysfs(struct device *dev) | 65 | void gp10b_remove_sysfs(struct device *dev) |
97 | { | 66 | { |
98 | device_remove_file(dev, &dev_attr_ecc_enable); | ||
99 | device_remove_file(dev, &dev_attr_czf_bypass); | 67 | device_remove_file(dev, &dev_attr_czf_bypass); |
100 | } | 68 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index c3ad8978..58844e8f 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -429,7 +429,6 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) | |||
429 | gops->pmu.pmu_lpwr_enable_pg = NULL; | 429 | gops->pmu.pmu_lpwr_enable_pg = NULL; |
430 | gops->pmu.pmu_lpwr_disable_pg = NULL; | 430 | gops->pmu.pmu_lpwr_disable_pg = NULL; |
431 | gops->pmu.pmu_pg_param_post_init = NULL; | 431 | gops->pmu.pmu_pg_param_post_init = NULL; |
432 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | ||
433 | gops->pmu.reset = NULL; | 432 | gops->pmu.reset = NULL; |
434 | gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gp10b; | 433 | gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gp10b; |
435 | } | 434 | } |