diff options
-rw-r--r-- | drivers/gpu/nvgpu/common/semaphore.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/common/semaphore.c b/drivers/gpu/nvgpu/common/semaphore.c index e1e6c027..dfed3588 100644 --- a/drivers/gpu/nvgpu/common/semaphore.c +++ b/drivers/gpu/nvgpu/common/semaphore.c | |||
@@ -59,6 +59,7 @@ static int __nvgpu_semaphore_sea_grow(struct nvgpu_semaphore_sea *sea) | |||
59 | { | 59 | { |
60 | int ret = 0; | 60 | int ret = 0; |
61 | struct gk20a *gk20a = sea->gk20a; | 61 | struct gk20a *gk20a = sea->gk20a; |
62 | u32 i; | ||
62 | 63 | ||
63 | __lock_sema_sea(sea); | 64 | __lock_sema_sea(sea); |
64 | 65 | ||
@@ -71,6 +72,14 @@ static int __nvgpu_semaphore_sea_grow(struct nvgpu_semaphore_sea *sea) | |||
71 | sea->size = SEMAPHORE_POOL_COUNT; | 72 | sea->size = SEMAPHORE_POOL_COUNT; |
72 | sea->map_size = SEMAPHORE_POOL_COUNT * PAGE_SIZE; | 73 | sea->map_size = SEMAPHORE_POOL_COUNT * PAGE_SIZE; |
73 | 74 | ||
75 | /* | ||
76 | * Start the semaphores at values that will soon overflow the 32-bit | ||
77 | * integer range. This way any buggy comparisons would start to fail | ||
78 | * sooner rather than later. | ||
79 | */ | ||
80 | for (i = 0; i < PAGE_SIZE * SEMAPHORE_POOL_COUNT; i += 4) | ||
81 | nvgpu_mem_wr(gk20a, &sea->sea_mem, i, 0xfffffff0); | ||
82 | |||
74 | out: | 83 | out: |
75 | __unlock_sema_sea(sea); | 84 | __unlock_sema_sea(sea); |
76 | return ret; | 85 | return ret; |
@@ -345,6 +354,7 @@ static int __nvgpu_init_hw_sema(struct channel_gk20a *ch) | |||
345 | int ret = 0; | 354 | int ret = 0; |
346 | struct nvgpu_semaphore_int *hw_sema; | 355 | struct nvgpu_semaphore_int *hw_sema; |
347 | struct nvgpu_semaphore_pool *p = ch->vm->sema_pool; | 356 | struct nvgpu_semaphore_pool *p = ch->vm->sema_pool; |
357 | int current_value; | ||
348 | 358 | ||
349 | BUG_ON(!p); | 359 | BUG_ON(!p); |
350 | 360 | ||
@@ -369,8 +379,8 @@ static int __nvgpu_init_hw_sema(struct channel_gk20a *ch) | |||
369 | hw_sema->p = p; | 379 | hw_sema->p = p; |
370 | hw_sema->idx = hw_sema_idx; | 380 | hw_sema->idx = hw_sema_idx; |
371 | hw_sema->offset = SEMAPHORE_SIZE * hw_sema_idx; | 381 | hw_sema->offset = SEMAPHORE_SIZE * hw_sema_idx; |
372 | nvgpu_atomic_set(&hw_sema->next_value, 0); | 382 | current_value = nvgpu_mem_rd(ch->g, &p->rw_mem, hw_sema->offset); |
373 | nvgpu_mem_wr(ch->g, &p->rw_mem, hw_sema->offset, 0); | 383 | nvgpu_atomic_set(&hw_sema->next_value, current_value); |
374 | 384 | ||
375 | nvgpu_mutex_release(&p->pool_lock); | 385 | nvgpu_mutex_release(&p->pool_lock); |
376 | 386 | ||