diff options
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ce2_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 20 |
2 files changed, 17 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c index b2d417b7..4cb13f3b 100644 --- a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c | |||
@@ -26,7 +26,7 @@ static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) | |||
26 | gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); | 26 | gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); |
27 | 27 | ||
28 | /* wake theads waiting in this channel */ | 28 | /* wake theads waiting in this channel */ |
29 | gk20a_channel_semaphore_wakeup(g); | 29 | gk20a_channel_semaphore_wakeup(g, true); |
30 | return ce2_intr_status_nonblockpipe_pending_f(); | 30 | return ce2_intr_status_nonblockpipe_pending_f(); |
31 | } | 31 | } |
32 | 32 | ||
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index f2308ab5..1aba35f3 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1491,6 +1491,16 @@ static int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, struct channel_gk2 | |||
1491 | gr_ctx->t18x.cilp_preempt_pending = true; | 1491 | gr_ctx->t18x.cilp_preempt_pending = true; |
1492 | g->gr.t18x.cilp_preempt_pending_chid = fault_ch->hw_chid; | 1492 | g->gr.t18x.cilp_preempt_pending_chid = fault_ch->hw_chid; |
1493 | 1493 | ||
1494 | if (gk20a_is_channel_marked_as_tsg(fault_ch)) { | ||
1495 | struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid]; | ||
1496 | |||
1497 | gk20a_tsg_event_id_post_event(tsg, | ||
1498 | NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED); | ||
1499 | } else { | ||
1500 | gk20a_channel_event_id_post_event(fault_ch, | ||
1501 | NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED); | ||
1502 | } | ||
1503 | |||
1494 | return 0; | 1504 | return 0; |
1495 | } | 1505 | } |
1496 | 1506 | ||
@@ -1684,8 +1694,6 @@ static int gr_gp10b_handle_fecs_error(struct gk20a *g, | |||
1684 | } | 1694 | } |
1685 | 1695 | ||
1686 | if (gk20a_gr_sm_debugger_attached(g)) { | 1696 | if (gk20a_gr_sm_debugger_attached(g)) { |
1687 | gk20a_err(dev_from_gk20a(g), "CILP: posting usermode event"); | ||
1688 | |||
1689 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 1697 | if (gk20a_is_channel_marked_as_tsg(ch)) { |
1690 | struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; | 1698 | struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; |
1691 | struct channel_gk20a *__ch; | 1699 | struct channel_gk20a *__ch; |
@@ -1693,12 +1701,16 @@ static int gr_gp10b_handle_fecs_error(struct gk20a *g, | |||
1693 | mutex_lock(&tsg->ch_list_lock); | 1701 | mutex_lock(&tsg->ch_list_lock); |
1694 | list_for_each_entry(__ch, &tsg->ch_list, ch_entry) { | 1702 | list_for_each_entry(__ch, &tsg->ch_list, ch_entry) { |
1695 | gk20a_dbg_gpu_post_events(__ch); | 1703 | gk20a_dbg_gpu_post_events(__ch); |
1696 | gk20a_channel_post_event(__ch); | ||
1697 | } | 1704 | } |
1698 | mutex_unlock(&tsg->ch_list_lock); | 1705 | mutex_unlock(&tsg->ch_list_lock); |
1706 | |||
1707 | gk20a_tsg_event_id_post_event(tsg, | ||
1708 | NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); | ||
1699 | } else { | 1709 | } else { |
1700 | gk20a_dbg_gpu_post_events(ch); | 1710 | gk20a_dbg_gpu_post_events(ch); |
1701 | gk20a_channel_post_event(ch); | 1711 | |
1712 | gk20a_channel_event_id_post_event(ch, | ||
1713 | NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); | ||
1702 | } | 1714 | } |
1703 | } | 1715 | } |
1704 | 1716 | ||