diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 13 |
5 files changed, 25 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 0d7a6bec..189ec330 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -3114,10 +3114,10 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3114 | __func__, cmd); | 3114 | __func__, cmd); |
3115 | break; | 3115 | break; |
3116 | } | 3116 | } |
3117 | /* enable channel */ | 3117 | if (ch->g->ops.fifo.enable_channel) |
3118 | gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid), | 3118 | ch->g->ops.fifo.enable_channel(ch); |
3119 | gk20a_readl(ch->g, ccsr_channel_r(ch->hw_chid)) | | 3119 | else |
3120 | ccsr_channel_enable_set_true_f()); | 3120 | err = -ENOSYS; |
3121 | gk20a_idle(dev); | 3121 | gk20a_idle(dev); |
3122 | break; | 3122 | break; |
3123 | case NVGPU_IOCTL_CHANNEL_DISABLE: | 3123 | case NVGPU_IOCTL_CHANNEL_DISABLE: |
@@ -3128,10 +3128,10 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3128 | __func__, cmd); | 3128 | __func__, cmd); |
3129 | break; | 3129 | break; |
3130 | } | 3130 | } |
3131 | /* disable channel */ | 3131 | if (ch->g->ops.fifo.disable_channel) |
3132 | gk20a_writel(ch->g, ccsr_channel_r(ch->hw_chid), | 3132 | ch->g->ops.fifo.disable_channel(ch); |
3133 | gk20a_readl(ch->g, ccsr_channel_r(ch->hw_chid)) | | 3133 | else |
3134 | ccsr_channel_enable_clr_true_f()); | 3134 | err = -ENOSYS; |
3135 | gk20a_idle(dev); | 3135 | gk20a_idle(dev); |
3136 | break; | 3136 | break; |
3137 | case NVGPU_IOCTL_CHANNEL_PREEMPT: | 3137 | case NVGPU_IOCTL_CHANNEL_PREEMPT: |
@@ -3153,7 +3153,7 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3153 | __func__, cmd); | 3153 | __func__, cmd); |
3154 | break; | 3154 | break; |
3155 | } | 3155 | } |
3156 | err = gk20a_fifo_force_reset_ch(ch, true); | 3156 | err = ch->g->ops.fifo.force_reset_ch(ch, true); |
3157 | gk20a_idle(dev); | 3157 | gk20a_idle(dev); |
3158 | break; | 3158 | break; |
3159 | case NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL: | 3159 | case NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL: |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index aa8e0c40..eccea4d4 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -2693,4 +2693,5 @@ void gk20a_init_fifo(struct gpu_ops *gops) | |||
2693 | gops->fifo.get_num_fifos = gk20a_fifo_get_num_fifos; | 2693 | gops->fifo.get_num_fifos = gk20a_fifo_get_num_fifos; |
2694 | gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature; | 2694 | gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature; |
2695 | gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave; | 2695 | gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave; |
2696 | gops->fifo.force_reset_ch = gk20a_fifo_force_reset_ch; | ||
2696 | } | 2697 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 0b15783b..ebc18d5d 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -319,6 +319,7 @@ struct gpu_ops { | |||
319 | u32 new_level); | 319 | u32 new_level); |
320 | int (*channel_set_timeslice)(struct channel_gk20a *ch, | 320 | int (*channel_set_timeslice)(struct channel_gk20a *ch, |
321 | u32 timeslice); | 321 | u32 timeslice); |
322 | int (*force_reset_ch)(struct channel_gk20a *ch, bool verbose); | ||
322 | } fifo; | 323 | } fifo; |
323 | struct pmu_v { | 324 | struct pmu_v { |
324 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ | 325 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 8586262f..e738b1d2 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -125,4 +125,5 @@ void gm20b_init_fifo(struct gpu_ops *gops) | |||
125 | gops->fifo.get_num_fifos = gm20b_fifo_get_num_fifos; | 125 | gops->fifo.get_num_fifos = gm20b_fifo_get_num_fifos; |
126 | gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature; | 126 | gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature; |
127 | gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave; | 127 | gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave; |
128 | gops->fifo.force_reset_ch = gk20a_fifo_force_reset_ch; | ||
128 | } | 129 | } |
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index dc82d57b..66b5e410 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -585,6 +585,17 @@ static int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) | |||
585 | return err ? err : msg.ret; | 585 | return err ? err : msg.ret; |
586 | } | 586 | } |
587 | 587 | ||
588 | static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose) | ||
589 | { | ||
590 | gk20a_dbg_fn(""); | ||
591 | |||
592 | if (verbose) | ||
593 | gk20a_warn(dev_from_gk20a(ch->g), | ||
594 | "channel force reset is not supported"); | ||
595 | |||
596 | return -ENOSYS; | ||
597 | } | ||
598 | |||
588 | static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, | 599 | static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, |
589 | struct channel_gk20a *ch) | 600 | struct channel_gk20a *ch) |
590 | { | 601 | { |
@@ -664,6 +675,7 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops) | |||
664 | { | 675 | { |
665 | gops->fifo.bind_channel = vgpu_channel_bind; | 676 | gops->fifo.bind_channel = vgpu_channel_bind; |
666 | gops->fifo.unbind_channel = vgpu_channel_unbind; | 677 | gops->fifo.unbind_channel = vgpu_channel_unbind; |
678 | gops->fifo.enable_channel = NULL; | ||
667 | gops->fifo.disable_channel = vgpu_channel_disable; | 679 | gops->fifo.disable_channel = vgpu_channel_disable; |
668 | gops->fifo.alloc_inst = vgpu_channel_alloc_inst; | 680 | gops->fifo.alloc_inst = vgpu_channel_alloc_inst; |
669 | gops->fifo.free_inst = vgpu_channel_free_inst; | 681 | gops->fifo.free_inst = vgpu_channel_free_inst; |
@@ -674,4 +686,5 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops) | |||
674 | gops->fifo.channel_set_priority = vgpu_channel_set_priority; | 686 | gops->fifo.channel_set_priority = vgpu_channel_set_priority; |
675 | gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave; | 687 | gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave; |
676 | gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice; | 688 | gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice; |
689 | gops->fifo.force_reset_ch = vgpu_fifo_force_reset_ch; | ||
677 | } | 690 | } |