diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 185 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gv11b.c | 120 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gv11b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/enabled.h | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 410 |
9 files changed, 729 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 2ae1b758..f1dc2f03 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -436,6 +436,7 @@ struct gpu_ops { | |||
436 | void (*init_gfxp_wfi_timeout_count)(struct gk20a *g); | 436 | void (*init_gfxp_wfi_timeout_count)(struct gk20a *g); |
437 | unsigned long (*get_max_gfxp_wfi_timeout_count) | 437 | unsigned long (*get_max_gfxp_wfi_timeout_count) |
438 | (struct gk20a *g); | 438 | (struct gk20a *g); |
439 | void (*ecc_init_scrub_reg)(struct gk20a *g); | ||
439 | } gr; | 440 | } gr; |
440 | struct { | 441 | struct { |
441 | void (*init_hw)(struct gk20a *g); | 442 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 99f85b57..ea4d1d24 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4478,7 +4478,10 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4478 | if (g->ops.gr.enable_gpc_exceptions) | 4478 | if (g->ops.gr.enable_gpc_exceptions) |
4479 | g->ops.gr.enable_gpc_exceptions(g); | 4479 | g->ops.gr.enable_gpc_exceptions(g); |
4480 | 4480 | ||
4481 | /* TBD: ECC for L1/SM */ | 4481 | /* enable ECC for L1/SM */ |
4482 | if (g->ops.gr.ecc_init_scrub_reg) | ||
4483 | g->ops.gr.ecc_init_scrub_reg(g); | ||
4484 | |||
4482 | /* TBD: enable per BE exceptions */ | 4485 | /* TBD: enable per BE exceptions */ |
4483 | 4486 | ||
4484 | /* reset and enable exceptions */ | 4487 | /* reset and enable exceptions */ |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 033d83d5..8514cc1e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -44,6 +44,7 @@ | |||
44 | #include "gv11b/gr_gv11b.h" | 44 | #include "gv11b/gr_gv11b.h" |
45 | #include "gv11b/mm_gv11b.h" | 45 | #include "gv11b/mm_gv11b.h" |
46 | #include "gv11b/subctx_gv11b.h" | 46 | #include "gv11b/subctx_gv11b.h" |
47 | #include "gv11b/gv11b.h" | ||
47 | 48 | ||
48 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> | 49 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> |
49 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> | 50 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> |
@@ -57,6 +58,10 @@ | |||
57 | 58 | ||
58 | #define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 1000 | 59 | #define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 1000 |
59 | 60 | ||
61 | /* ecc scrubbing will done in 1 pri read cycle,but for safety used 10 retries */ | ||
62 | #define ECC_SCRUBBING_TIMEOUT_MAX 1000 | ||
63 | #define ECC_SCRUBBING_TIMEOUT_DEFAULT 10 | ||
64 | |||
60 | bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) | 65 | bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) |
61 | { | 66 | { |
62 | bool valid = false; | 67 | bool valid = false; |
@@ -3674,3 +3679,183 @@ unsigned long gr_gv11b_get_max_gfxp_wfi_timeout_count(struct gk20a *g) | |||
3674 | /* 100 msec in usec count */ | 3679 | /* 100 msec in usec count */ |
3675 | return (100 * 1000UL); | 3680 | return (100 * 1000UL); |
3676 | } | 3681 | } |
3682 | |||
3683 | static int gr_gv11b_ecc_scrub_is_done(struct gk20a *g, | ||
3684 | u32 scrub_reg, u32 scrub_mask, u32 scrub_done) | ||
3685 | { | ||
3686 | struct nvgpu_timeout timeout; | ||
3687 | int status = 0; | ||
3688 | u32 val; | ||
3689 | |||
3690 | nvgpu_timeout_init(g, &timeout, | ||
3691 | ECC_SCRUBBING_TIMEOUT_MAX / | ||
3692 | ECC_SCRUBBING_TIMEOUT_DEFAULT, | ||
3693 | NVGPU_TIMER_RETRY_TIMER); | ||
3694 | do { | ||
3695 | val = gk20a_readl(g, scrub_reg); | ||
3696 | if ((val & scrub_mask) == scrub_done) | ||
3697 | goto exit; | ||
3698 | nvgpu_udelay(ECC_SCRUBBING_TIMEOUT_DEFAULT); | ||
3699 | } while (!nvgpu_timeout_expired(&timeout)); | ||
3700 | |||
3701 | if (nvgpu_timeout_peek_expired(&timeout)) | ||
3702 | status = -ETIMEDOUT; | ||
3703 | exit: | ||
3704 | return status; | ||
3705 | |||
3706 | } | ||
3707 | |||
3708 | static int gr_gv11b_ecc_scrub_sm_lrf(struct gk20a *g) | ||
3709 | { | ||
3710 | u32 scrub_mask, scrub_done; | ||
3711 | |||
3712 | if (!nvgpu_is_enabled(g, NVGPU_ECC_ENABLED_SM_LRF)) { | ||
3713 | nvgpu_log_info(g, "ECC SM LRF is disabled"); | ||
3714 | return 0; | ||
3715 | } | ||
3716 | |||
3717 | nvgpu_log_info(g, "gr_gv11b_ecc_scrub_sm_lrf"); | ||
3718 | scrub_mask = | ||
3719 | (gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_task_f() | | ||
3720 | gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_task_f() | | ||
3721 | gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_task_f() | | ||
3722 | gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_task_f() | | ||
3723 | gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_task_f() | | ||
3724 | gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_task_f() | | ||
3725 | gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_task_f() | | ||
3726 | gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_task_f()); | ||
3727 | |||
3728 | /* Issue scrub lrf regions with single write command */ | ||
3729 | gk20a_writel(g, gr_pri_gpcs_tpcs_sm_lrf_ecc_control_r(), scrub_mask); | ||
3730 | |||
3731 | scrub_done = | ||
3732 | (gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_init_f() | | ||
3733 | gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_init_f() | | ||
3734 | gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_init_f() | | ||
3735 | gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_init_f() | | ||
3736 | gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_init_f() | | ||
3737 | gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_init_f() | | ||
3738 | gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_init_f() | | ||
3739 | gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_init_f()); | ||
3740 | |||
3741 | return gr_gv11b_ecc_scrub_is_done(g, | ||
3742 | gr_pri_gpc0_tpc0_sm_lrf_ecc_control_r(), | ||
3743 | scrub_mask, scrub_done); | ||
3744 | } | ||
3745 | |||
3746 | static int gr_gv11b_ecc_scrub_sm_l1_data(struct gk20a *g) | ||
3747 | { | ||
3748 | u32 scrub_mask, scrub_done; | ||
3749 | |||
3750 | if (!nvgpu_is_enabled(g, NVGPU_ECC_ENABLED_SM_L1_DATA)) { | ||
3751 | nvgpu_log_info(g, "ECC L1DATA is disabled"); | ||
3752 | return 0; | ||
3753 | } | ||
3754 | nvgpu_log_info(g, "gr_gv11b_ecc_scrub_sm_l1_data"); | ||
3755 | scrub_mask = | ||
3756 | (gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_task_f() | | ||
3757 | gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_task_f()); | ||
3758 | |||
3759 | gk20a_writel(g, gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_r(), | ||
3760 | scrub_mask); | ||
3761 | |||
3762 | scrub_done = | ||
3763 | (gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_init_f() | | ||
3764 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_init_f()); | ||
3765 | return gr_gv11b_ecc_scrub_is_done(g, | ||
3766 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_r(), | ||
3767 | scrub_mask, scrub_done); | ||
3768 | } | ||
3769 | |||
3770 | static int gr_gv11b_ecc_scrub_sm_l1_tag(struct gk20a *g) | ||
3771 | { | ||
3772 | u32 scrub_mask, scrub_done; | ||
3773 | |||
3774 | if (!nvgpu_is_enabled(g, NVGPU_ECC_ENABLED_SM_L1_TAG)) { | ||
3775 | nvgpu_log_info(g, "ECC L1TAG is disabled"); | ||
3776 | return 0; | ||
3777 | } | ||
3778 | nvgpu_log_info(g, "gr_gv11b_ecc_scrub_sm_l1_tag"); | ||
3779 | scrub_mask = | ||
3780 | (gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_task_f() | | ||
3781 | gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_task_f()); | ||
3782 | gk20a_writel(g, gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_r(), scrub_mask); | ||
3783 | |||
3784 | scrub_done = | ||
3785 | (gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_init_f() | | ||
3786 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_init_f()); | ||
3787 | return gr_gv11b_ecc_scrub_is_done(g, | ||
3788 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_r(), | ||
3789 | scrub_mask, scrub_done); | ||
3790 | } | ||
3791 | |||
3792 | static int gr_gv11b_ecc_scrub_sm_cbu(struct gk20a *g) | ||
3793 | { | ||
3794 | u32 scrub_mask, scrub_done; | ||
3795 | |||
3796 | if (!nvgpu_is_enabled(g, NVGPU_ECC_ENABLED_SM_CBU)) { | ||
3797 | nvgpu_log_info(g, "ECC CBU is disabled"); | ||
3798 | return 0; | ||
3799 | } | ||
3800 | nvgpu_log_info(g, "gr_gv11b_ecc_scrub_sm_cbu"); | ||
3801 | scrub_mask = | ||
3802 | (gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_task_f() | | ||
3803 | gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_task_f() | | ||
3804 | gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_task_f() | | ||
3805 | gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_task_f()); | ||
3806 | gk20a_writel(g, gr_pri_gpcs_tpcs_sm_cbu_ecc_control_r(), scrub_mask); | ||
3807 | |||
3808 | scrub_done = | ||
3809 | (gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_init_f() | | ||
3810 | gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_init_f() | | ||
3811 | gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_init_f() | | ||
3812 | gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_init_f()); | ||
3813 | return gr_gv11b_ecc_scrub_is_done(g, | ||
3814 | gr_pri_gpc0_tpc0_sm_cbu_ecc_control_r(), | ||
3815 | scrub_mask, scrub_done); | ||
3816 | } | ||
3817 | |||
3818 | static int gr_gv11b_ecc_scrub_sm_icahe(struct gk20a *g) | ||
3819 | { | ||
3820 | u32 scrub_mask, scrub_done; | ||
3821 | |||
3822 | if (!nvgpu_is_enabled(g, NVGPU_ECC_ENABLED_SM_ICACHE)) { | ||
3823 | nvgpu_log_info(g, "ECC ICAHE is disabled"); | ||
3824 | return 0; | ||
3825 | } | ||
3826 | nvgpu_log_info(g, "gr_gv11b_ecc_scrub_sm_icahe"); | ||
3827 | scrub_mask = | ||
3828 | (gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_task_f() | | ||
3829 | gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_task_f() | | ||
3830 | gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_task_f() | | ||
3831 | gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_task_f()); | ||
3832 | gk20a_writel(g, gr_pri_gpcs_tpcs_sm_icache_ecc_control_r(), scrub_mask); | ||
3833 | |||
3834 | scrub_done = | ||
3835 | (gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_init_f() | | ||
3836 | gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_init_f() | | ||
3837 | gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_init_f() | | ||
3838 | gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_init_f()); | ||
3839 | return gr_gv11b_ecc_scrub_is_done(g, | ||
3840 | gr_pri_gpc0_tpc0_sm_icache_ecc_control_r(), | ||
3841 | scrub_mask, scrub_done); | ||
3842 | } | ||
3843 | |||
3844 | void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g) | ||
3845 | { | ||
3846 | nvgpu_log_fn(g, "ecc srub start "); | ||
3847 | |||
3848 | gv11b_detect_ecc_enabled_units(g); | ||
3849 | |||
3850 | if (gr_gv11b_ecc_scrub_sm_lrf(g)) | ||
3851 | nvgpu_warn(g, "ECC SCRUB SM LRF Failed"); | ||
3852 | if (gr_gv11b_ecc_scrub_sm_l1_data(g)) | ||
3853 | nvgpu_warn(g, "ECC SCRUB SM L1 DATA Failed"); | ||
3854 | if (gr_gv11b_ecc_scrub_sm_l1_tag(g)) | ||
3855 | nvgpu_warn(g, "ECC SCRUB SM L1 TAG Failed"); | ||
3856 | if (gr_gv11b_ecc_scrub_sm_cbu(g)) | ||
3857 | nvgpu_warn(g, "ECC SCRUB SM CBU Failed"); | ||
3858 | if (gr_gv11b_ecc_scrub_sm_icahe(g)) | ||
3859 | nvgpu_warn(g, "ECC SCRUB SM ICACHE Failed"); | ||
3860 | |||
3861 | } | ||
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 7c56f62d..39d12b3f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -216,5 +216,6 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g); | |||
216 | int gr_gv11b_init_preemption_state(struct gk20a *g); | 216 | int gr_gv11b_init_preemption_state(struct gk20a *g); |
217 | void gr_gv11b_init_gfxp_wfi_timeout_count(struct gk20a *g); | 217 | void gr_gv11b_init_gfxp_wfi_timeout_count(struct gk20a *g); |
218 | unsigned long gr_gv11b_get_max_gfxp_wfi_timeout_count(struct gk20a *g); | 218 | unsigned long gr_gv11b_get_max_gfxp_wfi_timeout_count(struct gk20a *g); |
219 | void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g); | ||
219 | 220 | ||
220 | #endif | 221 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c index 211755e5..a62e49fb 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c | |||
@@ -26,8 +26,128 @@ | |||
26 | #include <nvgpu/enabled_t19x.h> | 26 | #include <nvgpu/enabled_t19x.h> |
27 | 27 | ||
28 | #include "gk20a/gk20a.h" | 28 | #include "gk20a/gk20a.h" |
29 | #include "gp10b/gp10b.h" | ||
29 | 30 | ||
30 | #include "gv11b/gv11b.h" | 31 | #include "gv11b/gv11b.h" |
32 | #include <nvgpu/hw/gv11b/hw_fuse_gv11b.h> | ||
33 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> | ||
34 | |||
35 | void gv11b_detect_ecc_enabled_units(struct gk20a *g) | ||
36 | { | ||
37 | u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); | ||
38 | u32 opt_feature_fuses_override_disable = | ||
39 | gk20a_readl(g, | ||
40 | fuse_opt_feature_fuses_override_disable_r()); | ||
41 | u32 fecs_feature_override_ecc = | ||
42 | gk20a_readl(g, | ||
43 | gr_fecs_feature_override_ecc_r()); | ||
44 | |||
45 | if (opt_feature_fuses_override_disable) { | ||
46 | if (opt_ecc_en) { | ||
47 | __nvgpu_set_enabled(g, | ||
48 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
49 | __nvgpu_set_enabled(g, | ||
50 | NVGPU_ECC_ENABLED_SM_L1_DATA, true); | ||
51 | __nvgpu_set_enabled(g, | ||
52 | NVGPU_ECC_ENABLED_SM_L1_TAG, true); | ||
53 | __nvgpu_set_enabled(g, | ||
54 | NVGPU_ECC_ENABLED_SM_ICACHE, true); | ||
55 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true); | ||
56 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true); | ||
57 | } | ||
58 | } else { | ||
59 | /* SM LRF */ | ||
60 | if (gr_fecs_feature_override_ecc_sm_lrf_override_v( | ||
61 | fecs_feature_override_ecc)) { | ||
62 | if (gr_fecs_feature_override_ecc_sm_lrf_v( | ||
63 | fecs_feature_override_ecc)) { | ||
64 | __nvgpu_set_enabled(g, | ||
65 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
66 | } | ||
67 | } else { | ||
68 | if (opt_ecc_en) { | ||
69 | __nvgpu_set_enabled(g, | ||
70 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
71 | } | ||
72 | } | ||
73 | /* SM L1 DATA*/ | ||
74 | if (gr_fecs_feature_override_ecc_sm_l1_data_override_v( | ||
75 | fecs_feature_override_ecc)) { | ||
76 | if (gr_fecs_feature_override_ecc_sm_l1_data_v( | ||
77 | fecs_feature_override_ecc)) { | ||
78 | __nvgpu_set_enabled(g, | ||
79 | NVGPU_ECC_ENABLED_SM_L1_DATA, true); | ||
80 | } | ||
81 | } else { | ||
82 | if (opt_ecc_en) { | ||
83 | __nvgpu_set_enabled(g, | ||
84 | NVGPU_ECC_ENABLED_SM_L1_DATA, true); | ||
85 | } | ||
86 | } | ||
87 | /* SM L1 TAG*/ | ||
88 | if (gr_fecs_feature_override_ecc_sm_l1_tag_override_v( | ||
89 | fecs_feature_override_ecc)) { | ||
90 | if (gr_fecs_feature_override_ecc_sm_l1_tag_v( | ||
91 | fecs_feature_override_ecc)) { | ||
92 | __nvgpu_set_enabled(g, | ||
93 | NVGPU_ECC_ENABLED_SM_L1_TAG, true); | ||
94 | } | ||
95 | } else { | ||
96 | if (opt_ecc_en) { | ||
97 | __nvgpu_set_enabled(g, | ||
98 | NVGPU_ECC_ENABLED_SM_L1_TAG, true); | ||
99 | } | ||
100 | } | ||
101 | /* SM ICACHE*/ | ||
102 | if (gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v( | ||
103 | fecs_feature_override_ecc) && | ||
104 | gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v( | ||
105 | fecs_feature_override_ecc)) { | ||
106 | if (gr_fecs_feature_override_ecc_1_sm_l0_icache_v( | ||
107 | fecs_feature_override_ecc) && | ||
108 | gr_fecs_feature_override_ecc_1_sm_l1_icache_v( | ||
109 | fecs_feature_override_ecc)) { | ||
110 | __nvgpu_set_enabled(g, | ||
111 | NVGPU_ECC_ENABLED_SM_ICACHE, true); | ||
112 | } | ||
113 | } else { | ||
114 | if (opt_ecc_en) { | ||
115 | __nvgpu_set_enabled(g, | ||
116 | NVGPU_ECC_ENABLED_SM_ICACHE, true); | ||
117 | } | ||
118 | } | ||
119 | /* LTC */ | ||
120 | if (gr_fecs_feature_override_ecc_ltc_override_v( | ||
121 | fecs_feature_override_ecc)) { | ||
122 | if (gr_fecs_feature_override_ecc_ltc_v( | ||
123 | fecs_feature_override_ecc)) { | ||
124 | __nvgpu_set_enabled(g, | ||
125 | NVGPU_ECC_ENABLED_LTC, true); | ||
126 | } | ||
127 | } else { | ||
128 | if (opt_ecc_en) { | ||
129 | __nvgpu_set_enabled(g, | ||
130 | NVGPU_ECC_ENABLED_LTC, true); | ||
131 | } | ||
132 | } | ||
133 | /* SM CBU */ | ||
134 | if (gr_fecs_feature_override_ecc_sm_cbu_override_v( | ||
135 | fecs_feature_override_ecc)) { | ||
136 | if (gr_fecs_feature_override_ecc_sm_cbu_v( | ||
137 | fecs_feature_override_ecc)) { | ||
138 | __nvgpu_set_enabled(g, | ||
139 | NVGPU_ECC_ENABLED_SM_CBU, true); | ||
140 | } | ||
141 | } else { | ||
142 | if (opt_ecc_en) { | ||
143 | __nvgpu_set_enabled(g, | ||
144 | NVGPU_ECC_ENABLED_SM_CBU, true); | ||
145 | } | ||
146 | } | ||
147 | } | ||
148 | } | ||
149 | |||
150 | |||
31 | 151 | ||
32 | int gv11b_init_gpu_characteristics(struct gk20a *g) | 152 | int gv11b_init_gpu_characteristics(struct gk20a *g) |
33 | { | 153 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.h b/drivers/gpu/nvgpu/gv11b/gv11b.h index 3d5490e6..17dfa7aa 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gv11b.h | |||
@@ -27,6 +27,7 @@ | |||
27 | 27 | ||
28 | #include "gk20a/gk20a.h" | 28 | #include "gk20a/gk20a.h" |
29 | 29 | ||
30 | void gv11b_detect_ecc_enabled_units(struct gk20a *g); | ||
30 | int gv11b_init_gpu_characteristics(struct gk20a *g); | 31 | int gv11b_init_gpu_characteristics(struct gk20a *g); |
31 | 32 | ||
32 | #endif /* GV11B_H */ | 33 | #endif /* GV11B_H */ |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f6bdf6e5..65cae8de 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -392,6 +392,7 @@ static const struct gpu_ops gv11b_ops = { | |||
392 | gr_gv11b_init_gfxp_wfi_timeout_count, | 392 | gr_gv11b_init_gfxp_wfi_timeout_count, |
393 | .get_max_gfxp_wfi_timeout_count = | 393 | .get_max_gfxp_wfi_timeout_count = |
394 | gr_gv11b_get_max_gfxp_wfi_timeout_count, | 394 | gr_gv11b_get_max_gfxp_wfi_timeout_count, |
395 | .ecc_init_scrub_reg = gr_gv11b_ecc_init_scrub_reg, | ||
395 | }, | 396 | }, |
396 | .fb = { | 397 | .fb = { |
397 | .reset = gv11b_fb_reset, | 398 | .reset = gv11b_fb_reset, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index ad5b3db3..4f31e3e2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -46,6 +46,15 @@ struct gk20a; | |||
46 | #define NVGPU_ECC_ENABLED_TEX 10 | 46 | #define NVGPU_ECC_ENABLED_TEX 10 |
47 | /* L2 ECC is enabled */ | 47 | /* L2 ECC is enabled */ |
48 | #define NVGPU_ECC_ENABLED_LTC 11 | 48 | #define NVGPU_ECC_ENABLED_LTC 11 |
49 | /* SM L1 DATA ECC is enabled */ | ||
50 | #define NVGPU_ECC_ENABLED_SM_L1_DATA 12 | ||
51 | /* SM L1 TAG ECC is enabled */ | ||
52 | #define NVGPU_ECC_ENABLED_SM_L1_TAG 13 | ||
53 | /* SM CBU ECC is enabled */ | ||
54 | #define NVGPU_ECC_ENABLED_SM_CBU 14 | ||
55 | /* SM ICAHE ECC is enabled */ | ||
56 | #define NVGPU_ECC_ENABLED_SM_ICACHE 15 | ||
57 | |||
49 | /* | 58 | /* |
50 | * MM flags. | 59 | * MM flags. |
51 | */ | 60 | */ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 805d8b0e..29999163 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -916,6 +916,366 @@ static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 | |||
916 | { | 916 | { |
917 | return (r >> 0U) & 0xffffU; | 917 | return (r >> 0U) & 0xffffU; |
918 | } | 918 | } |
919 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_r(void) | ||
920 | { | ||
921 | return 0x00419b54U; | ||
922 | } | ||
923 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_f(u32 v) | ||
924 | { | ||
925 | return (v & 0x1U) << 0U; | ||
926 | } | ||
927 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_task_f(void) | ||
928 | { | ||
929 | return 0x1U; | ||
930 | } | ||
931 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_f(u32 v) | ||
932 | { | ||
933 | return (v & 0x1U) << 1U; | ||
934 | } | ||
935 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_task_f(void) | ||
936 | { | ||
937 | return 0x2U; | ||
938 | } | ||
939 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_f(u32 v) | ||
940 | { | ||
941 | return (v & 0x1U) << 2U; | ||
942 | } | ||
943 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_task_f(void) | ||
944 | { | ||
945 | return 0x4U; | ||
946 | } | ||
947 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_f(u32 v) | ||
948 | { | ||
949 | return (v & 0x1U) << 3U; | ||
950 | } | ||
951 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_task_f(void) | ||
952 | { | ||
953 | return 0x8U; | ||
954 | } | ||
955 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_f(u32 v) | ||
956 | { | ||
957 | return (v & 0x1U) << 4U; | ||
958 | } | ||
959 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_task_f(void) | ||
960 | { | ||
961 | return 0x10U; | ||
962 | } | ||
963 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_f(u32 v) | ||
964 | { | ||
965 | return (v & 0x1U) << 5U; | ||
966 | } | ||
967 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_task_f(void) | ||
968 | { | ||
969 | return 0x20U; | ||
970 | } | ||
971 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_f(u32 v) | ||
972 | { | ||
973 | return (v & 0x1U) << 6U; | ||
974 | } | ||
975 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_task_f(void) | ||
976 | { | ||
977 | return 0x40U; | ||
978 | } | ||
979 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_f(u32 v) | ||
980 | { | ||
981 | return (v & 0x1U) << 7U; | ||
982 | } | ||
983 | static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_task_f(void) | ||
984 | { | ||
985 | return 0x80U; | ||
986 | } | ||
987 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_r(void) | ||
988 | { | ||
989 | return 0x00504354U; | ||
990 | } | ||
991 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_f(u32 v) | ||
992 | { | ||
993 | return (v & 0x1U) << 0U; | ||
994 | } | ||
995 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_init_f(void) | ||
996 | { | ||
997 | return 0x0U; | ||
998 | } | ||
999 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_f(u32 v) | ||
1000 | { | ||
1001 | return (v & 0x1U) << 1U; | ||
1002 | } | ||
1003 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_init_f(void) | ||
1004 | { | ||
1005 | return 0x0U; | ||
1006 | } | ||
1007 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_f(u32 v) | ||
1008 | { | ||
1009 | return (v & 0x1U) << 2U; | ||
1010 | } | ||
1011 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_init_f(void) | ||
1012 | { | ||
1013 | return 0x0U; | ||
1014 | } | ||
1015 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_f(u32 v) | ||
1016 | { | ||
1017 | return (v & 0x1U) << 3U; | ||
1018 | } | ||
1019 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_init_f(void) | ||
1020 | { | ||
1021 | return 0x0U; | ||
1022 | } | ||
1023 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_f(u32 v) | ||
1024 | { | ||
1025 | return (v & 0x1U) << 4U; | ||
1026 | } | ||
1027 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_init_f(void) | ||
1028 | { | ||
1029 | return 0x0U; | ||
1030 | } | ||
1031 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_f(u32 v) | ||
1032 | { | ||
1033 | return (v & 0x1U) << 5U; | ||
1034 | } | ||
1035 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_init_f(void) | ||
1036 | { | ||
1037 | return 0x0U; | ||
1038 | } | ||
1039 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_f(u32 v) | ||
1040 | { | ||
1041 | return (v & 0x1U) << 6U; | ||
1042 | } | ||
1043 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_init_f(void) | ||
1044 | { | ||
1045 | return 0x0U; | ||
1046 | } | ||
1047 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_f(u32 v) | ||
1048 | { | ||
1049 | return (v & 0x1U) << 7U; | ||
1050 | } | ||
1051 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_init_f(void) | ||
1052 | { | ||
1053 | return 0x0U; | ||
1054 | } | ||
1055 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_r(void) | ||
1056 | { | ||
1057 | return 0x00419b68U; | ||
1058 | } | ||
1059 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_f(u32 v) | ||
1060 | { | ||
1061 | return (v & 0x1U) << 0U; | ||
1062 | } | ||
1063 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_task_f(void) | ||
1064 | { | ||
1065 | return 0x1U; | ||
1066 | } | ||
1067 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_f(u32 v) | ||
1068 | { | ||
1069 | return (v & 0x1U) << 1U; | ||
1070 | } | ||
1071 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_task_f(void) | ||
1072 | { | ||
1073 | return 0x2U; | ||
1074 | } | ||
1075 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_r(void) | ||
1076 | { | ||
1077 | return 0x00504368U; | ||
1078 | } | ||
1079 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_f(u32 v) | ||
1080 | { | ||
1081 | return (v & 0x1U) << 0U; | ||
1082 | } | ||
1083 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_init_f(void) | ||
1084 | { | ||
1085 | return 0x0U; | ||
1086 | } | ||
1087 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_f(u32 v) | ||
1088 | { | ||
1089 | return (v & 0x1U) << 1U; | ||
1090 | } | ||
1091 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_init_f(void) | ||
1092 | { | ||
1093 | return 0x0U; | ||
1094 | } | ||
1095 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_r(void) | ||
1096 | { | ||
1097 | return 0x00419e20U; | ||
1098 | } | ||
1099 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_f(u32 v) | ||
1100 | { | ||
1101 | return (v & 0x1U) << 0U; | ||
1102 | } | ||
1103 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_task_f(void) | ||
1104 | { | ||
1105 | return 0x1U; | ||
1106 | } | ||
1107 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_f(u32 v) | ||
1108 | { | ||
1109 | return (v & 0x1U) << 1U; | ||
1110 | } | ||
1111 | static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_task_f(void) | ||
1112 | { | ||
1113 | return 0x2U; | ||
1114 | } | ||
1115 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_r(void) | ||
1116 | { | ||
1117 | return 0x00504620U; | ||
1118 | } | ||
1119 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_f(u32 v) | ||
1120 | { | ||
1121 | return (v & 0x1U) << 0U; | ||
1122 | } | ||
1123 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_init_f(void) | ||
1124 | { | ||
1125 | return 0x0U; | ||
1126 | } | ||
1127 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_f(u32 v) | ||
1128 | { | ||
1129 | return (v & 0x1U) << 1U; | ||
1130 | } | ||
1131 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_init_f(void) | ||
1132 | { | ||
1133 | return 0x0U; | ||
1134 | } | ||
1135 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_r(void) | ||
1136 | { | ||
1137 | return 0x00419e34U; | ||
1138 | } | ||
1139 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_f(u32 v) | ||
1140 | { | ||
1141 | return (v & 0x1U) << 0U; | ||
1142 | } | ||
1143 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_task_f(void) | ||
1144 | { | ||
1145 | return 0x1U; | ||
1146 | } | ||
1147 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_f(u32 v) | ||
1148 | { | ||
1149 | return (v & 0x1U) << 1U; | ||
1150 | } | ||
1151 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_task_f(void) | ||
1152 | { | ||
1153 | return 0x2U; | ||
1154 | } | ||
1155 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_f(u32 v) | ||
1156 | { | ||
1157 | return (v & 0x1U) << 2U; | ||
1158 | } | ||
1159 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_task_f(void) | ||
1160 | { | ||
1161 | return 0x4U; | ||
1162 | } | ||
1163 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_f(u32 v) | ||
1164 | { | ||
1165 | return (v & 0x1U) << 3U; | ||
1166 | } | ||
1167 | static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_task_f(void) | ||
1168 | { | ||
1169 | return 0x8U; | ||
1170 | } | ||
1171 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_r(void) | ||
1172 | { | ||
1173 | return 0x00504634U; | ||
1174 | } | ||
1175 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_f(u32 v) | ||
1176 | { | ||
1177 | return (v & 0x1U) << 0U; | ||
1178 | } | ||
1179 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_init_f(void) | ||
1180 | { | ||
1181 | return 0x0U; | ||
1182 | } | ||
1183 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_f(u32 v) | ||
1184 | { | ||
1185 | return (v & 0x1U) << 1U; | ||
1186 | } | ||
1187 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_init_f(void) | ||
1188 | { | ||
1189 | return 0x0U; | ||
1190 | } | ||
1191 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_f(u32 v) | ||
1192 | { | ||
1193 | return (v & 0x1U) << 2U; | ||
1194 | } | ||
1195 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_init_f(void) | ||
1196 | { | ||
1197 | return 0x0U; | ||
1198 | } | ||
1199 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_f(u32 v) | ||
1200 | { | ||
1201 | return (v & 0x1U) << 3U; | ||
1202 | } | ||
1203 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_init_f(void) | ||
1204 | { | ||
1205 | return 0x0U; | ||
1206 | } | ||
1207 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_r(void) | ||
1208 | { | ||
1209 | return 0x00419e48U; | ||
1210 | } | ||
1211 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_f(u32 v) | ||
1212 | { | ||
1213 | return (v & 0x1U) << 0U; | ||
1214 | } | ||
1215 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_task_f(void) | ||
1216 | { | ||
1217 | return 0x1U; | ||
1218 | } | ||
1219 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_f(u32 v) | ||
1220 | { | ||
1221 | return (v & 0x1U) << 1U; | ||
1222 | } | ||
1223 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_task_f(void) | ||
1224 | { | ||
1225 | return 0x2U; | ||
1226 | } | ||
1227 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_f(u32 v) | ||
1228 | { | ||
1229 | return (v & 0x1U) << 2U; | ||
1230 | } | ||
1231 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_task_f(void) | ||
1232 | { | ||
1233 | return 0x4U; | ||
1234 | } | ||
1235 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_f(u32 v) | ||
1236 | { | ||
1237 | return (v & 0x1U) << 3U; | ||
1238 | } | ||
1239 | static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_task_f(void) | ||
1240 | { | ||
1241 | return 0x8U; | ||
1242 | } | ||
1243 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_r(void) | ||
1244 | { | ||
1245 | return 0x00504648U; | ||
1246 | } | ||
1247 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_f(u32 v) | ||
1248 | { | ||
1249 | return (v & 0x1U) << 0U; | ||
1250 | } | ||
1251 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_init_f(void) | ||
1252 | { | ||
1253 | return 0x0U; | ||
1254 | } | ||
1255 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_f(u32 v) | ||
1256 | { | ||
1257 | return (v & 0x1U) << 1U; | ||
1258 | } | ||
1259 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_init_f(void) | ||
1260 | { | ||
1261 | return 0x0U; | ||
1262 | } | ||
1263 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_f(u32 v) | ||
1264 | { | ||
1265 | return (v & 0x1U) << 2U; | ||
1266 | } | ||
1267 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_init_f(void) | ||
1268 | { | ||
1269 | return 0x0U; | ||
1270 | } | ||
1271 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_f(u32 v) | ||
1272 | { | ||
1273 | return (v & 0x1U) << 3U; | ||
1274 | } | ||
1275 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_init_f(void) | ||
1276 | { | ||
1277 | return 0x0U; | ||
1278 | } | ||
919 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) | 1279 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) |
920 | { | 1280 | { |
921 | return 0x005042c4U; | 1281 | return 0x005042c4U; |
@@ -1920,21 +2280,65 @@ static inline u32 gr_fecs_feature_override_ecc_r(void) | |||
1920 | { | 2280 | { |
1921 | return 0x00409658U; | 2281 | return 0x00409658U; |
1922 | } | 2282 | } |
2283 | static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) | ||
2284 | { | ||
2285 | return (r >> 0U) & 0x1U; | ||
2286 | } | ||
1923 | static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) | 2287 | static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) |
1924 | { | 2288 | { |
1925 | return (r >> 3U) & 0x1U; | 2289 | return (r >> 3U) & 0x1U; |
1926 | } | 2290 | } |
2291 | static inline u32 gr_fecs_feature_override_ecc_sm_l1_data_v(u32 r) | ||
2292 | { | ||
2293 | return (r >> 4U) & 0x1U; | ||
2294 | } | ||
2295 | static inline u32 gr_fecs_feature_override_ecc_sm_l1_data_override_v(u32 r) | ||
2296 | { | ||
2297 | return (r >> 7U) & 0x1U; | ||
2298 | } | ||
2299 | static inline u32 gr_fecs_feature_override_ecc_sm_l1_tag_v(u32 r) | ||
2300 | { | ||
2301 | return (r >> 8U) & 0x1U; | ||
2302 | } | ||
2303 | static inline u32 gr_fecs_feature_override_ecc_sm_l1_tag_override_v(u32 r) | ||
2304 | { | ||
2305 | return (r >> 11U) & 0x1U; | ||
2306 | } | ||
2307 | static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) | ||
2308 | { | ||
2309 | return (r >> 12U) & 0x1U; | ||
2310 | } | ||
1927 | static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) | 2311 | static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) |
1928 | { | 2312 | { |
1929 | return (r >> 15U) & 0x1U; | 2313 | return (r >> 15U) & 0x1U; |
1930 | } | 2314 | } |
1931 | static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) | 2315 | static inline u32 gr_fecs_feature_override_ecc_sm_cbu_v(u32 r) |
2316 | { | ||
2317 | return (r >> 20U) & 0x1U; | ||
2318 | } | ||
2319 | static inline u32 gr_fecs_feature_override_ecc_sm_cbu_override_v(u32 r) | ||
2320 | { | ||
2321 | return (r >> 23U) & 0x1U; | ||
2322 | } | ||
2323 | static inline u32 gr_fecs_feature_override_ecc_1_r(void) | ||
2324 | { | ||
2325 | return 0x0040965cU; | ||
2326 | } | ||
2327 | static inline u32 gr_fecs_feature_override_ecc_1_sm_l0_icache_v(u32 r) | ||
1932 | { | 2328 | { |
1933 | return (r >> 0U) & 0x1U; | 2329 | return (r >> 0U) & 0x1U; |
1934 | } | 2330 | } |
1935 | static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) | 2331 | static inline u32 gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v(u32 r) |
1936 | { | 2332 | { |
1937 | return (r >> 12U) & 0x1U; | 2333 | return (r >> 1U) & 0x1U; |
2334 | } | ||
2335 | static inline u32 gr_fecs_feature_override_ecc_1_sm_l1_icache_v(u32 r) | ||
2336 | { | ||
2337 | return (r >> 2U) & 0x1U; | ||
2338 | } | ||
2339 | static inline u32 gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v(u32 r) | ||
2340 | { | ||
2341 | return (r >> 3U) & 0x1U; | ||
1938 | } | 2342 | } |
1939 | static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) | 2343 | static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) |
1940 | { | 2344 | { |