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-rw-r--r--drivers/gpu/nvgpu/vgpu/gr_vgpu.c9
-rw-r--r--include/linux/tegra_vgpu.h6
2 files changed, 7 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index 5477bca0..bb52347f 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -71,15 +71,12 @@ static int vgpu_gr_load_golden_ctx_image(struct gk20a *g,
71int vgpu_gr_init_ctx_state(struct gk20a *g) 71int vgpu_gr_init_ctx_state(struct gk20a *g)
72{ 72{
73 struct gr_gk20a *gr = &g->gr; 73 struct gr_gk20a *gr = &g->gr;
74 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
74 75
75 gk20a_dbg_fn(""); 76 gk20a_dbg_fn("");
76 77
77 vgpu_get_attribute(vgpu_get_handle(g), 78 g->gr.ctx_vars.golden_image_size = priv->constants.golden_ctx_size;
78 TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE, 79 g->gr.ctx_vars.zcull_ctxsw_image_size = priv->constants.zcull_ctx_size;
79 &g->gr.ctx_vars.golden_image_size);
80 vgpu_get_attribute(vgpu_get_handle(g),
81 TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE,
82 &g->gr.ctx_vars.zcull_ctxsw_image_size);
83 if (!g->gr.ctx_vars.golden_image_size || 80 if (!g->gr.ctx_vars.golden_image_size ||
84 !g->gr.ctx_vars.zcull_ctxsw_image_size) 81 !g->gr.ctx_vars.zcull_ctxsw_image_size)
85 return -ENXIO; 82 return -ENXIO;
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 04bb65b3..504a31ad 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -112,8 +112,8 @@ struct tegra_vgpu_channel_hwctx_params {
112 112
113enum { 113enum {
114 TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, /*deprecated */ 114 TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, /*deprecated */
115 TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, 115 TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, /* deprecated */
116 TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, 116 TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, /* deprecated */
117 TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, 117 TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3,
118 TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, 118 TEGRA_VGPU_ATTRIB_GPC_COUNT = 4,
119 TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, 119 TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5,
@@ -409,6 +409,8 @@ struct tegra_vgpu_constants_params {
409 u32 rev; 409 u32 rev;
410 u32 max_freq; 410 u32 max_freq;
411 u32 num_channels; 411 u32 num_channels;
412 u32 golden_ctx_size;
413 u32 zcull_ctx_size;
412}; 414};
413 415
414struct tegra_vgpu_cmd_msg { 416struct tegra_vgpu_cmd_msg {