diff options
23 files changed, 573 insertions, 540 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 58dde415..9f2e0017 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -186,9 +186,9 @@ static int channel_gk20a_set_schedule_params(struct channel_gk20a *c, | |||
186 | } | 186 | } |
187 | 187 | ||
188 | /* set new timeslice */ | 188 | /* set new timeslice */ |
189 | gk20a_mem_wr32(inst_ptr, ram_fc_eng_timeslice_w(), | 189 | gk20a_mem_wr32(inst_ptr, ram_fc_runlist_timeslice_w(), |
190 | value | (shift << 12) | | 190 | value | (shift << 12) | |
191 | fifo_eng_timeslice_enable_true_f()); | 191 | fifo_runlist_timeslice_enable_true_f()); |
192 | 192 | ||
193 | /* enable channel */ | 193 | /* enable channel */ |
194 | gk20a_writel(c->g, ccsr_channel_r(c->hw_chid), | 194 | gk20a_writel(c->g, ccsr_channel_r(c->hw_chid), |
@@ -249,10 +249,10 @@ int channel_gk20a_setup_ramfc(struct channel_gk20a *c, | |||
249 | pbdma_acquire_timeout_man_max_f() | | 249 | pbdma_acquire_timeout_man_max_f() | |
250 | pbdma_acquire_timeout_en_disable_f()); | 250 | pbdma_acquire_timeout_en_disable_f()); |
251 | 251 | ||
252 | gk20a_mem_wr32(inst_ptr, ram_fc_eng_timeslice_w(), | 252 | gk20a_mem_wr32(inst_ptr, ram_fc_runlist_timeslice_w(), |
253 | fifo_eng_timeslice_timeout_128_f() | | 253 | fifo_runlist_timeslice_timeout_128_f() | |
254 | fifo_eng_timeslice_timescale_3_f() | | 254 | fifo_runlist_timeslice_timescale_3_f() | |
255 | fifo_eng_timeslice_enable_true_f()); | 255 | fifo_runlist_timeslice_enable_true_f()); |
256 | 256 | ||
257 | gk20a_mem_wr32(inst_ptr, ram_fc_pb_timeslice_w(), | 257 | gk20a_mem_wr32(inst_ptr, ram_fc_pb_timeslice_w(), |
258 | fifo_pb_timeslice_timeout_16_f() | | 258 | fifo_pb_timeslice_timeout_16_f() | |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_chiplet_pwr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_chiplet_pwr_gk20a.h deleted file mode 100644 index 66bf01b0..00000000 --- a/drivers/gpu/nvgpu/gk20a/hw_chiplet_pwr_gk20a.h +++ /dev/null | |||
@@ -1,85 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_chiplet_pwr_gk20a_h_ | ||
51 | #define _hw_chiplet_pwr_gk20a_h_ | ||
52 | |||
53 | static inline u32 chiplet_pwr_gpcs_weight_6_r(void) | ||
54 | { | ||
55 | return 0x0010e018; | ||
56 | } | ||
57 | static inline u32 chiplet_pwr_gpcs_weight_7_r(void) | ||
58 | { | ||
59 | return 0x0010e01c; | ||
60 | } | ||
61 | static inline u32 chiplet_pwr_gpcs_config_1_r(void) | ||
62 | { | ||
63 | return 0x0010e03c; | ||
64 | } | ||
65 | static inline u32 chiplet_pwr_gpcs_config_1_ba_enable_yes_f(void) | ||
66 | { | ||
67 | return 0x1; | ||
68 | } | ||
69 | static inline u32 chiplet_pwr_fbps_weight_0_r(void) | ||
70 | { | ||
71 | return 0x0010e100; | ||
72 | } | ||
73 | static inline u32 chiplet_pwr_fbps_weight_1_r(void) | ||
74 | { | ||
75 | return 0x0010e104; | ||
76 | } | ||
77 | static inline u32 chiplet_pwr_fbps_config_1_r(void) | ||
78 | { | ||
79 | return 0x0010e13c; | ||
80 | } | ||
81 | static inline u32 chiplet_pwr_fbps_config_1_ba_enable_yes_f(void) | ||
82 | { | ||
83 | return 0x1; | ||
84 | } | ||
85 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h index 1c50d0d5..6b8b6718 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h | |||
@@ -62,6 +62,10 @@ static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) | |||
62 | { | 62 | { |
63 | return 0x0; | 63 | return 0x0; |
64 | } | 64 | } |
65 | static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) | ||
66 | { | ||
67 | return 0x1; | ||
68 | } | ||
65 | static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) | 69 | static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) |
66 | { | 70 | { |
67 | return (r >> 15) & 0x1; | 71 | return (r >> 15) & 0x1; |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h index f549bac4..757ae3f0 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h | |||
@@ -114,19 +114,19 @@ static inline u32 fifo_eng_runlist_pending_true_f(void) | |||
114 | { | 114 | { |
115 | return 0x100000; | 115 | return 0x100000; |
116 | } | 116 | } |
117 | static inline u32 fifo_eng_timeslice_r(u32 i) | 117 | static inline u32 fifo_runlist_timeslice_r(u32 i) |
118 | { | 118 | { |
119 | return 0x00002310 + i*4; | 119 | return 0x00002310 + i*4; |
120 | } | 120 | } |
121 | static inline u32 fifo_eng_timeslice_timeout_128_f(void) | 121 | static inline u32 fifo_runlist_timeslice_timeout_128_f(void) |
122 | { | 122 | { |
123 | return 0x80; | 123 | return 0x80; |
124 | } | 124 | } |
125 | static inline u32 fifo_eng_timeslice_timescale_3_f(void) | 125 | static inline u32 fifo_runlist_timeslice_timescale_3_f(void) |
126 | { | 126 | { |
127 | return 0x3000; | 127 | return 0x3000; |
128 | } | 128 | } |
129 | static inline u32 fifo_eng_timeslice_enable_true_f(void) | 129 | static inline u32 fifo_runlist_timeslice_enable_true_f(void) |
130 | { | 130 | { |
131 | return 0x10000000; | 131 | return 0x10000000; |
132 | } | 132 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gmmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gmmu_gk20a.h index e0118946..45ae59d6 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gmmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gmmu_gk20a.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -142,6 +142,10 @@ static inline u32 gmmu_pte_valid_true_f(void) | |||
142 | { | 142 | { |
143 | return 0x1; | 143 | return 0x1; |
144 | } | 144 | } |
145 | static inline u32 gmmu_pte_valid_false_f(void) | ||
146 | { | ||
147 | return 0x0; | ||
148 | } | ||
145 | static inline u32 gmmu_pte_address_sys_f(u32 v) | 149 | static inline u32 gmmu_pte_address_sys_f(u32 v) |
146 | { | 150 | { |
147 | return (v & 0xfffffff) << 4; | 151 | return (v & 0xfffffff) << 4; |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index f18e19be..463443d6 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -2618,30 +2618,6 @@ static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) | |||
2618 | { | 2618 | { |
2619 | return 0x10000000; | 2619 | return 0x10000000; |
2620 | } | 2620 | } |
2621 | static inline u32 gr_gpcs_tpcs_l1c_pm_r(void) | ||
2622 | { | ||
2623 | return 0x00419ca8; | ||
2624 | } | ||
2625 | static inline u32 gr_gpcs_tpcs_l1c_pm_enable_m(void) | ||
2626 | { | ||
2627 | return 0x1 << 31; | ||
2628 | } | ||
2629 | static inline u32 gr_gpcs_tpcs_l1c_pm_enable_enable_f(void) | ||
2630 | { | ||
2631 | return 0x80000000; | ||
2632 | } | ||
2633 | static inline u32 gr_gpcs_tpcs_l1c_cfg_r(void) | ||
2634 | { | ||
2635 | return 0x00419cb8; | ||
2636 | } | ||
2637 | static inline u32 gr_gpcs_tpcs_l1c_cfg_blkactivity_enable_m(void) | ||
2638 | { | ||
2639 | return 0x1 << 31; | ||
2640 | } | ||
2641 | static inline u32 gr_gpcs_tpcs_l1c_cfg_blkactivity_enable_enable_f(void) | ||
2642 | { | ||
2643 | return 0x80000000; | ||
2644 | } | ||
2645 | static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) | 2621 | static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) |
2646 | { | 2622 | { |
2647 | return 0x00419c00; | 2623 | return 0x00419c00; |
@@ -2654,26 +2630,6 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) | |||
2654 | { | 2630 | { |
2655 | return 0x8; | 2631 | return 0x8; |
2656 | } | 2632 | } |
2657 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_r(void) | ||
2658 | { | ||
2659 | return 0x00419e00; | ||
2660 | } | ||
2661 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(void) | ||
2662 | { | ||
2663 | return 0x1 << 7; | ||
2664 | } | ||
2665 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f(void) | ||
2666 | { | ||
2667 | return 0x80; | ||
2668 | } | ||
2669 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(void) | ||
2670 | { | ||
2671 | return 0x1 << 15; | ||
2672 | } | ||
2673 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f(void) | ||
2674 | { | ||
2675 | return 0x8000; | ||
2676 | } | ||
2677 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) | 2633 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) |
2678 | { | 2634 | { |
2679 | return 0x00419e44; | 2635 | return 0x00419e44; |
@@ -2906,14 +2862,6 @@ static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) | |||
2906 | { | 2862 | { |
2907 | return 0x00419f70; | 2863 | return 0x00419f70; |
2908 | } | 2864 | } |
2909 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_blkactivity_enable_m(void) | ||
2910 | { | ||
2911 | return 0x1 << 1; | ||
2912 | } | ||
2913 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_blkactivity_enable_enable_f(void) | ||
2914 | { | ||
2915 | return 0x2; | ||
2916 | } | ||
2917 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) | 2865 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) |
2918 | { | 2866 | { |
2919 | return 0x1 << 4; | 2867 | return 0x1 << 4; |
@@ -2938,18 +2886,6 @@ static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) | |||
2938 | { | 2886 | { |
2939 | return (v & 0x1) << 0; | 2887 | return (v & 0x1) << 0; |
2940 | } | 2888 | } |
2941 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_blkactivity_enable_m(void) | ||
2942 | { | ||
2943 | return 0x1 << 16; | ||
2944 | } | ||
2945 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_blkactivity_enable_enable_f(void) | ||
2946 | { | ||
2947 | return 0x10000; | ||
2948 | } | ||
2949 | static inline u32 gr_gpcs_tpcs_sm_power_throttle_r(void) | ||
2950 | { | ||
2951 | return 0x00419ed0; | ||
2952 | } | ||
2953 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) | 2889 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) |
2954 | { | 2890 | { |
2955 | return 0x0041be08; | 2891 | return 0x0041be08; |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_ltc_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_ltc_gk20a.h index f60b34e2..6db5654b 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_ltc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_ltc_gk20a.h | |||
@@ -54,6 +54,14 @@ static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) | |||
54 | { | 54 | { |
55 | return 0x001410c8; | 55 | return 0x001410c8; |
56 | } | 56 | } |
57 | static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) | ||
58 | { | ||
59 | return 0x00141200; | ||
60 | } | ||
61 | static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) | ||
62 | { | ||
63 | return 0x0017ea00; | ||
64 | } | ||
57 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) | 65 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) |
58 | { | 66 | { |
59 | return 0x00141104; | 67 | return 0x00141104; |
@@ -104,7 +112,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) | |||
104 | } | 112 | } |
105 | static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) | 113 | static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) |
106 | { | 114 | { |
107 | return 0x0017e8c8; | 115 | return 0x001410c8; |
108 | } | 116 | } |
109 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) | 117 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) |
110 | { | 118 | { |
@@ -242,4 +250,188 @@ static inline u32 ltc_ltc0_ltss_intr_r(void) | |||
242 | { | 250 | { |
243 | return 0x00140820; | 251 | return 0x00140820; |
244 | } | 252 | } |
253 | static inline u32 ltc_ltcs_ltss_intr_r(void) | ||
254 | { | ||
255 | return 0x0017e820; | ||
256 | } | ||
257 | static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) | ||
258 | { | ||
259 | return 0x1 << 20; | ||
260 | } | ||
261 | static inline u32 ltc_ltc0_lts0_intr_r(void) | ||
262 | { | ||
263 | return 0x00141020; | ||
264 | } | ||
265 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) | ||
266 | { | ||
267 | return 0x0017e910; | ||
268 | } | ||
269 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
270 | { | ||
271 | return (r >> 0) & 0x1; | ||
272 | } | ||
273 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
274 | { | ||
275 | return 0x00000001; | ||
276 | } | ||
277 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
278 | { | ||
279 | return 0x1; | ||
280 | } | ||
281 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) | ||
282 | { | ||
283 | return (r >> 8) & 0xf; | ||
284 | } | ||
285 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) | ||
286 | { | ||
287 | return 0x00000003; | ||
288 | } | ||
289 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) | ||
290 | { | ||
291 | return 0x300; | ||
292 | } | ||
293 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) | ||
294 | { | ||
295 | return (r >> 28) & 0x1; | ||
296 | } | ||
297 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) | ||
298 | { | ||
299 | return 0x00000001; | ||
300 | } | ||
301 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) | ||
302 | { | ||
303 | return 0x10000000; | ||
304 | } | ||
305 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) | ||
306 | { | ||
307 | return (r >> 29) & 0x1; | ||
308 | } | ||
309 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) | ||
310 | { | ||
311 | return 0x00000001; | ||
312 | } | ||
313 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) | ||
314 | { | ||
315 | return 0x20000000; | ||
316 | } | ||
317 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) | ||
318 | { | ||
319 | return (r >> 30) & 0x1; | ||
320 | } | ||
321 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) | ||
322 | { | ||
323 | return 0x00000001; | ||
324 | } | ||
325 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) | ||
326 | { | ||
327 | return 0x40000000; | ||
328 | } | ||
329 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) | ||
330 | { | ||
331 | return 0x0017e914; | ||
332 | } | ||
333 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
334 | { | ||
335 | return (r >> 0) & 0x1; | ||
336 | } | ||
337 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
338 | { | ||
339 | return 0x00000001; | ||
340 | } | ||
341 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
342 | { | ||
343 | return 0x1; | ||
344 | } | ||
345 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) | ||
346 | { | ||
347 | return (r >> 8) & 0xf; | ||
348 | } | ||
349 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) | ||
350 | { | ||
351 | return 0x00000003; | ||
352 | } | ||
353 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) | ||
354 | { | ||
355 | return 0x300; | ||
356 | } | ||
357 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) | ||
358 | { | ||
359 | return (r >> 16) & 0x1; | ||
360 | } | ||
361 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) | ||
362 | { | ||
363 | return 0x00000001; | ||
364 | } | ||
365 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) | ||
366 | { | ||
367 | return 0x10000; | ||
368 | } | ||
369 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) | ||
370 | { | ||
371 | return (r >> 28) & 0x1; | ||
372 | } | ||
373 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) | ||
374 | { | ||
375 | return 0x00000001; | ||
376 | } | ||
377 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) | ||
378 | { | ||
379 | return 0x10000000; | ||
380 | } | ||
381 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) | ||
382 | { | ||
383 | return (r >> 29) & 0x1; | ||
384 | } | ||
385 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) | ||
386 | { | ||
387 | return 0x00000001; | ||
388 | } | ||
389 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) | ||
390 | { | ||
391 | return 0x20000000; | ||
392 | } | ||
393 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) | ||
394 | { | ||
395 | return (r >> 30) & 0x1; | ||
396 | } | ||
397 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) | ||
398 | { | ||
399 | return 0x00000001; | ||
400 | } | ||
401 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) | ||
402 | { | ||
403 | return 0x40000000; | ||
404 | } | ||
405 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) | ||
406 | { | ||
407 | return 0x00140910; | ||
408 | } | ||
409 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
410 | { | ||
411 | return (r >> 0) & 0x1; | ||
412 | } | ||
413 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
414 | { | ||
415 | return 0x00000001; | ||
416 | } | ||
417 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
418 | { | ||
419 | return 0x1; | ||
420 | } | ||
421 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) | ||
422 | { | ||
423 | return 0x00140914; | ||
424 | } | ||
425 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
426 | { | ||
427 | return (r >> 0) & 0x1; | ||
428 | } | ||
429 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
430 | { | ||
431 | return 0x00000001; | ||
432 | } | ||
433 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
434 | { | ||
435 | return 0x1; | ||
436 | } | ||
245 | #endif | 437 | #endif |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h index d7d26b80..35312bd4 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_pwr_gk20a.h | |||
@@ -290,6 +290,42 @@ static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) | |||
290 | { | 290 | { |
291 | return (v & 0x1) << 1; | 291 | return (v & 0x1) << 1; |
292 | } | 292 | } |
293 | static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) | ||
294 | { | ||
295 | return (v & 0x1) << 4; | ||
296 | } | ||
297 | static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) | ||
298 | { | ||
299 | return 0x1 << 4; | ||
300 | } | ||
301 | static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) | ||
302 | { | ||
303 | return (r >> 4) & 0x1; | ||
304 | } | ||
305 | static inline u32 pwr_falcon_imemc_r(u32 i) | ||
306 | { | ||
307 | return 0x0010a180 + i*16; | ||
308 | } | ||
309 | static inline u32 pwr_falcon_imemc_offs_f(u32 v) | ||
310 | { | ||
311 | return (v & 0x3f) << 2; | ||
312 | } | ||
313 | static inline u32 pwr_falcon_imemc_blk_f(u32 v) | ||
314 | { | ||
315 | return (v & 0xff) << 8; | ||
316 | } | ||
317 | static inline u32 pwr_falcon_imemc_aincw_f(u32 v) | ||
318 | { | ||
319 | return (v & 0x1) << 24; | ||
320 | } | ||
321 | static inline u32 pwr_falcon_imemd_r(u32 i) | ||
322 | { | ||
323 | return 0x0010a184 + i*16; | ||
324 | } | ||
325 | static inline u32 pwr_falcon_imemt_r(u32 i) | ||
326 | { | ||
327 | return 0x0010a188 + i*16; | ||
328 | } | ||
293 | static inline u32 pwr_falcon_bootvec_r(void) | 329 | static inline u32 pwr_falcon_bootvec_r(void) |
294 | { | 330 | { |
295 | return 0x0010a104; | 331 | return 0x0010a104; |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h index a039685e..0f4f6726 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_ram_gk20a.h | |||
@@ -318,7 +318,7 @@ static inline u32 ram_fc_chid_id_w(void) | |||
318 | { | 318 | { |
319 | return 0; | 319 | return 0; |
320 | } | 320 | } |
321 | static inline u32 ram_fc_eng_timeslice_w(void) | 321 | static inline u32 ram_fc_runlist_timeslice_w(void) |
322 | { | 322 | { |
323 | return 62; | 323 | return 62; |
324 | } | 324 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_therm_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_therm_gk20a.h index 5d6397b4..42a31c5d 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_therm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_therm_gk20a.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -66,70 +66,10 @@ static inline u32 therm_evt_ext_therm_2_r(void) | |||
66 | { | 66 | { |
67 | return 0x00020708; | 67 | return 0x00020708; |
68 | } | 68 | } |
69 | static inline u32 therm_evt_ba_w0_t1h_r(void) | ||
70 | { | ||
71 | return 0x00020750; | ||
72 | } | ||
73 | static inline u32 therm_weight_1_r(void) | 69 | static inline u32 therm_weight_1_r(void) |
74 | { | 70 | { |
75 | return 0x00020024; | 71 | return 0x00020024; |
76 | } | 72 | } |
77 | static inline u32 therm_peakpower_config1_r(u32 i) | ||
78 | { | ||
79 | return 0x00020154 + i*4; | ||
80 | } | ||
81 | static inline u32 therm_peakpower_config1_window_period_2m_v(void) | ||
82 | { | ||
83 | return 0x0000000f; | ||
84 | } | ||
85 | static inline u32 therm_peakpower_config1_window_period_2m_f(void) | ||
86 | { | ||
87 | return 0xf; | ||
88 | } | ||
89 | static inline u32 therm_peakpower_config1_ba_sum_shift_s(void) | ||
90 | { | ||
91 | return 6; | ||
92 | } | ||
93 | static inline u32 therm_peakpower_config1_ba_sum_shift_f(u32 v) | ||
94 | { | ||
95 | return (v & 0x3f) << 8; | ||
96 | } | ||
97 | static inline u32 therm_peakpower_config1_ba_sum_shift_m(void) | ||
98 | { | ||
99 | return 0x3f << 8; | ||
100 | } | ||
101 | static inline u32 therm_peakpower_config1_ba_sum_shift_v(u32 r) | ||
102 | { | ||
103 | return (r >> 8) & 0x3f; | ||
104 | } | ||
105 | static inline u32 therm_peakpower_config1_ba_sum_shift_20_f(void) | ||
106 | { | ||
107 | return 0x1400; | ||
108 | } | ||
109 | static inline u32 therm_peakpower_config1_window_en_enabled_f(void) | ||
110 | { | ||
111 | return 0x80000000; | ||
112 | } | ||
113 | static inline u32 therm_peakpower_config2_r(u32 i) | ||
114 | { | ||
115 | return 0x00020170 + i*4; | ||
116 | } | ||
117 | static inline u32 therm_peakpower_config4_r(u32 i) | ||
118 | { | ||
119 | return 0x000201c0 + i*4; | ||
120 | } | ||
121 | static inline u32 therm_peakpower_config6_r(u32 i) | ||
122 | { | ||
123 | return 0x00020270 + i*4; | ||
124 | } | ||
125 | static inline u32 therm_peakpower_config8_r(u32 i) | ||
126 | { | ||
127 | return 0x000202e8 + i*4; | ||
128 | } | ||
129 | static inline u32 therm_peakpower_config9_r(u32 i) | ||
130 | { | ||
131 | return 0x000202f4 + i*4; | ||
132 | } | ||
133 | static inline u32 therm_config1_r(void) | 73 | static inline u32 therm_config1_r(void) |
134 | { | 74 | { |
135 | return 0x00020050; | 75 | return 0x00020050; |
@@ -222,4 +162,24 @@ static inline u32 therm_hubmmu_idle_filter_value_m(void) | |||
222 | { | 162 | { |
223 | return 0xffffffff << 0; | 163 | return 0xffffffff << 0; |
224 | } | 164 | } |
165 | static inline u32 therm_clk_slowdown_r(u32 i) | ||
166 | { | ||
167 | return 0x00020160 + i*4; | ||
168 | } | ||
169 | static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) | ||
170 | { | ||
171 | return (v & 0x3f) << 16; | ||
172 | } | ||
173 | static inline u32 therm_clk_slowdown_idle_factor_m(void) | ||
174 | { | ||
175 | return 0x3f << 16; | ||
176 | } | ||
177 | static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) | ||
178 | { | ||
179 | return (r >> 16) & 0x3f; | ||
180 | } | ||
181 | static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) | ||
182 | { | ||
183 | return 0x0; | ||
184 | } | ||
225 | #endif | 185 | #endif |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_trim_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_trim_gk20a.h index 826e9bd1..3b0aa05b 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_trim_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_trim_gk20a.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -110,6 +110,10 @@ static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) | |||
110 | { | 110 | { |
111 | return (v & 0xff) << 0; | 111 | return (v & 0xff) << 0; |
112 | } | 112 | } |
113 | static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void) | ||
114 | { | ||
115 | return 0xff << 0; | ||
116 | } | ||
113 | static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) | 117 | static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) |
114 | { | 118 | { |
115 | return (r >> 0) & 0xff; | 119 | return (r >> 0) & 0xff; |
@@ -130,6 +134,10 @@ static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) | |||
130 | { | 134 | { |
131 | return (v & 0x3f) << 16; | 135 | return (v & 0x3f) << 16; |
132 | } | 136 | } |
137 | static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void) | ||
138 | { | ||
139 | return 0x3f << 16; | ||
140 | } | ||
133 | static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) | 141 | static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) |
134 | { | 142 | { |
135 | return (r >> 16) & 0x3f; | 143 | return (r >> 16) & 0x3f; |
diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c index da911979..b02113ad 100644 --- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c | |||
@@ -20,7 +20,6 @@ | |||
20 | */ | 20 | */ |
21 | 21 | ||
22 | #include "gk20a.h" | 22 | #include "gk20a.h" |
23 | #include "hw_chiplet_pwr_gk20a.h" | ||
24 | #include "hw_gr_gk20a.h" | 23 | #include "hw_gr_gk20a.h" |
25 | #include "hw_therm_gk20a.h" | 24 | #include "hw_therm_gk20a.h" |
26 | 25 | ||
@@ -45,78 +44,6 @@ static int gk20a_init_therm_setup_hw(struct gk20a *g) | |||
45 | gk20a_writel(g, therm_evt_ext_therm_2_r(), | 44 | gk20a_writel(g, therm_evt_ext_therm_2_r(), |
46 | NV_THERM_EVT_EXT_THERM_2_INIT); | 45 | NV_THERM_EVT_EXT_THERM_2_INIT); |
47 | 46 | ||
48 | /* | ||
49 | u32 data; | ||
50 | |||
51 | data = gk20a_readl(g, gr_gpcs_tpcs_l1c_cfg_r()); | ||
52 | data = set_field(data, gr_gpcs_tpcs_l1c_cfg_blkactivity_enable_m(), | ||
53 | gr_gpcs_tpcs_l1c_cfg_blkactivity_enable_enable_f()); | ||
54 | gk20a_writel(g, gr_gpcs_tpcs_l1c_cfg_r(), data); | ||
55 | |||
56 | data = gk20a_readl(g, gr_gpcs_tpcs_l1c_pm_r()); | ||
57 | data = set_field(data, gr_gpcs_tpcs_l1c_pm_enable_m(), | ||
58 | gr_gpcs_tpcs_l1c_pm_enable_enable_f()); | ||
59 | gk20a_writel(g, gr_gpcs_tpcs_l1c_pm_r(), data); | ||
60 | |||
61 | data = gk20a_readl(g, gr_gpcs_tpcs_sm_pm_ctrl_r()); | ||
62 | data = set_field(data, gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(), | ||
63 | gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f()); | ||
64 | data = set_field(data, gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(), | ||
65 | gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f()); | ||
66 | gk20a_writel(g, gr_gpcs_tpcs_sm_pm_ctrl_r(), data); | ||
67 | |||
68 | data = gk20a_readl(g, gr_gpcs_tpcs_sm_halfctl_ctrl_r()); | ||
69 | data = set_field(data, gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_blkactivity_enable_m(), | ||
70 | gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_blkactivity_enable_enable_f()); | ||
71 | gk20a_writel(g, gr_gpcs_tpcs_sm_halfctl_ctrl_r(), data); | ||
72 | |||
73 | data = gk20a_readl(g, gr_gpcs_tpcs_sm_debug_sfe_control_r()); | ||
74 | data = set_field(data, gr_gpcs_tpcs_sm_debug_sfe_control_blkactivity_enable_m(), | ||
75 | gr_gpcs_tpcs_sm_debug_sfe_control_blkactivity_enable_enable_f()); | ||
76 | gk20a_writel(g, gr_gpcs_tpcs_sm_debug_sfe_control_r(), data); | ||
77 | |||
78 | gk20a_writel(g, therm_peakpower_config6_r(0), | ||
79 | therm_peakpower_config6_trigger_cfg_1h_intr_f() | | ||
80 | therm_peakpower_config6_trigger_cfg_1l_intr_f()); | ||
81 | |||
82 | gk20a_writel(g, chiplet_pwr_gpcs_config_1_r(), | ||
83 | chiplet_pwr_gpcs_config_1_ba_enable_yes_f()); | ||
84 | gk20a_writel(g, chiplet_pwr_fbps_config_1_r(), | ||
85 | chiplet_pwr_fbps_config_1_ba_enable_yes_f()); | ||
86 | |||
87 | data = gk20a_readl(g, therm_config1_r()); | ||
88 | data = set_field(data, therm_config1_ba_enable_m(), | ||
89 | therm_config1_ba_enable_yes_f()); | ||
90 | gk20a_writel(g, therm_config1_r(), data); | ||
91 | |||
92 | gk20a_writel(g, gr_gpcs_tpcs_sm_power_throttle_r(), 0x441a); | ||
93 | |||
94 | gk20a_writel(g, therm_weight_1_r(), 0xd3); | ||
95 | gk20a_writel(g, chiplet_pwr_gpcs_weight_6_r(), 0x7d); | ||
96 | gk20a_writel(g, chiplet_pwr_gpcs_weight_7_r(), 0xff); | ||
97 | gk20a_writel(g, chiplet_pwr_fbps_weight_0_r(), 0x13000000); | ||
98 | gk20a_writel(g, chiplet_pwr_fbps_weight_1_r(), 0x19); | ||
99 | |||
100 | gk20a_writel(g, therm_peakpower_config8_r(0), 0x8); | ||
101 | gk20a_writel(g, therm_peakpower_config9_r(0), 0x0); | ||
102 | |||
103 | gk20a_writel(g, therm_evt_ba_w0_t1h_r(), 0x100); | ||
104 | |||
105 | gk20a_writel(g, therm_use_a_r(), therm_use_a_ba_w0_t1h_yes_f()); | ||
106 | |||
107 | gk20a_writel(g, therm_peakpower_config1_r(0), | ||
108 | therm_peakpower_config1_window_period_2m_f() | | ||
109 | therm_peakpower_config1_ba_sum_shift_20_f() | | ||
110 | therm_peakpower_config1_window_en_enabled_f()); | ||
111 | |||
112 | gk20a_writel(g, therm_peakpower_config2_r(0), | ||
113 | therm_peakpower_config2_ba_threshold_1h_val_f(1) | | ||
114 | therm_peakpower_config2_ba_threshold_1h_en_enabled_f()); | ||
115 | |||
116 | gk20a_writel(g, therm_peakpower_config4_r(0), | ||
117 | therm_peakpower_config4_ba_threshold_1l_val_f(1) | | ||
118 | therm_peakpower_config4_ba_threshold_1l_en_enabled_f()); | ||
119 | */ | ||
120 | return 0; | 47 | return 0; |
121 | } | 48 | } |
122 | 49 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_chiplet_pwr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_chiplet_pwr_gm20b.h deleted file mode 100644 index a9e28cb5..00000000 --- a/drivers/gpu/nvgpu/gm20b/hw_chiplet_pwr_gm20b.h +++ /dev/null | |||
@@ -1,85 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_chiplet_pwr_gm20b_h_ | ||
51 | #define _hw_chiplet_pwr_gm20b_h_ | ||
52 | |||
53 | static inline u32 chiplet_pwr_gpcs_weight_6_r(void) | ||
54 | { | ||
55 | return 0x0010e018; | ||
56 | } | ||
57 | static inline u32 chiplet_pwr_gpcs_weight_7_r(void) | ||
58 | { | ||
59 | return 0x0010e01c; | ||
60 | } | ||
61 | static inline u32 chiplet_pwr_gpcs_config_1_r(void) | ||
62 | { | ||
63 | return 0x0010e03c; | ||
64 | } | ||
65 | static inline u32 chiplet_pwr_gpcs_config_1_ba_enable_yes_f(void) | ||
66 | { | ||
67 | return 0x1; | ||
68 | } | ||
69 | static inline u32 chiplet_pwr_fbps_weight_0_r(void) | ||
70 | { | ||
71 | return 0x0010e100; | ||
72 | } | ||
73 | static inline u32 chiplet_pwr_fbps_weight_1_r(void) | ||
74 | { | ||
75 | return 0x0010e104; | ||
76 | } | ||
77 | static inline u32 chiplet_pwr_fbps_config_1_r(void) | ||
78 | { | ||
79 | return 0x0010e13c; | ||
80 | } | ||
81 | static inline u32 chiplet_pwr_fbps_config_1_ba_enable_yes_f(void) | ||
82 | { | ||
83 | return 0x1; | ||
84 | } | ||
85 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h index 01161f17..8783a0bc 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h | |||
@@ -90,13 +90,25 @@ static inline u32 ctxsw_prog_main_image_pm_o(void) | |||
90 | { | 90 | { |
91 | return 0x00000028; | 91 | return 0x00000028; |
92 | } | 92 | } |
93 | static inline u32 ctxsw_prog_main_image_pm_mode_v(u32 r) | 93 | static inline u32 ctxsw_prog_main_image_pm_mode_m(void) |
94 | { | 94 | { |
95 | return (r >> 0) & 0x7; | 95 | return 0x7 << 0; |
96 | } | 96 | } |
97 | static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_v(void) | 97 | static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) |
98 | { | 98 | { |
99 | return 0x00000000; | 99 | return 0x0; |
100 | } | ||
101 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) | ||
102 | { | ||
103 | return 0x7 << 3; | ||
104 | } | ||
105 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) | ||
106 | { | ||
107 | return 0x8; | ||
108 | } | ||
109 | static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) | ||
110 | { | ||
111 | return 0x0; | ||
100 | } | 112 | } |
101 | static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) | 113 | static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) |
102 | { | 114 | { |
@@ -178,4 +190,52 @@ static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_strid | |||
178 | { | 190 | { |
179 | return 0x00000002; | 191 | return 0x00000002; |
180 | } | 192 | } |
193 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) | ||
194 | { | ||
195 | return 0x000000a0; | ||
196 | } | ||
197 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) | ||
198 | { | ||
199 | return 2; | ||
200 | } | ||
201 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) | ||
202 | { | ||
203 | return (v & 0x3) << 0; | ||
204 | } | ||
205 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) | ||
206 | { | ||
207 | return 0x3 << 0; | ||
208 | } | ||
209 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) | ||
210 | { | ||
211 | return (r >> 0) & 0x3; | ||
212 | } | ||
213 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) | ||
214 | { | ||
215 | return 0x0; | ||
216 | } | ||
217 | static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) | ||
218 | { | ||
219 | return 0x2; | ||
220 | } | ||
221 | static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) | ||
222 | { | ||
223 | return 0x000000a4; | ||
224 | } | ||
225 | static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) | ||
226 | { | ||
227 | return 0x000000a8; | ||
228 | } | ||
229 | static inline u32 ctxsw_prog_main_image_misc_options_o(void) | ||
230 | { | ||
231 | return 0x0000003c; | ||
232 | } | ||
233 | static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) | ||
234 | { | ||
235 | return 0x1 << 3; | ||
236 | } | ||
237 | static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) | ||
238 | { | ||
239 | return 0x0; | ||
240 | } | ||
181 | #endif | 241 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h index 7655d2a3..91b998ca 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h | |||
@@ -178,9 +178,9 @@ static inline u32 fb_mmu_debug_wr_vol_true_f(void) | |||
178 | { | 178 | { |
179 | return 0x4; | 179 | return 0x4; |
180 | } | 180 | } |
181 | static inline u32 fb_mmu_debug_wr_addr_v(u32 r) | 181 | static inline u32 fb_mmu_debug_wr_addr_f(u32 v) |
182 | { | 182 | { |
183 | return (r >> 4) & 0xfffffff; | 183 | return (v & 0xfffffff) << 4; |
184 | } | 184 | } |
185 | static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) | 185 | static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) |
186 | { | 186 | { |
@@ -198,9 +198,9 @@ static inline u32 fb_mmu_debug_rd_vol_false_f(void) | |||
198 | { | 198 | { |
199 | return 0x0; | 199 | return 0x0; |
200 | } | 200 | } |
201 | static inline u32 fb_mmu_debug_rd_addr_v(u32 r) | 201 | static inline u32 fb_mmu_debug_rd_addr_f(u32 v) |
202 | { | 202 | { |
203 | return (r >> 4) & 0xfffffff; | 203 | return (v & 0xfffffff) << 4; |
204 | } | 204 | } |
205 | static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) | 205 | static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) |
206 | { | 206 | { |
@@ -222,10 +222,6 @@ static inline u32 fb_mmu_vpr_info_r(void) | |||
222 | { | 222 | { |
223 | return 0x00100cd0; | 223 | return 0x00100cd0; |
224 | } | 224 | } |
225 | static inline u32 fb_mmu_vpr_info_fetch_f(u32 v) | ||
226 | { | ||
227 | return (v & 0x1) << 2; | ||
228 | } | ||
229 | static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) | 225 | static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) |
230 | { | 226 | { |
231 | return (r >> 2) & 0x1; | 227 | return (r >> 2) & 0x1; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h index e0f41d34..acbe6a4e 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h | |||
@@ -206,6 +206,10 @@ static inline u32 fifo_intr_en_0_r(void) | |||
206 | { | 206 | { |
207 | return 0x00002140; | 207 | return 0x00002140; |
208 | } | 208 | } |
209 | static inline u32 fifo_intr_en_0_sched_error_m(void) | ||
210 | { | ||
211 | return 0x1 << 8; | ||
212 | } | ||
209 | static inline u32 fifo_intr_en_1_r(void) | 213 | static inline u32 fifo_intr_en_1_r(void) |
210 | { | 214 | { |
211 | return 0x00002528; | 215 | return 0x00002528; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 21a46d33..95d06cc6 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -78,6 +78,26 @@ static inline u32 gr_intr_illegal_method_reset_f(void) | |||
78 | { | 78 | { |
79 | return 0x10; | 79 | return 0x10; |
80 | } | 80 | } |
81 | static inline u32 gr_intr_illegal_notify_pending_f(void) | ||
82 | { | ||
83 | return 0x40; | ||
84 | } | ||
85 | static inline u32 gr_intr_illegal_notify_reset_f(void) | ||
86 | { | ||
87 | return 0x40; | ||
88 | } | ||
89 | static inline u32 gr_intr_firmware_method_f(u32 v) | ||
90 | { | ||
91 | return (v & 0x1) << 8; | ||
92 | } | ||
93 | static inline u32 gr_intr_firmware_method_pending_f(void) | ||
94 | { | ||
95 | return 0x100; | ||
96 | } | ||
97 | static inline u32 gr_intr_firmware_method_reset_f(void) | ||
98 | { | ||
99 | return 0x100; | ||
100 | } | ||
81 | static inline u32 gr_intr_illegal_class_pending_f(void) | 101 | static inline u32 gr_intr_illegal_class_pending_f(void) |
82 | { | 102 | { |
83 | return 0x20; | 103 | return 0x20; |
@@ -86,6 +106,14 @@ static inline u32 gr_intr_illegal_class_reset_f(void) | |||
86 | { | 106 | { |
87 | return 0x20; | 107 | return 0x20; |
88 | } | 108 | } |
109 | static inline u32 gr_intr_fecs_error_pending_f(void) | ||
110 | { | ||
111 | return 0x80000; | ||
112 | } | ||
113 | static inline u32 gr_intr_fecs_error_reset_f(void) | ||
114 | { | ||
115 | return 0x80000; | ||
116 | } | ||
89 | static inline u32 gr_intr_class_error_pending_f(void) | 117 | static inline u32 gr_intr_class_error_pending_f(void) |
90 | { | 118 | { |
91 | return 0x100000; | 119 | return 0x100000; |
@@ -102,6 +130,26 @@ static inline u32 gr_intr_exception_reset_f(void) | |||
102 | { | 130 | { |
103 | return 0x200000; | 131 | return 0x200000; |
104 | } | 132 | } |
133 | static inline u32 gr_fecs_intr_r(void) | ||
134 | { | ||
135 | return 0x00400144; | ||
136 | } | ||
137 | static inline u32 gr_class_error_r(void) | ||
138 | { | ||
139 | return 0x00400110; | ||
140 | } | ||
141 | static inline u32 gr_class_error_code_v(u32 r) | ||
142 | { | ||
143 | return (r >> 0) & 0xffff; | ||
144 | } | ||
145 | static inline u32 gr_intr_nonstall_r(void) | ||
146 | { | ||
147 | return 0x00400120; | ||
148 | } | ||
149 | static inline u32 gr_intr_nonstall_trap_pending_f(void) | ||
150 | { | ||
151 | return 0x2; | ||
152 | } | ||
105 | static inline u32 gr_intr_en_r(void) | 153 | static inline u32 gr_intr_en_r(void) |
106 | { | 154 | { |
107 | return 0x0040013c; | 155 | return 0x0040013c; |
@@ -198,6 +246,10 @@ static inline u32 gr_status_r(void) | |||
198 | { | 246 | { |
199 | return 0x00400700; | 247 | return 0x00400700; |
200 | } | 248 | } |
249 | static inline u32 gr_status_fe_method_upper_v(u32 r) | ||
250 | { | ||
251 | return (r >> 1) & 0x1; | ||
252 | } | ||
201 | static inline u32 gr_status_fe_method_lower_v(u32 r) | 253 | static inline u32 gr_status_fe_method_lower_v(u32 r) |
202 | { | 254 | { |
203 | return (r >> 2) & 0x1; | 255 | return (r >> 2) & 0x1; |
@@ -206,6 +258,10 @@ static inline u32 gr_status_fe_method_lower_idle_v(void) | |||
206 | { | 258 | { |
207 | return 0x00000000; | 259 | return 0x00000000; |
208 | } | 260 | } |
261 | static inline u32 gr_status_fe_gi_v(u32 r) | ||
262 | { | ||
263 | return (r >> 21) & 0x1; | ||
264 | } | ||
209 | static inline u32 gr_status_mask_r(void) | 265 | static inline u32 gr_status_mask_r(void) |
210 | { | 266 | { |
211 | return 0x00400610; | 267 | return 0x00400610; |
@@ -662,6 +718,22 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) | |||
662 | { | 718 | { |
663 | return 0x21; | 719 | return 0x21; |
664 | } | 720 | } |
721 | static inline u32 gr_fecs_host_int_status_r(void) | ||
722 | { | ||
723 | return 0x00409c18; | ||
724 | } | ||
725 | static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) | ||
726 | { | ||
727 | return (v & 0x1) << 17; | ||
728 | } | ||
729 | static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) | ||
730 | { | ||
731 | return (v & 0x1) << 18; | ||
732 | } | ||
733 | static inline u32 gr_fecs_host_int_clear_r(void) | ||
734 | { | ||
735 | return 0x00409c20; | ||
736 | } | ||
665 | static inline u32 gr_fecs_host_int_enable_r(void) | 737 | static inline u32 gr_fecs_host_int_enable_r(void) |
666 | { | 738 | { |
667 | return 0x00409c24; | 739 | return 0x00409c24; |
@@ -2570,26 +2642,6 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) | |||
2570 | { | 2642 | { |
2571 | return 0x10000000; | 2643 | return 0x10000000; |
2572 | } | 2644 | } |
2573 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_r(void) | ||
2574 | { | ||
2575 | return 0x00419e00; | ||
2576 | } | ||
2577 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(void) | ||
2578 | { | ||
2579 | return 0x1 << 7; | ||
2580 | } | ||
2581 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f(void) | ||
2582 | { | ||
2583 | return 0x80; | ||
2584 | } | ||
2585 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(void) | ||
2586 | { | ||
2587 | return 0x1 << 15; | ||
2588 | } | ||
2589 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f(void) | ||
2590 | { | ||
2591 | return 0x8000; | ||
2592 | } | ||
2593 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) | 2645 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) |
2594 | { | 2646 | { |
2595 | return 0x00419e44; | 2647 | return 0x00419e44; |
@@ -2714,51 +2766,51 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complet | |||
2714 | { | 2766 | { |
2715 | return 0x40; | 2767 | return 0x40; |
2716 | } | 2768 | } |
2717 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) | 2769 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) |
2718 | { | 2770 | { |
2719 | return 0x0050450c; | 2771 | return 0x00419d0c; |
2720 | } | 2772 | } |
2721 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) | 2773 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) |
2722 | { | 2774 | { |
2723 | return 0x2; | 2775 | return 0x2; |
2724 | } | 2776 | } |
2725 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_disabled_f(void) | 2777 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) |
2726 | { | 2778 | { |
2727 | return 0x0; | 2779 | return 0x0050450c; |
2728 | } | 2780 | } |
2729 | static inline u32 gr_gpc0_gpccs_gpc_exception_en_r(void) | 2781 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) |
2730 | { | 2782 | { |
2731 | return 0x00502c94; | 2783 | return 0x2; |
2732 | } | 2784 | } |
2733 | static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_enabled_f(void) | 2785 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) |
2734 | { | 2786 | { |
2735 | return 0x10000; | 2787 | return 0x0041ac94; |
2736 | } | 2788 | } |
2737 | static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_disabled_f(void) | 2789 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) |
2738 | { | 2790 | { |
2739 | return 0x0; | 2791 | return (v & 0xff) << 16; |
2740 | } | 2792 | } |
2741 | static inline u32 gr_gpcs_gpccs_gpc_exception_r(void) | 2793 | static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) |
2742 | { | 2794 | { |
2743 | return 0x0041ac90; | 2795 | return 0x00502c90; |
2744 | } | 2796 | } |
2745 | static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_v(u32 r) | 2797 | static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) |
2746 | { | 2798 | { |
2747 | return (r >> 16) & 0xff; | 2799 | return (r >> 16) & 0xff; |
2748 | } | 2800 | } |
2749 | static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_0_pending_v(void) | 2801 | static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) |
2750 | { | 2802 | { |
2751 | return 0x00000001; | 2803 | return 0x00000001; |
2752 | } | 2804 | } |
2753 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_r(void) | 2805 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) |
2754 | { | 2806 | { |
2755 | return 0x00419d08; | 2807 | return 0x00504508; |
2756 | } | 2808 | } |
2757 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_v(u32 r) | 2809 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) |
2758 | { | 2810 | { |
2759 | return (r >> 1) & 0x1; | 2811 | return (r >> 1) & 0x1; |
2760 | } | 2812 | } |
2761 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_pending_v(void) | 2813 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) |
2762 | { | 2814 | { |
2763 | return 0x00000001; | 2815 | return 0x00000001; |
2764 | } | 2816 | } |
@@ -2854,10 +2906,6 @@ static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) | |||
2854 | { | 2906 | { |
2855 | return (v & 0x1) << 0; | 2907 | return (v & 0x1) << 0; |
2856 | } | 2908 | } |
2857 | static inline u32 gr_gpcs_tpcs_sm_power_throttle_r(void) | ||
2858 | { | ||
2859 | return 0x00419ed8; | ||
2860 | } | ||
2861 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) | 2909 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) |
2862 | { | 2910 | { |
2863 | return 0x0041be08; | 2911 | return 0x0041be08; |
@@ -3122,42 +3170,6 @@ static inline u32 gr_fe_pwr_mode_req_done_v(void) | |||
3122 | { | 3170 | { |
3123 | return 0x00000000; | 3171 | return 0x00000000; |
3124 | } | 3172 | } |
3125 | static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_r(void) | ||
3126 | { | ||
3127 | return 0x00419f88; | ||
3128 | } | ||
3129 | static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_f(u32 v) | ||
3130 | { | ||
3131 | return (v & 0x1) << 31; | ||
3132 | } | ||
3133 | static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_m(void) | ||
3134 | { | ||
3135 | return 0x1 << 31; | ||
3136 | } | ||
3137 | static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_r(void) | ||
3138 | { | ||
3139 | return 0x00419f80; | ||
3140 | } | ||
3141 | static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_f(u32 v) | ||
3142 | { | ||
3143 | return (v & 0x1) << 31; | ||
3144 | } | ||
3145 | static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_m(void) | ||
3146 | { | ||
3147 | return 0x1 << 31; | ||
3148 | } | ||
3149 | static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_r(void) | ||
3150 | { | ||
3151 | return 0x00419ccc; | ||
3152 | } | ||
3153 | static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_f(u32 v) | ||
3154 | { | ||
3155 | return (v & 0x1) << 31; | ||
3156 | } | ||
3157 | static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_m(void) | ||
3158 | { | ||
3159 | return 0x1 << 31; | ||
3160 | } | ||
3161 | static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) | 3173 | static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) |
3162 | { | 3174 | { |
3163 | return 0x00418880; | 3175 | return 0x00418880; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h index 467bd665..95e0c43d 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h | |||
@@ -50,6 +50,10 @@ | |||
50 | #ifndef _hw_ltc_gm20b_h_ | 50 | #ifndef _hw_ltc_gm20b_h_ |
51 | #define _hw_ltc_gm20b_h_ | 51 | #define _hw_ltc_gm20b_h_ |
52 | 52 | ||
53 | static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) | ||
54 | { | ||
55 | return 0x0014046c; | ||
56 | } | ||
53 | static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) | 57 | static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) |
54 | { | 58 | { |
55 | return 0x00140518; | 59 | return 0x00140518; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h index 1b741677..96e21899 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h | |||
@@ -50,31 +50,47 @@ | |||
50 | #ifndef _hw_mc_gm20b_h_ | 50 | #ifndef _hw_mc_gm20b_h_ |
51 | #define _hw_mc_gm20b_h_ | 51 | #define _hw_mc_gm20b_h_ |
52 | 52 | ||
53 | static inline u32 mc_intr_0_r(void) | 53 | static inline u32 mc_boot_0_r(void) |
54 | { | 54 | { |
55 | return 0x00000100; | 55 | return 0x00000000; |
56 | } | 56 | } |
57 | static inline u32 mc_intr_0_pfifo_pending_f(void) | 57 | static inline u32 mc_boot_0_architecture_v(u32 r) |
58 | { | 58 | { |
59 | return 0x100; | 59 | return (r >> 24) & 0x1f; |
60 | } | 60 | } |
61 | static inline u32 mc_intr_0_pgraph_pending_f(void) | 61 | static inline u32 mc_boot_0_implementation_v(u32 r) |
62 | { | 62 | { |
63 | return 0x1000; | 63 | return (r >> 20) & 0xf; |
64 | } | ||
65 | static inline u32 mc_boot_0_major_revision_v(u32 r) | ||
66 | { | ||
67 | return (r >> 4) & 0xf; | ||
68 | } | ||
69 | static inline u32 mc_boot_0_minor_revision_v(u32 r) | ||
70 | { | ||
71 | return (r >> 0) & 0xf; | ||
64 | } | 72 | } |
65 | static inline u32 mc_intr_0_pmu_pending_f(void) | 73 | static inline u32 mc_intr_r(u32 i) |
74 | { | ||
75 | return 0x00000100 + i*4; | ||
76 | } | ||
77 | static inline u32 mc_intr_pfifo_pending_f(void) | ||
78 | { | ||
79 | return 0x100; | ||
80 | } | ||
81 | static inline u32 mc_intr_pmu_pending_f(void) | ||
66 | { | 82 | { |
67 | return 0x1000000; | 83 | return 0x1000000; |
68 | } | 84 | } |
69 | static inline u32 mc_intr_0_ltc_pending_f(void) | 85 | static inline u32 mc_intr_ltc_pending_f(void) |
70 | { | 86 | { |
71 | return 0x2000000; | 87 | return 0x2000000; |
72 | } | 88 | } |
73 | static inline u32 mc_intr_0_priv_ring_pending_f(void) | 89 | static inline u32 mc_intr_priv_ring_pending_f(void) |
74 | { | 90 | { |
75 | return 0x40000000; | 91 | return 0x40000000; |
76 | } | 92 | } |
77 | static inline u32 mc_intr_0_pbus_pending_f(void) | 93 | static inline u32 mc_intr_pbus_pending_f(void) |
78 | { | 94 | { |
79 | return 0x10000000; | 95 | return 0x10000000; |
80 | } | 96 | } |
@@ -98,6 +114,30 @@ static inline u32 mc_intr_en_0_inta_hardware_f(void) | |||
98 | { | 114 | { |
99 | return 0x1; | 115 | return 0x1; |
100 | } | 116 | } |
117 | static inline u32 mc_intr_mask_1_r(void) | ||
118 | { | ||
119 | return 0x00000644; | ||
120 | } | ||
121 | static inline u32 mc_intr_mask_1_pmu_s(void) | ||
122 | { | ||
123 | return 1; | ||
124 | } | ||
125 | static inline u32 mc_intr_mask_1_pmu_f(u32 v) | ||
126 | { | ||
127 | return (v & 0x1) << 24; | ||
128 | } | ||
129 | static inline u32 mc_intr_mask_1_pmu_m(void) | ||
130 | { | ||
131 | return 0x1 << 24; | ||
132 | } | ||
133 | static inline u32 mc_intr_mask_1_pmu_v(u32 r) | ||
134 | { | ||
135 | return (r >> 24) & 0x1; | ||
136 | } | ||
137 | static inline u32 mc_intr_mask_1_pmu_enabled_f(void) | ||
138 | { | ||
139 | return 0x1000000; | ||
140 | } | ||
101 | static inline u32 mc_intr_en_1_r(void) | 141 | static inline u32 mc_intr_en_1_r(void) |
102 | { | 142 | { |
103 | return 0x00000144; | 143 | return 0x00000144; |
@@ -106,6 +146,10 @@ static inline u32 mc_intr_en_1_inta_disabled_f(void) | |||
106 | { | 146 | { |
107 | return 0x0; | 147 | return 0x0; |
108 | } | 148 | } |
149 | static inline u32 mc_intr_en_1_inta_hardware_f(void) | ||
150 | { | ||
151 | return 0x1; | ||
152 | } | ||
109 | static inline u32 mc_enable_r(void) | 153 | static inline u32 mc_enable_r(void) |
110 | { | 154 | { |
111 | return 0x00000200; | 155 | return 0x00000200; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_pbdma_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_pbdma_gm20b.h index c64184cb..7b25d4af 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_pbdma_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_pbdma_gm20b.h | |||
@@ -174,6 +174,10 @@ static inline u32 pbdma_pb_header_type_inc_f(void) | |||
174 | { | 174 | { |
175 | return 0x20000000; | 175 | return 0x20000000; |
176 | } | 176 | } |
177 | static inline u32 pbdma_hdr_shadow_r(u32 i) | ||
178 | { | ||
179 | return 0x00040118 + i*8192; | ||
180 | } | ||
177 | static inline u32 pbdma_subdevice_r(u32 i) | 181 | static inline u32 pbdma_subdevice_r(u32 i) |
178 | { | 182 | { |
179 | return 0x00040094 + i*8192; | 183 | return 0x00040094 + i*8192; |
@@ -466,4 +470,20 @@ static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) | |||
466 | { | 470 | { |
467 | return (r >> 8) & 0xff; | 471 | return (r >> 8) & 0xff; |
468 | } | 472 | } |
473 | static inline u32 pbdma_runlist_timeslice_r(u32 i) | ||
474 | { | ||
475 | return 0x000400f8 + i*8192; | ||
476 | } | ||
477 | static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) | ||
478 | { | ||
479 | return 0x80; | ||
480 | } | ||
481 | static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) | ||
482 | { | ||
483 | return 0x3000; | ||
484 | } | ||
485 | static inline u32 pbdma_runlist_timeslice_enable_true_f(void) | ||
486 | { | ||
487 | return 0x10000000; | ||
488 | } | ||
469 | #endif | 489 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_pwr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_pwr_gm20b.h index 384a9ab5..7f1814f0 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_pwr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_pwr_gm20b.h | |||
@@ -378,6 +378,18 @@ static inline u32 pwr_falcon_bootvec_vec_f(u32 v) | |||
378 | { | 378 | { |
379 | return (v & 0xffffffff) << 0; | 379 | return (v & 0xffffffff) << 0; |
380 | } | 380 | } |
381 | static inline u32 pwr_falcon_dmactl_r(void) | ||
382 | { | ||
383 | return 0x0010a10c; | ||
384 | } | ||
385 | static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) | ||
386 | { | ||
387 | return 0x1 << 1; | ||
388 | } | ||
389 | static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) | ||
390 | { | ||
391 | return 0x1 << 2; | ||
392 | } | ||
381 | static inline u32 pwr_falcon_hwcfg_r(void) | 393 | static inline u32 pwr_falcon_hwcfg_r(void) |
382 | { | 394 | { |
383 | return 0x0010a108; | 395 | return 0x0010a108; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_ram_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ram_gm20b.h index 2e1df1d4..a05f1c2b 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_ram_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_ram_gm20b.h | |||
@@ -338,7 +338,7 @@ static inline u32 ram_fc_chid_id_w(void) | |||
338 | { | 338 | { |
339 | return 0; | 339 | return 0; |
340 | } | 340 | } |
341 | static inline u32 ram_fc_pb_timeslice_w(void) | 341 | static inline u32 ram_fc_runlist_timeslice_w(void) |
342 | { | 342 | { |
343 | return 62; | 343 | return 62; |
344 | } | 344 | } |
@@ -402,4 +402,44 @@ static inline u32 ram_rl_entry_size_v(void) | |||
402 | { | 402 | { |
403 | return 0x00000008; | 403 | return 0x00000008; |
404 | } | 404 | } |
405 | static inline u32 ram_rl_entry_chid_f(u32 v) | ||
406 | { | ||
407 | return (v & 0xfff) << 0; | ||
408 | } | ||
409 | static inline u32 ram_rl_entry_id_f(u32 v) | ||
410 | { | ||
411 | return (v & 0xfff) << 0; | ||
412 | } | ||
413 | static inline u32 ram_rl_entry_type_f(u32 v) | ||
414 | { | ||
415 | return (v & 0x1) << 13; | ||
416 | } | ||
417 | static inline u32 ram_rl_entry_type_chid_f(void) | ||
418 | { | ||
419 | return 0x0; | ||
420 | } | ||
421 | static inline u32 ram_rl_entry_type_tsg_f(void) | ||
422 | { | ||
423 | return 0x2000; | ||
424 | } | ||
425 | static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) | ||
426 | { | ||
427 | return (v & 0xf) << 14; | ||
428 | } | ||
429 | static inline u32 ram_rl_entry_timeslice_scale_3_f(void) | ||
430 | { | ||
431 | return 0xc000; | ||
432 | } | ||
433 | static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) | ||
434 | { | ||
435 | return (v & 0xff) << 18; | ||
436 | } | ||
437 | static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) | ||
438 | { | ||
439 | return 0x2000000; | ||
440 | } | ||
441 | static inline u32 ram_rl_entry_tsg_length_f(u32 v) | ||
442 | { | ||
443 | return (v & 0x3f) << 26; | ||
444 | } | ||
405 | #endif | 445 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h index 09bd5830..d928d70e 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h | |||
@@ -66,66 +66,10 @@ static inline u32 therm_evt_ext_therm_2_r(void) | |||
66 | { | 66 | { |
67 | return 0x00020708; | 67 | return 0x00020708; |
68 | } | 68 | } |
69 | static inline u32 therm_evt_ba_w0_t1h_r(void) | ||
70 | { | ||
71 | return 0x00020750; | ||
72 | } | ||
73 | static inline u32 therm_weight_1_r(void) | 69 | static inline u32 therm_weight_1_r(void) |
74 | { | 70 | { |
75 | return 0x00020024; | 71 | return 0x00020024; |
76 | } | 72 | } |
77 | static inline u32 therm_peakpower_config1_r(u32 i) | ||
78 | { | ||
79 | return 0x00020154 + i*4; | ||
80 | } | ||
81 | static inline u32 therm_peakpower_config1_window_period_2m_v(void) | ||
82 | { | ||
83 | return 0x0000000f; | ||
84 | } | ||
85 | static inline u32 therm_peakpower_config1_window_period_2m_f(void) | ||
86 | { | ||
87 | return 0xf; | ||
88 | } | ||
89 | static inline u32 therm_peakpower_config1_window_en_enabled_f(void) | ||
90 | { | ||
91 | return 0x80000000; | ||
92 | } | ||
93 | static inline u32 therm_peakpower_config8_r(u32 i) | ||
94 | { | ||
95 | return 0x000202e8 + i*4; | ||
96 | } | ||
97 | static inline u32 therm_peakpower_config8_ba_sum_shift_s(void) | ||
98 | { | ||
99 | return 5; | ||
100 | } | ||
101 | static inline u32 therm_peakpower_config8_ba_sum_shift_f(u32 v) | ||
102 | { | ||
103 | return (v & 0x1f) << 8; | ||
104 | } | ||
105 | static inline u32 therm_peakpower_config8_ba_sum_shift_m(void) | ||
106 | { | ||
107 | return 0x1f << 8; | ||
108 | } | ||
109 | static inline u32 therm_peakpower_config8_ba_sum_shift_v(u32 r) | ||
110 | { | ||
111 | return (r >> 8) & 0x1f; | ||
112 | } | ||
113 | static inline u32 therm_peakpower_config2_r(u32 i) | ||
114 | { | ||
115 | return 0x00020170 + i*4; | ||
116 | } | ||
117 | static inline u32 therm_peakpower_config4_r(u32 i) | ||
118 | { | ||
119 | return 0x000201c0 + i*4; | ||
120 | } | ||
121 | static inline u32 therm_peakpower_config6_r(u32 i) | ||
122 | { | ||
123 | return 0x00020270 + i*4; | ||
124 | } | ||
125 | static inline u32 therm_peakpower_config9_r(u32 i) | ||
126 | { | ||
127 | return 0x000202f4 + i*4; | ||
128 | } | ||
129 | static inline u32 therm_config1_r(void) | 73 | static inline u32 therm_config1_r(void) |
130 | { | 74 | { |
131 | return 0x00020050; | 75 | return 0x00020050; |