diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 2 |
4 files changed, 23 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 70b1ac5f..a0a67332 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -295,6 +295,7 @@ struct gpu_ops { | |||
295 | u32 gpc, u32 tpc, u32 sm); | 295 | u32 gpc, u32 tpc, u32 sm); |
296 | u32 (*get_sm_hww_global_esr)(struct gk20a *g, | 296 | u32 (*get_sm_hww_global_esr)(struct gk20a *g, |
297 | u32 gpc, u32 tpc, u32 sm); | 297 | u32 gpc, u32 tpc, u32 sm); |
298 | u32 (*get_sm_no_lock_down_hww_global_esr_mask)(struct gk20a *g); | ||
298 | void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc, | 299 | void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc, |
299 | u32 *esr_sm_sel); | 300 | u32 *esr_sm_sel); |
300 | int (*handle_sm_exception)(struct gk20a *g, | 301 | int (*handle_sm_exception)(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index b714b2e2..d325f794 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5527,16 +5527,7 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | |||
5527 | bool disable_sm_exceptions = true; | 5527 | bool disable_sm_exceptions = true; |
5528 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); | 5528 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); |
5529 | bool sm_debugger_attached; | 5529 | bool sm_debugger_attached; |
5530 | u32 global_esr, warp_esr; | 5530 | u32 global_esr, warp_esr, global_mask; |
5531 | |||
5532 | /* these three interrupts don't require locking down the SM. They can | ||
5533 | * be handled by usermode clients as they aren't fatal. Additionally, | ||
5534 | * usermode clients may wish to allow some warps to execute while others | ||
5535 | * are at breakpoints, as opposed to fatal errors where all warps should | ||
5536 | * halt. */ | ||
5537 | u32 global_mask = gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f() | | ||
5538 | gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() | | ||
5539 | gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(); | ||
5540 | 5531 | ||
5541 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); | 5532 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); |
5542 | 5533 | ||
@@ -5545,6 +5536,7 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | |||
5545 | global_esr = g->ops.gr.get_sm_hww_global_esr(g, gpc, tpc, sm); | 5536 | global_esr = g->ops.gr.get_sm_hww_global_esr(g, gpc, tpc, sm); |
5546 | *hww_global_esr = global_esr; | 5537 | *hww_global_esr = global_esr; |
5547 | warp_esr = g->ops.gr.get_sm_hww_warp_esr(g, gpc, tpc, sm); | 5538 | warp_esr = g->ops.gr.get_sm_hww_warp_esr(g, gpc, tpc, sm); |
5539 | global_mask = g->ops.gr.get_sm_no_lock_down_hww_global_esr_mask(g); | ||
5548 | 5540 | ||
5549 | if (!sm_debugger_attached) { | 5541 | if (!sm_debugger_attached) { |
5550 | nvgpu_err(g, "sm hww global 0x%08x warp 0x%08x", | 5542 | nvgpu_err(g, "sm hww global 0x%08x warp 0x%08x", |
@@ -8387,9 +8379,7 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct warpstate *w_state) | |||
8387 | * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp | 8379 | * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp |
8388 | * masks. | 8380 | * masks. |
8389 | */ | 8381 | */ |
8390 | global_mask = gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f() | | 8382 | global_mask = g->ops.gr.get_sm_no_lock_down_hww_global_esr_mask(g); |
8391 | gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() | | ||
8392 | gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(); | ||
8393 | 8383 | ||
8394 | /* Lock down all SMs */ | 8384 | /* Lock down all SMs */ |
8395 | for (sm_id = 0; sm_id < gr->no_of_sm; sm_id++) { | 8385 | for (sm_id = 0; sm_id < gr->no_of_sm; sm_id++) { |
@@ -8499,3 +8489,19 @@ u32 gk20a_gr_get_sm_hww_global_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm) | |||
8499 | return hww_global_esr; | 8489 | return hww_global_esr; |
8500 | } | 8490 | } |
8501 | 8491 | ||
8492 | u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g) | ||
8493 | { | ||
8494 | /* | ||
8495 | * These three interrupts don't require locking down the SM. They can | ||
8496 | * be handled by usermode clients as they aren't fatal. Additionally, | ||
8497 | * usermode clients may wish to allow some warps to execute while others | ||
8498 | * are at breakpoints, as opposed to fatal errors where all warps should | ||
8499 | * halt. | ||
8500 | */ | ||
8501 | u32 global_esr_mask = | ||
8502 | gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f() | | ||
8503 | gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() | | ||
8504 | gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(); | ||
8505 | |||
8506 | return global_esr_mask; | ||
8507 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 3dbf5697..8230ba72 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -541,6 +541,7 @@ void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config); | |||
541 | bool gk20a_gr_sm_debugger_attached(struct gk20a *g); | 541 | bool gk20a_gr_sm_debugger_attached(struct gk20a *g); |
542 | void gk20a_gr_clear_sm_hww(struct gk20a *g, | 542 | void gk20a_gr_clear_sm_hww(struct gk20a *g, |
543 | u32 gpc, u32 tpc, u32 global_esr); | 543 | u32 gpc, u32 tpc, u32 global_esr); |
544 | u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); | ||
544 | 545 | ||
545 | #define gr_gk20a_elpg_protected_call(g, func) \ | 546 | #define gr_gk20a_elpg_protected_call(g, func) \ |
546 | ({ \ | 547 | ({ \ |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 3a1d579a..fecd487f 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1636,4 +1636,6 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1636 | gops->gr.resume_all_sms = gk20a_gr_resume_all_sms; | 1636 | gops->gr.resume_all_sms = gk20a_gr_resume_all_sms; |
1637 | gops->gr.get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr; | 1637 | gops->gr.get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr; |
1638 | gops->gr.get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr; | 1638 | gops->gr.get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr; |
1639 | gops->gr.get_sm_no_lock_down_hww_global_esr_mask = | ||
1640 | gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask; | ||
1639 | } | 1641 | } |