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-rw-r--r--drivers/gpu/nvgpu/gk20a/clk_gk20a.c10
-rw-r--r--drivers/gpu/nvgpu/gk20a/clk_gk20a.h4
2 files changed, 8 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c
index 517e8e49..41305e3e 100644
--- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c
@@ -415,11 +415,15 @@ struct clk *gk20a_clk_get(struct gk20a *g)
415{ 415{
416 if (!g->clk.tegra_clk) { 416 if (!g->clk.tegra_clk) {
417 struct clk *clk; 417 struct clk *clk;
418 char clk_dev_id[32];
419 struct device *dev = dev_from_gk20a(g);
418 420
419 clk = clk_get_sys("tegra_gk20a", "gpu"); 421 snprintf(clk_dev_id, 32, "tegra_%s", dev_name(dev));
422
423 clk = clk_get_sys(clk_dev_id, "gpu");
420 if (IS_ERR(clk)) { 424 if (IS_ERR(clk)) {
421 gk20a_err(dev_from_gk20a(g), 425 gk20a_err(dev, "fail to get tegra gpu clk %s/gpu\n",
422 "fail to get tegra gpu clk tegra_gk20a/gpu"); 426 clk_dev_id);
423 return NULL; 427 return NULL;
424 } 428 }
425 g->clk.tegra_clk = clk; 429 g->clk.tegra_clk = clk;
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
index debd6fbc..e6d14f74 100644
--- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h
@@ -59,13 +59,11 @@ struct clk_gk20a {
59 bool debugfs_set; 59 bool debugfs_set;
60}; 60};
61 61
62/* APIs used for separate HAL */
63struct clk *gk20a_clk_get(struct gk20a *g);
64
65/* APIs used for both GK20A and GM20B */ 62/* APIs used for both GK20A and GM20B */
66unsigned long gk20a_clk_get_rate(struct gk20a *g); 63unsigned long gk20a_clk_get_rate(struct gk20a *g);
67int gk20a_clk_set_rate(struct gk20a *g, unsigned long rate); 64int gk20a_clk_set_rate(struct gk20a *g, unsigned long rate);
68long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate); 65long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate);
66struct clk *gk20a_clk_get(struct gk20a *g);
69 67
70#define KHZ 1000 68#define KHZ 1000
71#define MHZ 1000000 69#define MHZ 1000000