diff options
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 141 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 48 |
2 files changed, 189 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index b7a52be0..250dc65c 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -158,10 +158,151 @@ void gr_gp10b_commit_global_pagepool(struct gk20a *g, | |||
158 | gr_gpcs_gcc_pagepool_total_pages_f(size), patch); | 158 | gr_gpcs_gcc_pagepool_total_pages_f(size), patch); |
159 | } | 159 | } |
160 | 160 | ||
161 | static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | ||
162 | struct zbc_entry *color_val, u32 index) | ||
163 | { | ||
164 | struct fifo_gk20a *f = &g->fifo; | ||
165 | struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; | ||
166 | u32 i; | ||
167 | unsigned long end_jiffies = jiffies + | ||
168 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
169 | u32 ret; | ||
170 | u32 zbc_c; | ||
171 | |||
172 | ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); | ||
173 | if (ret) { | ||
174 | gk20a_err(dev_from_gk20a(g), | ||
175 | "failed to disable gr engine activity\n"); | ||
176 | return ret; | ||
177 | } | ||
178 | |||
179 | ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); | ||
180 | if (ret) { | ||
181 | gk20a_err(dev_from_gk20a(g), | ||
182 | "failed to idle graphics\n"); | ||
183 | goto clean_up; | ||
184 | } | ||
185 | |||
186 | /* update l2 table */ | ||
187 | g->ops.ltc.set_zbc_color_entry(g, color_val, index); | ||
188 | |||
189 | /* update ds table */ | ||
190 | gk20a_writel(g, gr_ds_zbc_color_r_r(), | ||
191 | gr_ds_zbc_color_r_val_f(color_val->color_ds[0])); | ||
192 | gk20a_writel(g, gr_ds_zbc_color_g_r(), | ||
193 | gr_ds_zbc_color_g_val_f(color_val->color_ds[1])); | ||
194 | gk20a_writel(g, gr_ds_zbc_color_b_r(), | ||
195 | gr_ds_zbc_color_b_val_f(color_val->color_ds[2])); | ||
196 | gk20a_writel(g, gr_ds_zbc_color_a_r(), | ||
197 | gr_ds_zbc_color_a_val_f(color_val->color_ds[3])); | ||
198 | |||
199 | gk20a_writel(g, gr_ds_zbc_color_fmt_r(), | ||
200 | gr_ds_zbc_color_fmt_val_f(color_val->format)); | ||
201 | |||
202 | gk20a_writel(g, gr_ds_zbc_tbl_index_r(), | ||
203 | gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE)); | ||
204 | |||
205 | /* trigger the write */ | ||
206 | gk20a_writel(g, gr_ds_zbc_tbl_ld_r(), | ||
207 | gr_ds_zbc_tbl_ld_select_c_f() | | ||
208 | gr_ds_zbc_tbl_ld_action_write_f() | | ||
209 | gr_ds_zbc_tbl_ld_trigger_active_f()); | ||
210 | |||
211 | /* update local copy */ | ||
212 | for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { | ||
213 | gr->zbc_col_tbl[index].color_l2[i] = color_val->color_l2[i]; | ||
214 | gr->zbc_col_tbl[index].color_ds[i] = color_val->color_ds[i]; | ||
215 | } | ||
216 | gr->zbc_col_tbl[index].format = color_val->format; | ||
217 | gr->zbc_col_tbl[index].ref_cnt++; | ||
218 | |||
219 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_r_r(index), color_val->color_ds[0]); | ||
220 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), color_val->color_ds[1]); | ||
221 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), color_val->color_ds[2]); | ||
222 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), color_val->color_ds[3]); | ||
223 | zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + ALIGN(index, 4)); | ||
224 | zbc_c |= color_val->format << (index % 4) * 6; | ||
225 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + ALIGN(index, 4), zbc_c); | ||
226 | |||
227 | clean_up: | ||
228 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); | ||
229 | if (ret) { | ||
230 | gk20a_err(dev_from_gk20a(g), | ||
231 | "failed to enable gr engine activity\n"); | ||
232 | } | ||
233 | |||
234 | return ret; | ||
235 | } | ||
236 | |||
237 | static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | ||
238 | struct zbc_entry *depth_val, u32 index) | ||
239 | { | ||
240 | struct fifo_gk20a *f = &g->fifo; | ||
241 | struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; | ||
242 | unsigned long end_jiffies = jiffies + | ||
243 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
244 | u32 ret; | ||
245 | u32 zbc_z; | ||
246 | |||
247 | ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); | ||
248 | if (ret) { | ||
249 | gk20a_err(dev_from_gk20a(g), | ||
250 | "failed to disable gr engine activity\n"); | ||
251 | return ret; | ||
252 | } | ||
253 | |||
254 | ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); | ||
255 | if (ret) { | ||
256 | gk20a_err(dev_from_gk20a(g), | ||
257 | "failed to idle graphics\n"); | ||
258 | goto clean_up; | ||
259 | } | ||
260 | |||
261 | /* update l2 table */ | ||
262 | g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); | ||
263 | |||
264 | /* update ds table */ | ||
265 | gk20a_writel(g, gr_ds_zbc_z_r(), | ||
266 | gr_ds_zbc_z_val_f(depth_val->depth)); | ||
267 | |||
268 | gk20a_writel(g, gr_ds_zbc_z_fmt_r(), | ||
269 | gr_ds_zbc_z_fmt_val_f(depth_val->format)); | ||
270 | |||
271 | gk20a_writel(g, gr_ds_zbc_tbl_index_r(), | ||
272 | gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE)); | ||
273 | |||
274 | /* trigger the write */ | ||
275 | gk20a_writel(g, gr_ds_zbc_tbl_ld_r(), | ||
276 | gr_ds_zbc_tbl_ld_select_z_f() | | ||
277 | gr_ds_zbc_tbl_ld_action_write_f() | | ||
278 | gr_ds_zbc_tbl_ld_trigger_active_f()); | ||
279 | |||
280 | /* update local copy */ | ||
281 | gr->zbc_dep_tbl[index].depth = depth_val->depth; | ||
282 | gr->zbc_dep_tbl[index].format = depth_val->format; | ||
283 | gr->zbc_dep_tbl[index].ref_cnt++; | ||
284 | |||
285 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth); | ||
286 | zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + ALIGN(index, 4)); | ||
287 | zbc_z |= depth_val->format << (index % 4) * 6; | ||
288 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + ALIGN(index, 4), zbc_z); | ||
289 | |||
290 | clean_up: | ||
291 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); | ||
292 | if (ret) { | ||
293 | gk20a_err(dev_from_gk20a(g), | ||
294 | "failed to enable gr engine activity\n"); | ||
295 | } | ||
296 | |||
297 | return ret; | ||
298 | } | ||
299 | |||
161 | void gp10b_init_gr(struct gpu_ops *gops) | 300 | void gp10b_init_gr(struct gpu_ops *gops) |
162 | { | 301 | { |
163 | gm20b_init_gr(gops); | 302 | gm20b_init_gr(gops); |
164 | gops->gr.is_valid_class = gr_gp10b_is_valid_class; | 303 | gops->gr.is_valid_class = gr_gp10b_is_valid_class; |
165 | gops->gr.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager; | 304 | gops->gr.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager; |
166 | gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool; | 305 | gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool; |
306 | gops->gr.add_zbc_color = gr_gp10b_add_zbc_color; | ||
307 | gops->gr.add_zbc_depth = gr_gp10b_add_zbc_depth; | ||
167 | } | 308 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index ca4aa6bd..f2237a50 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | |||
@@ -2198,6 +2198,54 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) | |||
2198 | { | 2198 | { |
2199 | return 0x3fffff << 0; | 2199 | return 0x3fffff << 0; |
2200 | } | 2200 | } |
2201 | static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) | ||
2202 | { | ||
2203 | return 0x00418010 + i*4; | ||
2204 | } | ||
2205 | static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) | ||
2206 | { | ||
2207 | return (v & 0xffffffff) << 0; | ||
2208 | } | ||
2209 | static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) | ||
2210 | { | ||
2211 | return 0x0041804c + i*4; | ||
2212 | } | ||
2213 | static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) | ||
2214 | { | ||
2215 | return (v & 0xffffffff) << 0; | ||
2216 | } | ||
2217 | static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) | ||
2218 | { | ||
2219 | return 0x00418088 + i*4; | ||
2220 | } | ||
2221 | static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) | ||
2222 | { | ||
2223 | return (v & 0xffffffff) << 0; | ||
2224 | } | ||
2225 | static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) | ||
2226 | { | ||
2227 | return 0x004180c4 + i*4; | ||
2228 | } | ||
2229 | static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) | ||
2230 | { | ||
2231 | return (v & 0xffffffff) << 0; | ||
2232 | } | ||
2233 | static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) | ||
2234 | { | ||
2235 | return 0x00500100; | ||
2236 | } | ||
2237 | static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) | ||
2238 | { | ||
2239 | return 0x00418110 + i*4; | ||
2240 | } | ||
2241 | static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) | ||
2242 | { | ||
2243 | return (v & 0xffffffff) << 0; | ||
2244 | } | ||
2245 | static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) | ||
2246 | { | ||
2247 | return 0x0050014c; | ||
2248 | } | ||
2201 | static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) | 2249 | static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) |
2202 | { | 2250 | { |
2203 | return 0x00418810; | 2251 | return 0x00418810; |