summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--drivers/gpu/nvgpu/common/linux/ioctl_channel.c55
-rw-r--r--drivers/gpu/nvgpu/common/linux/ioctl_channel.h1
-rw-r--r--drivers/gpu/nvgpu/common/linux/ioctl_tsg.c4
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_gk20a.c8
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c8
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.h7
-rw-r--r--drivers/gpu/nvgpu/gk20a/tsg_gk20a.c8
7 files changed, 66 insertions, 25 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
index 9a867bcb..781a803e 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c
@@ -914,6 +914,48 @@ clean_up:
914 return ret; 914 return ret;
915} 915}
916 916
917/*
918 * Convert linux specific runlist level of the form NVGPU_RUNLIST_INTERLEAVE_LEVEL_*
919 * to common runlist level of the form NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_*
920 */
921u32 nvgpu_get_common_runlist_level(u32 level)
922{
923 switch (level) {
924 case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW:
925 return NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW;
926 case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
927 return NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM;
928 case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH:
929 return NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH;
930 default:
931 pr_err("%s: incorrect runlist level\n", __func__);
932 }
933
934 return level;
935}
936
937static int gk20a_ioctl_channel_set_runlist_interleave(struct channel_gk20a *ch,
938 u32 level)
939{
940 int err = 0;
941
942 err = gk20a_busy(ch->g);
943 if (err) {
944 nvgpu_err(ch->g, "failed to power on, %d", err);
945 goto fail;
946 }
947
948 level = nvgpu_get_common_runlist_level(level);
949 err = gk20a_channel_set_runlist_interleave(ch, level);
950
951 gk20a_idle(ch->g);
952 gk20a_channel_trace_sched_param(
953 trace_gk20a_channel_set_runlist_interleave, ch);
954
955fail:
956 return err;
957}
958
917long gk20a_channel_ioctl(struct file *filp, 959long gk20a_channel_ioctl(struct file *filp,
918 unsigned int cmd, unsigned long arg) 960 unsigned int cmd, unsigned long arg)
919{ 961{
@@ -1202,19 +1244,8 @@ long gk20a_channel_ioctl(struct file *filp,
1202 (struct nvgpu_channel_wdt_args *)buf); 1244 (struct nvgpu_channel_wdt_args *)buf);
1203 break; 1245 break;
1204 case NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE: 1246 case NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE:
1205 err = gk20a_busy(ch->g); 1247 err = gk20a_ioctl_channel_set_runlist_interleave(ch,
1206 if (err) {
1207 dev_err(dev,
1208 "%s: failed to host gk20a for ioctl cmd: 0x%x",
1209 __func__, cmd);
1210 break;
1211 }
1212 err = gk20a_channel_set_runlist_interleave(ch,
1213 ((struct nvgpu_runlist_interleave_args *)buf)->level); 1248 ((struct nvgpu_runlist_interleave_args *)buf)->level);
1214
1215 gk20a_idle(ch->g);
1216 gk20a_channel_trace_sched_param(
1217 trace_gk20a_channel_set_runlist_interleave, ch);
1218 break; 1249 break;
1219 case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE: 1250 case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE:
1220 err = gk20a_busy(ch->g); 1251 err = gk20a_busy(ch->g);
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.h b/drivers/gpu/nvgpu/common/linux/ioctl_channel.h
index c3cd11c7..48caf9df 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.h
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.h
@@ -31,4 +31,5 @@ extern const struct file_operations gk20a_event_id_ops;
31extern const struct file_operations gk20a_channel_ops; 31extern const struct file_operations gk20a_channel_ops;
32 32
33u32 nvgpu_event_id_to_ioctl_channel_event_id(u32 event_id); 33u32 nvgpu_event_id_to_ioctl_channel_event_id(u32 event_id);
34u32 nvgpu_get_common_runlist_level(u32 level);
34#endif 35#endif
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
index 681a5e66..eb223382 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
@@ -328,6 +328,7 @@ static int gk20a_tsg_ioctl_set_runlist_interleave(struct gk20a *g,
328{ 328{
329 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 329 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
330 struct gk20a_sched_ctrl *sched = &l->sched_ctrl; 330 struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
331 u32 level = arg->level;
331 int err; 332 int err;
332 333
333 gk20a_dbg(gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); 334 gk20a_dbg(gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
@@ -343,7 +344,8 @@ static int gk20a_tsg_ioctl_set_runlist_interleave(struct gk20a *g,
343 goto done; 344 goto done;
344 } 345 }
345 346
346 err = gk20a_tsg_set_runlist_interleave(tsg, arg->level); 347 level = nvgpu_get_common_runlist_level(level);
348 err = gk20a_tsg_set_runlist_interleave(tsg, level);
347 349
348 gk20a_idle(g); 350 gk20a_idle(g);
349done: 351done:
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 6c607ae2..229e3782 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -322,9 +322,9 @@ int gk20a_channel_set_runlist_interleave(struct channel_gk20a *ch,
322 } 322 }
323 323
324 switch (level) { 324 switch (level) {
325 case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW: 325 case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW:
326 case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM: 326 case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
327 case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH: 327 case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH:
328 ret = g->ops.fifo.set_runlist_interleave(g, ch->chid, 328 ret = g->ops.fifo.set_runlist_interleave(g, ch->chid,
329 false, 0, level); 329 false, 0, level);
330 break; 330 break;
@@ -858,7 +858,7 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g,
858 ch->has_timedout = false; 858 ch->has_timedout = false;
859 ch->wdt_enabled = true; 859 ch->wdt_enabled = true;
860 ch->obj_class = 0; 860 ch->obj_class = 0;
861 ch->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW; 861 ch->interleave_level = NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW;
862 ch->timeslice_us = g->timeslice_low_priority_us; 862 ch->timeslice_us = g->timeslice_low_priority_us;
863#ifdef CONFIG_TEGRA_19x_GPU 863#ifdef CONFIG_TEGRA_19x_GPU
864 memset(&ch->t19x, 0, sizeof(struct channel_t19x)); 864 memset(&ch->t19x, 0, sizeof(struct channel_t19x));
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 76995406..061ceba1 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -3048,7 +3048,7 @@ static u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f,
3048 bool prev_empty, 3048 bool prev_empty,
3049 u32 *entries_left) 3049 u32 *entries_left)
3050{ 3050{
3051 bool last_level = cur_level == NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH; 3051 bool last_level = cur_level == NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH;
3052 struct channel_gk20a *ch; 3052 struct channel_gk20a *ch;
3053 bool skip_next = false; 3053 bool skip_next = false;
3054 u32 chid, tsgid, count = 0; 3054 u32 chid, tsgid, count = 0;
@@ -4081,13 +4081,13 @@ u32 gk20a_fifo_pbdma_acquire_val(u64 timeout)
4081const char *gk20a_fifo_interleave_level_name(u32 interleave_level) 4081const char *gk20a_fifo_interleave_level_name(u32 interleave_level)
4082{ 4082{
4083 switch (interleave_level) { 4083 switch (interleave_level) {
4084 case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW: 4084 case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW:
4085 return "LOW"; 4085 return "LOW";
4086 4086
4087 case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM: 4087 case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
4088 return "MEDIUM"; 4088 return "MEDIUM";
4089 4089
4090 case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH: 4090 case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH:
4091 return "HIGH"; 4091 return "HIGH";
4092 4092
4093 default: 4093 default:
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index ea5d55a4..4c967e80 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -38,6 +38,13 @@
38struct gk20a_debug_output; 38struct gk20a_debug_output;
39struct mmu_fault_info; 39struct mmu_fault_info;
40 40
41enum {
42 NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW = 0,
43 NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM,
44 NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH,
45 NVGPU_FIFO_RUNLIST_INTERLEAVE_NUM_LEVELS,
46};
47
41#define MAX_RUNLIST_BUFFERS 2 48#define MAX_RUNLIST_BUFFERS 2
42 49
43#define FIFO_INVAL_ENGINE_ID ((u32)~0) 50#define FIFO_INVAL_ENGINE_ID ((u32)~0)
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
index badc7ef9..640174a6 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
@@ -229,9 +229,9 @@ int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level)
229 gk20a_dbg(gpu_dbg_sched, "tsgid=%u interleave=%u", tsg->tsgid, level); 229 gk20a_dbg(gpu_dbg_sched, "tsgid=%u interleave=%u", tsg->tsgid, level);
230 230
231 switch (level) { 231 switch (level) {
232 case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW: 232 case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW:
233 case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM: 233 case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
234 case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH: 234 case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH:
235 ret = g->ops.fifo.set_runlist_interleave(g, tsg->tsgid, 235 ret = g->ops.fifo.set_runlist_interleave(g, tsg->tsgid,
236 true, 0, level); 236 true, 0, level);
237 if (!ret) 237 if (!ret)
@@ -304,7 +304,7 @@ struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g)
304 304
305 tsg->tsg_gr_ctx = NULL; 305 tsg->tsg_gr_ctx = NULL;
306 tsg->vm = NULL; 306 tsg->vm = NULL;
307 tsg->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW; 307 tsg->interleave_level = NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW;
308 tsg->timeslice_us = 0; 308 tsg->timeslice_us = 0;
309 tsg->timeslice_timeout = 0; 309 tsg->timeslice_timeout = 0;
310 tsg->timeslice_scale = 0; 310 tsg->timeslice_scale = 0;