diff options
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_tsg.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 6 | ||||
-rw-r--r-- | include/uapi/linux/nvgpu.h | 9 |
4 files changed, 25 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c index 46bc5f59..cb876e23 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c | |||
@@ -30,6 +30,9 @@ | |||
30 | #include "ioctl_tsg.h" | 30 | #include "ioctl_tsg.h" |
31 | #include "ioctl_channel.h" | 31 | #include "ioctl_channel.h" |
32 | #include "os_linux.h" | 32 | #include "os_linux.h" |
33 | #ifdef CONFIG_TEGRA_19x_GPU | ||
34 | #include "tsg_t19x.h" | ||
35 | #endif | ||
33 | 36 | ||
34 | struct tsg_private { | 37 | struct tsg_private { |
35 | struct gk20a *g; | 38 | struct gk20a *g; |
@@ -469,9 +472,13 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd, | |||
469 | } | 472 | } |
470 | 473 | ||
471 | default: | 474 | default: |
475 | #ifdef CONFIG_TEGRA_19x_GPU | ||
476 | err = t19x_tsg_ioctl_handler(g, tsg, cmd, buf); | ||
477 | #else | ||
472 | nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", | 478 | nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", |
473 | cmd); | 479 | cmd); |
474 | err = -ENOTTY; | 480 | err = -ENOTTY; |
481 | #endif | ||
475 | break; | 482 | break; |
476 | } | 483 | } |
477 | 484 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index bca201cf..87923537 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -858,6 +858,10 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, | |||
858 | ch->obj_class = 0; | 858 | ch->obj_class = 0; |
859 | ch->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW; | 859 | ch->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW; |
860 | ch->timeslice_us = g->timeslice_low_priority_us; | 860 | ch->timeslice_us = g->timeslice_low_priority_us; |
861 | #ifdef CONFIG_TEGRA_19x_GPU | ||
862 | memset(&ch->t19x, 0, sizeof(struct channel_t19x)); | ||
863 | #endif | ||
864 | |||
861 | 865 | ||
862 | /* The channel is *not* runnable at this point. It still needs to have | 866 | /* The channel is *not* runnable at this point. It still needs to have |
863 | * an address space bound and allocate a gpfifo and grctx. */ | 867 | * an address space bound and allocate a gpfifo and grctx. */ |
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index 380440b9..46a9b0a7 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -36,6 +36,9 @@ struct fifo_profile_gk20a; | |||
36 | #include "mm_gk20a.h" | 36 | #include "mm_gk20a.h" |
37 | #include "gr_gk20a.h" | 37 | #include "gr_gk20a.h" |
38 | #include "fence_gk20a.h" | 38 | #include "fence_gk20a.h" |
39 | #ifdef CONFIG_TEGRA_19x_GPU | ||
40 | #include "channel_t19x.h" | ||
41 | #endif | ||
39 | 42 | ||
40 | struct notification { | 43 | struct notification { |
41 | struct { | 44 | struct { |
@@ -276,6 +279,9 @@ struct channel_gk20a { | |||
276 | u32 runlist_id; | 279 | u32 runlist_id; |
277 | 280 | ||
278 | bool is_privileged_channel; | 281 | bool is_privileged_channel; |
282 | #ifdef CONFIG_TEGRA_19x_GPU | ||
283 | struct channel_t19x t19x; | ||
284 | #endif | ||
279 | }; | 285 | }; |
280 | 286 | ||
281 | static inline struct channel_gk20a * | 287 | static inline struct channel_gk20a * |
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 8b29a3ae..c34a7e83 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -970,11 +970,18 @@ struct nvgpu_gpu_set_event_filter_args { | |||
970 | #define NVGPU_IOCTL_TSG_GET_TIMESLICE \ | 970 | #define NVGPU_IOCTL_TSG_GET_TIMESLICE \ |
971 | _IOR(NVGPU_TSG_IOCTL_MAGIC, 10, struct nvgpu_timeslice_args) | 971 | _IOR(NVGPU_TSG_IOCTL_MAGIC, 10, struct nvgpu_timeslice_args) |
972 | 972 | ||
973 | |||
974 | #ifdef CONFIG_TEGRA_19x_GPU | ||
975 | #define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \ | ||
976 | NVGPU_TSG_IOCTL_MAX_ARG | ||
977 | #define NVGPU_TSG_IOCTL_LAST \ | ||
978 | _IOC_NR(NVGPU_TSG_IOCTL_MAX) | ||
979 | #else | ||
973 | #define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \ | 980 | #define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \ |
974 | sizeof(struct nvgpu_event_id_ctrl_args) | 981 | sizeof(struct nvgpu_event_id_ctrl_args) |
975 | #define NVGPU_TSG_IOCTL_LAST \ | 982 | #define NVGPU_TSG_IOCTL_LAST \ |
976 | _IOC_NR(NVGPU_IOCTL_TSG_GET_TIMESLICE) | 983 | _IOC_NR(NVGPU_IOCTL_TSG_GET_TIMESLICE) |
977 | 984 | #endif | |
978 | 985 | ||
979 | /* | 986 | /* |
980 | * /dev/nvhost-dbg-gpu device | 987 | * /dev/nvhost-dbg-gpu device |