diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 20 |
2 files changed, 22 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index fea46a0e..e12576d2 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics FIFO (gr host) | 2 | * GK20A Graphics FIFO (gr host) |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -1647,28 +1647,32 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1647 | * Disable the channel/TSG from hw and increment syncpoints. | 1647 | * Disable the channel/TSG from hw and increment syncpoints. |
1648 | */ | 1648 | */ |
1649 | if (tsg) { | 1649 | if (tsg) { |
1650 | if (!g->fifo.deferred_reset_pending) { | 1650 | if (g->fifo.deferred_reset_pending) { |
1651 | gk20a_disable_tsg(tsg); | ||
1652 | } else { | ||
1651 | if (!fake_fault) | 1653 | if (!fake_fault) |
1652 | gk20a_fifo_set_ctx_mmu_error_tsg(g, | 1654 | gk20a_fifo_set_ctx_mmu_error_tsg(g, |
1653 | tsg); | 1655 | tsg); |
1654 | verbose = gk20a_fifo_error_tsg(g, tsg); | 1656 | verbose = gk20a_fifo_error_tsg(g, tsg); |
1657 | gk20a_fifo_abort_tsg(g, tsg->tsgid, false); | ||
1655 | } | 1658 | } |
1656 | gk20a_fifo_abort_tsg(g, tsg->tsgid, false); | ||
1657 | 1659 | ||
1658 | /* put back the ref taken early above */ | 1660 | /* put back the ref taken early above */ |
1659 | if (refch) | 1661 | if (refch) |
1660 | gk20a_channel_put(ch); | 1662 | gk20a_channel_put(ch); |
1661 | } else if (ch) { | 1663 | } else if (ch) { |
1662 | if (refch) { | 1664 | if (refch) { |
1663 | if (!g->fifo.deferred_reset_pending) { | 1665 | if (g->fifo.deferred_reset_pending) { |
1666 | g->ops.fifo.disable_channel(ch); | ||
1667 | } else { | ||
1664 | if (!fake_fault) | 1668 | if (!fake_fault) |
1665 | gk20a_fifo_set_ctx_mmu_error_ch( | 1669 | gk20a_fifo_set_ctx_mmu_error_ch( |
1666 | g, refch); | 1670 | g, refch); |
1667 | 1671 | ||
1668 | verbose = gk20a_fifo_error_ch(g, | 1672 | verbose = gk20a_fifo_error_ch(g, |
1669 | refch); | 1673 | refch); |
1674 | gk20a_channel_abort(ch, false); | ||
1670 | } | 1675 | } |
1671 | gk20a_channel_abort(ch, false); | ||
1672 | gk20a_channel_put(ch); | 1676 | gk20a_channel_put(ch); |
1673 | } else { | 1677 | } else { |
1674 | nvgpu_err(g, | 1678 | nvgpu_err(g, |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 97ab7aab..feed2002 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -1049,19 +1049,25 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, | |||
1049 | #endif | 1049 | #endif |
1050 | 1050 | ||
1051 | if (tsg) { | 1051 | if (tsg) { |
1052 | if (!g->fifo.deferred_reset_pending && | 1052 | if (g->fifo.deferred_reset_pending) { |
1053 | rc_type == RC_TYPE_MMU_FAULT) | 1053 | gk20a_disable_tsg(tsg); |
1054 | gk20a_fifo_set_ctx_mmu_error_tsg(g, tsg); | 1054 | } else { |
1055 | if (rc_type == RC_TYPE_MMU_FAULT) | ||
1056 | gk20a_fifo_set_ctx_mmu_error_tsg(g, tsg); | ||
1055 | 1057 | ||
1056 | gk20a_fifo_abort_tsg(g, tsg->tsgid, false); | 1058 | gk20a_fifo_abort_tsg(g, tsg->tsgid, false); |
1059 | } | ||
1057 | if (refch) | 1060 | if (refch) |
1058 | gk20a_channel_put(refch); | 1061 | gk20a_channel_put(refch); |
1059 | } else if (refch) { | 1062 | } else if (refch) { |
1060 | if (!g->fifo.deferred_reset_pending && | 1063 | if (g->fifo.deferred_reset_pending) { |
1061 | rc_type == RC_TYPE_MMU_FAULT) | 1064 | g->ops.fifo.disable_channel(refch); |
1065 | } else { | ||
1066 | if (rc_type == RC_TYPE_MMU_FAULT) | ||
1062 | gk20a_fifo_set_ctx_mmu_error_ch(g, refch); | 1067 | gk20a_fifo_set_ctx_mmu_error_ch(g, refch); |
1063 | 1068 | ||
1064 | gk20a_channel_abort(refch, false); | 1069 | gk20a_channel_abort(refch, false); |
1070 | } | ||
1065 | gk20a_channel_put(refch); | 1071 | gk20a_channel_put(refch); |
1066 | } else { | 1072 | } else { |
1067 | nvgpu_err(g, "id unknown, abort runlist"); | 1073 | nvgpu_err(g, "id unknown, abort runlist"); |