diff options
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/fuse.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/fuse.h | 16 |
7 files changed, 44 insertions, 43 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/fuse.c b/drivers/gpu/nvgpu/common/linux/fuse.c index 993cbc5a..27851f92 100644 --- a/drivers/gpu/nvgpu/common/linux/fuse.c +++ b/drivers/gpu/nvgpu/common/linux/fuse.c | |||
@@ -15,7 +15,7 @@ | |||
15 | 15 | ||
16 | #include <nvgpu/fuse.h> | 16 | #include <nvgpu/fuse.h> |
17 | 17 | ||
18 | int nvgpu_tegra_get_gpu_speedo_id(void) | 18 | int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g) |
19 | { | 19 | { |
20 | return tegra_sku_info.gpu_speedo_id; | 20 | return tegra_sku_info.gpu_speedo_id; |
21 | } | 21 | } |
@@ -24,32 +24,32 @@ int nvgpu_tegra_get_gpu_speedo_id(void) | |||
24 | * Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100 | 24 | * Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100 |
25 | * Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100 | 25 | * Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100 |
26 | */ | 26 | */ |
27 | void nvgpu_tegra_fuse_write_bypass(u32 val) | 27 | void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val) |
28 | { | 28 | { |
29 | tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0); | 29 | tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0); |
30 | } | 30 | } |
31 | 31 | ||
32 | void nvgpu_tegra_fuse_write_access_sw(u32 val) | 32 | void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val) |
33 | { | 33 | { |
34 | tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0); | 34 | tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0); |
35 | } | 35 | } |
36 | 36 | ||
37 | void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val) | 37 | void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val) |
38 | { | 38 | { |
39 | tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0); | 39 | tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0); |
40 | } | 40 | } |
41 | 41 | ||
42 | void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val) | 42 | void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val) |
43 | { | 43 | { |
44 | tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0); | 44 | tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0); |
45 | } | 45 | } |
46 | 46 | ||
47 | int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val) | 47 | int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val) |
48 | { | 48 | { |
49 | return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val); | 49 | return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val); |
50 | } | 50 | } |
51 | 51 | ||
52 | int nvgpu_tegra_fuse_read_reserved_calib(u32 *val) | 52 | int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val) |
53 | { | 53 | { |
54 | return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val); | 54 | return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val); |
55 | } | 55 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 22501c64..027d4fb6 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -258,12 +258,13 @@ static inline int fuse_get_gpcpll_adc_intercept_uv(u32 val) | |||
258 | return ((val >> 4) & 0x3ff) * 1000 + ((val >> 0) & 0xf) * 100; | 258 | return ((val >> 4) & 0x3ff) * 1000 + ((val >> 0) & 0xf) * 100; |
259 | } | 259 | } |
260 | 260 | ||
261 | static int nvgpu_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv) | 261 | static int nvgpu_fuse_calib_gpcpll_get_adc(struct gk20a *g, |
262 | int *slope_uv, int *intercept_uv) | ||
262 | { | 263 | { |
263 | u32 val; | 264 | u32 val; |
264 | int ret; | 265 | int ret; |
265 | 266 | ||
266 | ret = nvgpu_tegra_fuse_read_reserved_calib(&val); | 267 | ret = nvgpu_tegra_fuse_read_reserved_calib(g, &val); |
267 | if (ret) | 268 | if (ret) |
268 | return ret; | 269 | return ret; |
269 | 270 | ||
@@ -276,9 +277,9 @@ static int nvgpu_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv) | |||
276 | } | 277 | } |
277 | 278 | ||
278 | #ifdef CONFIG_TEGRA_USE_NA_GPCPLL | 279 | #ifdef CONFIG_TEGRA_USE_NA_GPCPLL |
279 | static bool nvgpu_fuse_can_use_na_gpcpll(void) | 280 | static bool nvgpu_fuse_can_use_na_gpcpll(struct gk20a *g) |
280 | { | 281 | { |
281 | return nvgpu_tegra_get_gpu_speedo_id(); | 282 | return nvgpu_tegra_get_gpu_speedo_id(g); |
282 | } | 283 | } |
283 | #endif | 284 | #endif |
284 | 285 | ||
@@ -291,7 +292,7 @@ static int clk_config_calibration_params(struct gk20a *g) | |||
291 | int slope, offs; | 292 | int slope, offs; |
292 | struct pll_parms *p = &gpc_pll_params; | 293 | struct pll_parms *p = &gpc_pll_params; |
293 | 294 | ||
294 | if (!nvgpu_fuse_calib_gpcpll_get_adc(&slope, &offs)) { | 295 | if (!nvgpu_fuse_calib_gpcpll_get_adc(g, &slope, &offs)) { |
295 | p->uvdet_slope = slope; | 296 | p->uvdet_slope = slope; |
296 | p->uvdet_offs = offs; | 297 | p->uvdet_offs = offs; |
297 | } | 298 | } |
@@ -1186,7 +1187,7 @@ int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1186 | */ | 1187 | */ |
1187 | clk_config_calibration_params(g); | 1188 | clk_config_calibration_params(g); |
1188 | #ifdef CONFIG_TEGRA_USE_NA_GPCPLL | 1189 | #ifdef CONFIG_TEGRA_USE_NA_GPCPLL |
1189 | if (nvgpu_fuse_can_use_na_gpcpll()) { | 1190 | if (nvgpu_fuse_can_use_na_gpcpll(g)) { |
1190 | /* NA mode is supported only at max update rate 38.4 MHz */ | 1191 | /* NA mode is supported only at max update rate 38.4 MHz */ |
1191 | BUG_ON(clk->gpc_pll.clk_in != gpc_pll_params.max_u); | 1192 | BUG_ON(clk->gpc_pll.clk_in != gpc_pll_params.max_u); |
1192 | clk->gpc_pll.mode = GPC_PLL_MODE_DVFS; | 1193 | clk->gpc_pll.mode = GPC_PLL_MODE_DVFS; |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index f60d880d..87cf3f01 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -548,18 +548,18 @@ static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | |||
548 | 548 | ||
549 | static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 549 | static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
550 | { | 550 | { |
551 | nvgpu_tegra_fuse_write_bypass(0x1); | 551 | nvgpu_tegra_fuse_write_bypass(g, 0x1); |
552 | nvgpu_tegra_fuse_write_access_sw(0x0); | 552 | nvgpu_tegra_fuse_write_access_sw(g, 0x0); |
553 | 553 | ||
554 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) { | 554 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) { |
555 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); | 555 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0); |
556 | nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x1); | 556 | nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(g, 0x1); |
557 | } else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) { | 557 | } else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) { |
558 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1); | 558 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1); |
559 | nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0); | 559 | nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(g, 0x0); |
560 | } else { | 560 | } else { |
561 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); | 561 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0); |
562 | nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0); | 562 | nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(g, 0x0); |
563 | } | 563 | } |
564 | } | 564 | } |
565 | 565 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 98cd3906..b85e72a0 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -265,13 +265,12 @@ static void pmu_dump_security_fuses_gm20b(struct gk20a *g) | |||
265 | { | 265 | { |
266 | u32 val; | 266 | u32 val; |
267 | 267 | ||
268 | nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", | 268 | nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x", |
269 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | 269 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); |
270 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", | 270 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x", |
271 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | 271 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); |
272 | nvgpu_tegra_fuse_read_gcplex_config_fuse(&val); | 272 | nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); |
273 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", | 273 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); |
274 | val); | ||
275 | } | 274 | } |
276 | 275 | ||
277 | void gm20b_init_pmu_ops(struct gk20a *g) | 276 | void gm20b_init_pmu_ops(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index d2b86e51..05fbeb21 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1600,15 +1600,15 @@ static void gr_gp10b_init_cyclestats(struct gk20a *g) | |||
1600 | 1600 | ||
1601 | static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 1601 | static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
1602 | { | 1602 | { |
1603 | nvgpu_tegra_fuse_write_bypass(0x1); | 1603 | nvgpu_tegra_fuse_write_bypass(g, 0x1); |
1604 | nvgpu_tegra_fuse_write_access_sw(0x0); | 1604 | nvgpu_tegra_fuse_write_access_sw(g, 0x0); |
1605 | 1605 | ||
1606 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) | 1606 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) |
1607 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x2); | 1607 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x2); |
1608 | else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) | 1608 | else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) |
1609 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1); | 1609 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1); |
1610 | else | 1610 | else |
1611 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); | 1611 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0); |
1612 | } | 1612 | } |
1613 | 1613 | ||
1614 | static void gr_gp10b_get_access_map(struct gk20a *g, | 1614 | static void gr_gp10b_get_access_map(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index e9a9b922..da8044cd 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -378,13 +378,12 @@ static void pmu_dump_security_fuses_gp10b(struct gk20a *g) | |||
378 | { | 378 | { |
379 | u32 val; | 379 | u32 val; |
380 | 380 | ||
381 | nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", | 381 | nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x", |
382 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | 382 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); |
383 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", | 383 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x", |
384 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | 384 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); |
385 | nvgpu_tegra_fuse_read_gcplex_config_fuse(&val); | 385 | nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); |
386 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", | 386 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); |
387 | val); | ||
388 | } | 387 | } |
389 | 388 | ||
390 | static bool gp10b_is_pmu_supported(struct gk20a *g) | 389 | static bool gp10b_is_pmu_supported(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/fuse.h b/drivers/gpu/nvgpu/include/nvgpu/fuse.h index 3650fd58..c10ece1d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/fuse.h +++ b/drivers/gpu/nvgpu/include/nvgpu/fuse.h | |||
@@ -13,13 +13,15 @@ | |||
13 | #ifndef __NVGPU_FUSE_H__ | 13 | #ifndef __NVGPU_FUSE_H__ |
14 | #define __NVGPU_FUSE_H__ | 14 | #define __NVGPU_FUSE_H__ |
15 | 15 | ||
16 | int nvgpu_tegra_get_gpu_speedo_id(void); | 16 | struct gk20a; |
17 | 17 | ||
18 | void nvgpu_tegra_fuse_write_bypass(u32 val); | 18 | int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g); |
19 | void nvgpu_tegra_fuse_write_access_sw(u32 val); | 19 | |
20 | void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val); | 20 | void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val); |
21 | void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val); | 21 | void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val); |
22 | int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val); | 22 | void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val); |
23 | int nvgpu_tegra_fuse_read_reserved_calib(u32 *val); | 23 | void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val); |
24 | int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val); | ||
25 | int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val); | ||
24 | 26 | ||
25 | #endif | 27 | #endif |